1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
7 /* Tegra30 Clock control functions */
12 #include <asm/arch/clock.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra30 has muxes for the
21 * peripheral clocks, and in most cases there are four options for the clock
22 * source. This gives us a clock 'type' and exploits what commonality exists
25 * Letters are obvious, except for T which means CLK_M, and S which means the
26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
27 * datasheet) and PLL_M are different things. The former is the basic
28 * clock supplied to the SOC from an external oscillator. The latter is the
31 * See definitions in clock_id in the header file.
34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
35 CLOCK_TYPE_MCPA, /* and so on */
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
51 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
55 * Clock source mux for each clock type. This just converts our enum into
56 * a list of mux sources for use by the code.
59 * The extra column in each clock source array is used to store the mask
60 * bits in its register for the source.
62 #define CLK(x) CLOCK_ID_ ## x
63 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
65 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
89 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
91 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
100 * Clock type for each peripheral clock source. We put the name in each
101 * record just so it is easy to match things up
103 #define TYPE(name, type) type
104 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
106 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
107 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
108 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
109 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
110 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
111 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
112 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
113 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
116 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
117 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
118 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
119 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
120 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
121 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
122 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
123 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
126 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
127 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
128 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
130 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
131 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
132 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
133 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
136 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
137 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
138 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
139 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
140 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
141 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
142 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
143 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
146 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
147 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
148 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
149 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
150 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
151 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
152 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
153 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
156 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
157 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
158 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
159 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
161 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
162 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
163 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
166 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
167 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
168 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
169 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
170 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
173 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
175 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
176 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
177 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
179 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
180 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
181 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
182 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
183 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
186 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
187 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
188 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
189 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
190 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
191 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
192 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
193 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
196 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
197 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
198 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
199 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
200 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
201 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
203 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
211 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
216 * This array translates a periph_id to a periphc_internal_id
218 * Not present/matched up:
219 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
220 * SPDIF - which is both 0x08 and 0x0c
223 #define NONE(name) (-1)
224 #define OFFSET(name, value) PERIPHC_ ## name
225 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
234 PERIPHC_UART2, /* and vfir 0x68 */
239 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
266 /* Middle word: 63:32 */
288 PERIPHC_TVO, /* also CVE 0x40 */
306 /* Upper word 95:64 */
389 NONE(RESERVED0_PCIERX0),
390 NONE(RESERVED1_PCIERX1),
391 NONE(RESERVED2_PCIERX2),
392 NONE(RESERVED3_PCIERX3),
393 NONE(RESERVED4_PCIERX4),
394 NONE(RESERVED5_PCIERX5),
398 NONE(RESERVED6_PCIE2),
400 NONE(RESERVED8_HDMI),
401 NONE(RESERVED9_SATA),
402 NONE(RESERVED10_MIPI),
408 * PLL divider shift/mask tables for all PLL IDs.
410 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
412 * T30: some deviations from T2x.
413 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
414 * If lock_ena or lock_det are >31, they're not used in that PLL.
417 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
418 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
419 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
420 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
421 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
422 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
423 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
424 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
425 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
426 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
427 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
428 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
429 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
430 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
431 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
432 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
433 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
434 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
438 * Get the oscillator frequency, from the corresponding hardware configuration
439 * field. Note that T30 supports 3 new higher freqs, but we map back
440 * to the old T20 freqs. Support for the higher oscillators is TBD.
442 enum clock_osc_freq clock_get_osc_freq(void)
444 struct clk_rst_ctlr *clkrst =
445 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
448 reg = readl(&clkrst->crc_osc_ctrl);
449 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
451 if (reg & 1) /* one of the newer freqs */
452 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
454 return reg >> 2; /* Map to most common (T20) freqs */
457 /* Returns a pointer to the clock source register for a peripheral */
458 u32 *get_periph_source_reg(enum periph_id periph_id)
460 struct clk_rst_ctlr *clkrst =
461 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
462 enum periphc_internal_id internal_id;
464 /* Coresight is a special case */
465 if (periph_id == PERIPH_ID_CSI)
466 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
468 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
469 internal_id = periph_id_to_internal_id[periph_id];
470 assert(internal_id != -1);
471 if (internal_id >= PERIPHC_VW_FIRST) {
472 internal_id -= PERIPHC_VW_FIRST;
473 return &clkrst->crc_clk_src_vw[internal_id];
475 return &clkrst->crc_clk_src[internal_id];
478 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
479 int *divider_bits, int *type)
481 enum periphc_internal_id internal_id;
483 if (!clock_periph_id_isvalid(periph_id))
486 internal_id = periph_id_to_internal_id[periph_id];
487 if (!periphc_internal_id_isvalid(internal_id))
490 *type = clock_periph_type[internal_id];
491 if (!clock_type_id_isvalid(*type))
494 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
496 if (*type == CLOCK_TYPE_PCMT16)
504 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
506 enum periphc_internal_id internal_id;
509 if (!clock_periph_id_isvalid(periph_id))
510 return CLOCK_ID_NONE;
512 internal_id = periph_id_to_internal_id[periph_id];
513 if (!periphc_internal_id_isvalid(internal_id))
514 return CLOCK_ID_NONE;
516 type = clock_periph_type[internal_id];
517 if (!clock_type_id_isvalid(type))
518 return CLOCK_ID_NONE;
520 return clock_source[type][source];
524 * Given a peripheral ID and the required source clock, this returns which
525 * value should be programmed into the source mux for that peripheral.
527 * There is special code here to handle the one source type with 5 sources.
529 * @param periph_id peripheral to start
530 * @param source PLL id of required parent clock
531 * @param mux_bits Set to number of bits in mux register: 2 or 4
532 * @param divider_bits Set to number of divider bits (8 or 16)
533 * @return mux value (0-4, or -1 if not found)
535 int get_periph_clock_source(enum periph_id periph_id,
536 enum clock_id parent, int *mux_bits, int *divider_bits)
538 enum clock_type_id type;
541 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
544 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
545 if (clock_source[type][mux] == parent)
548 /* if we get here, either us or the caller has made a mistake */
549 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
554 void clock_set_enable(enum periph_id periph_id, int enable)
556 struct clk_rst_ctlr *clkrst =
557 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
561 /* Enable/disable the clock to this peripheral */
562 assert(clock_periph_id_isvalid(periph_id));
563 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
564 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
566 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
569 reg |= PERIPH_MASK(periph_id);
571 reg &= ~PERIPH_MASK(periph_id);
575 void reset_set_enable(enum periph_id periph_id, int enable)
577 struct clk_rst_ctlr *clkrst =
578 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
582 /* Enable/disable reset to the peripheral */
583 assert(clock_periph_id_isvalid(periph_id));
584 if (periph_id < PERIPH_ID_VW_FIRST)
585 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
587 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
590 reg |= PERIPH_MASK(periph_id);
592 reg &= ~PERIPH_MASK(periph_id);
596 #if CONFIG_IS_ENABLED(OF_CONTROL)
598 * Convert a device tree clock ID to our peripheral ID. They are mostly
599 * the same but we are very cautious so we check that a valid clock ID is
602 * @param clk_id Clock ID according to tegra30 device tree binding
603 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
605 enum periph_id clk_id_to_periph_id(int clk_id)
607 if (clk_id > PERIPH_ID_COUNT)
608 return PERIPH_ID_NONE;
611 case PERIPH_ID_RESERVED3:
612 case PERIPH_ID_RESERVED4:
613 case PERIPH_ID_RESERVED16:
614 case PERIPH_ID_RESERVED24:
615 case PERIPH_ID_RESERVED35:
616 case PERIPH_ID_RESERVED43:
617 case PERIPH_ID_RESERVED45:
618 case PERIPH_ID_RESERVED56:
619 case PERIPH_ID_PCIEXCLK:
620 case PERIPH_ID_RESERVED76:
621 case PERIPH_ID_RESERVED77:
622 case PERIPH_ID_RESERVED78:
623 case PERIPH_ID_RESERVED83:
624 case PERIPH_ID_RESERVED89:
625 case PERIPH_ID_RESERVED91:
626 case PERIPH_ID_RESERVED93:
627 case PERIPH_ID_RESERVED94:
628 case PERIPH_ID_RESERVED95:
629 return PERIPH_ID_NONE;
634 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
636 void clock_early_init(void)
638 tegra30_set_up_pllp();
641 void arch_timer_init(void)
645 #define PMC_SATA_PWRGT 0x1ac
646 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
647 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
649 #define PLLE_SS_CNTL 0x68
650 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
651 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
652 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
653 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
654 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
655 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
657 #define PLLE_BASE 0x0e8
658 #define PLLE_BASE_ENABLE_CML (1 << 31)
659 #define PLLE_BASE_ENABLE (1 << 30)
660 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
661 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
662 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
665 #define PLLE_MISC 0x0ec
666 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
667 #define PLLE_MISC_PLL_READY (1 << 15)
668 #define PLLE_MISC_LOCK (1 << 11)
669 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
670 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
672 static int tegra_plle_train(void)
674 unsigned int timeout = 2000;
677 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
678 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
679 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
681 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
682 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
683 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
685 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
686 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
687 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
690 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
691 if (value & PLLE_MISC_PLL_READY)
698 pr_err("timeout waiting for PLLE to become ready");
705 int tegra_plle_enable(void)
707 unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
711 /* disable PLLE clock */
712 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
713 value &= ~PLLE_BASE_ENABLE_CML;
714 value &= ~PLLE_BASE_ENABLE;
715 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
717 /* clear lock enable and setup field */
718 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
719 value &= ~PLLE_MISC_LOCK_ENABLE;
720 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
721 value &= ~PLLE_MISC_SETUP_EXT(0x3);
722 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
724 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
725 if ((value & PLLE_MISC_PLL_READY) == 0) {
726 err = tegra_plle_train();
728 pr_err("failed to train PLLE: %d", err);
734 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
736 value &= ~PLLE_BASE_PLDIV_CML(0x0f);
737 value |= PLLE_BASE_PLDIV_CML(cpcon);
739 value &= ~PLLE_BASE_PLDIV(0x3f);
740 value |= PLLE_BASE_PLDIV(p);
742 value &= ~PLLE_BASE_NDIV(0xff);
743 value |= PLLE_BASE_NDIV(n);
745 value &= ~PLLE_BASE_MDIV(0xff);
746 value |= PLLE_BASE_MDIV(m);
748 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
750 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
751 value |= PLLE_MISC_SETUP_BASE(0x7);
752 value |= PLLE_MISC_LOCK_ENABLE;
753 value |= PLLE_MISC_SETUP_EXT(0);
754 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
756 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
757 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
758 PLLE_SS_CNTL_BYPASS_SS;
759 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
761 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
762 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
763 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
766 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
767 if (value & PLLE_MISC_LOCK)
774 pr_err("timeout waiting for PLLE to lock");
780 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
781 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
782 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
784 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
785 value |= PLLE_SS_CNTL_SSCINC(0x01);
787 value &= ~PLLE_SS_CNTL_SSCBYP;
788 value &= ~PLLE_SS_CNTL_INTERP_RESET;
789 value &= ~PLLE_SS_CNTL_BYPASS_SS;
791 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
792 value |= PLLE_SS_CNTL_SSCMAX(0x24);
793 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
798 struct periph_clk_init periph_clk_init_table[] = {
799 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
800 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
801 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
802 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
803 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
804 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
805 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
806 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
807 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
808 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
809 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
810 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
811 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
812 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
813 { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
814 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
815 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
816 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
817 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },