1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2020
4 * NVIDIA Corporation <www.nvidia.com>
7 /* Tegra210 Clock control functions */
12 #include <asm/cache.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sysctr.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <asm/arch-tegra/timer.h>
23 * Clock types that we can use as a source. The Tegra210 has muxes for the
24 * peripheral clocks, and in most cases there are four options for the clock
25 * source. This gives us a clock 'type' and exploits what commonality exists
28 * Letters are obvious, except for T which means CLK_M, and S which means the
29 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
30 * datasheet) and PLL_M are different things. The former is the basic
31 * clock supplied to the SOC from an external oscillator. The latter is the
34 * See definitions in clock_id in the header file.
37 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
38 CLOCK_TYPE_MCPA, /* and so on */
52 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
55 CLOCK_TYPE_MCPTM2C2C3,
57 CLOCK_TYPE_AC2CC3P_TS2,
58 CLOCK_TYPE_PC01C00_C42C41TC40,
61 CLOCK_TYPE_NONE = -1, /* invalid clock type */
65 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
69 * Clock source mux for each clock type. This just converts our enum into
70 * a list of mux sources for use by the code.
73 * The extra column in each clock source array is used to store the mask
74 * bits in its register for the source.
76 #define CLK(x) CLOCK_ID_ ## x
77 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
78 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
79 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
82 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
85 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
88 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
90 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
91 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
93 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
94 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
96 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
97 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
99 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
100 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
102 { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
103 CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
105 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
106 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
109 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
110 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
113 /* Additional clock types on Tegra114+ */
114 /* CLOCK_TYPE_PC2CC3M */
115 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
116 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
118 /* CLOCK_TYPE_PC2CC3S_T */
119 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
120 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
122 /* CLOCK_TYPE_PC2CC3M_T */
123 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
124 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
126 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
127 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
128 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
130 /* CLOCK_TYPE_MC2CC3P_A */
131 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
132 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
135 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
136 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
138 /* CLOCK_TYPE_MCPTM2C2C3 */
139 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
140 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
142 /* CLOCK_TYPE_PC2CC3T_S */
143 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
144 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
146 /* CLOCK_TYPE_AC2CC3P_TS2 */
147 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
148 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
150 /* CLOCK_TYPE_PC01C00_C42C41TC40 */
151 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
152 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
157 * Clock type for each peripheral clock source. We put the name in each
158 * record just so it is easy to match things up
160 #define TYPE(name, type) type
161 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
163 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
164 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
165 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
166 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
167 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
168 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
169 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
170 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
173 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
174 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
175 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
176 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
177 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
178 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
179 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
180 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
183 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
184 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
185 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
186 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
187 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
188 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
189 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
190 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
193 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
194 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
195 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
196 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
197 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
198 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
199 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
200 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
203 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
204 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
205 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
207 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
209 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
210 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
213 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
214 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
215 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
216 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
219 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
220 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
223 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
224 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
225 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
226 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
227 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
228 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
229 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
230 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
233 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
234 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
235 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
236 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
237 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
238 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
239 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
240 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
243 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
244 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
245 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
246 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
247 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
248 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
249 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
250 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
253 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
254 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
255 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
256 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
257 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
258 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
259 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
260 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
263 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
264 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
265 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
266 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
267 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
268 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
269 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
270 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
273 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
274 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
275 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
276 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
277 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
278 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
279 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
280 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
283 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
284 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
285 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
286 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
287 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
288 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
289 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
290 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
294 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
295 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
296 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
297 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
298 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
299 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
300 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
304 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
305 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
306 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
307 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
308 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
309 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
310 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
313 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
314 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
315 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
316 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
317 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
318 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
319 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
320 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
323 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
324 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
325 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
326 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
327 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
328 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
329 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
330 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
333 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
334 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
335 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
336 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
337 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
338 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
339 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
340 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
343 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
344 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
348 * This array translates a periph_id to a periphc_internal_id
350 * Not present/matched up:
351 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
352 * SPDIF - which is both 0x08 and 0x0c
355 #define NONE(name) (-1)
356 #define OFFSET(name, value) PERIPHC_ ## name
357 #define INTERNAL_ID(id) (id & 0x000000ff)
358 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
367 PERIPHC_UART2, /* and vfir 0x68 */
399 /* Middle word: 63:32 */
411 PERIPHC_SBC1, /* SBCx = SPIx */
439 /* Upper word 95:64 */
599 /* Y: 192 (192 - 223) */
601 PERIPHC_SDMMC_LEGACY_TM,
605 PERIPHC_DMIC3, /* 197 */
606 PERIPHC_APE, /* 198 */
620 PERIPHC_VI_I2C, /* 208 */
623 PERIPHC_QSPI, /* 211 */
633 PERIPHC_NVENC, /* 219 */
641 * PLL divider shift/mask tables for all PLL IDs.
643 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
645 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
646 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
648 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
649 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */
650 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
651 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
652 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
653 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */
654 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
655 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */
656 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
657 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */
658 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
659 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */
660 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
661 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */
662 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
663 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
664 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
665 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
666 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
667 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
671 * Get the oscillator frequency, from the corresponding hardware configuration
672 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
673 * to the old T20 freqs. Support for the higher oscillators is TBD.
675 enum clock_osc_freq clock_get_osc_freq(void)
677 struct clk_rst_ctlr *clkrst =
678 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
681 reg = readl(&clkrst->crc_osc_ctrl);
682 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
684 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
685 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
688 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
689 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
694 * Map to most common (T20) freqs (except 38.4, handled above):
695 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
700 /* Returns a pointer to the clock source register for a peripheral */
701 u32 *get_periph_source_reg(enum periph_id periph_id)
703 struct clk_rst_ctlr *clkrst =
704 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
705 enum periphc_internal_id internal_id;
707 /* Coresight is a special case */
708 if (periph_id == PERIPH_ID_CSI)
709 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
711 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
712 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
713 assert(internal_id != -1);
715 if (internal_id < PERIPHC_VW_FIRST)
717 return &clkrst->crc_clk_src[internal_id];
719 if (internal_id < PERIPHC_X_FIRST) {
721 internal_id -= PERIPHC_VW_FIRST;
722 return &clkrst->crc_clk_src_vw[internal_id];
725 if (internal_id < PERIPHC_Y_FIRST) {
727 internal_id -= PERIPHC_X_FIRST;
728 return &clkrst->crc_clk_src_x[internal_id];
732 internal_id -= PERIPHC_Y_FIRST;
733 return &clkrst->crc_clk_src_y[internal_id];
736 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
737 int *divider_bits, int *type)
739 enum periphc_internal_id internal_id;
741 if (!clock_periph_id_isvalid(periph_id))
744 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
745 if (!periphc_internal_id_isvalid(internal_id))
748 *type = clock_periph_type[internal_id];
749 if (!clock_type_id_isvalid(*type))
752 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
754 if (*type == CLOCK_TYPE_PC2CC3M_T16)
762 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
764 enum periphc_internal_id internal_id;
767 if (!clock_periph_id_isvalid(periph_id))
768 return CLOCK_ID_NONE;
770 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
771 if (!periphc_internal_id_isvalid(internal_id))
772 return CLOCK_ID_NONE;
774 type = clock_periph_type[internal_id];
775 if (!clock_type_id_isvalid(type))
776 return CLOCK_ID_NONE;
778 return clock_source[type][source];
782 * Given a peripheral ID and the required source clock, this returns which
783 * value should be programmed into the source mux for that peripheral.
785 * There is special code here to handle the one source type with 5 sources.
787 * @param periph_id peripheral to start
788 * @param source PLL id of required parent clock
789 * @param mux_bits Set to number of bits in mux register: 2 or 4
790 * @param divider_bits Set to number of divider bits (8 or 16)
791 * @return mux value (0-4, or -1 if not found)
793 int get_periph_clock_source(enum periph_id periph_id,
794 enum clock_id parent, int *mux_bits, int *divider_bits)
796 enum clock_type_id type;
799 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
802 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
803 if (clock_source[type][mux] == parent)
806 /* if we get here, either us or the caller has made a mistake */
807 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
812 void clock_set_enable(enum periph_id periph_id, int enable)
814 struct clk_rst_ctlr *clkrst =
815 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
819 /* Enable/disable the clock to this peripheral */
820 assert(clock_periph_id_isvalid(periph_id));
821 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
822 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
823 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
824 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
825 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
826 clk = &clkrst->crc_clk_out_enb_x;
828 clk = &clkrst->crc_clk_out_enb_y;
832 reg |= PERIPH_MASK(periph_id);
834 reg &= ~PERIPH_MASK(periph_id);
838 void reset_set_enable(enum periph_id periph_id, int enable)
840 struct clk_rst_ctlr *clkrst =
841 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
845 /* Enable/disable reset to the peripheral */
846 assert(clock_periph_id_isvalid(periph_id));
847 if (periph_id < PERIPH_ID_VW_FIRST)
848 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
849 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
850 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
851 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
852 reset = &clkrst->crc_rst_devices_x;
854 reset = &clkrst->crc_rst_devices_y;
858 reg |= PERIPH_MASK(periph_id);
860 reg &= ~PERIPH_MASK(periph_id);
864 #ifdef CONFIG_OF_CONTROL
866 * Convert a device tree clock ID to our peripheral ID. They are mostly
867 * the same but we are very cautious so we check that a valid clock ID is
870 * @param clk_id Clock ID according to tegra210 device tree binding
871 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
873 enum periph_id clk_id_to_periph_id(int clk_id)
875 if (clk_id > PERIPH_ID_COUNT)
876 return PERIPH_ID_NONE;
879 case PERIPH_ID_RESERVED4:
880 case PERIPH_ID_RESERVED25:
881 case PERIPH_ID_RESERVED35:
882 case PERIPH_ID_RESERVED36:
883 case PERIPH_ID_RESERVED38:
884 case PERIPH_ID_RESERVED43:
885 case PERIPH_ID_RESERVED49:
886 case PERIPH_ID_RESERVED53:
887 case PERIPH_ID_RESERVED64:
888 case PERIPH_ID_RESERVED84:
889 case PERIPH_ID_RESERVED85:
890 case PERIPH_ID_RESERVED86:
891 case PERIPH_ID_RESERVED88:
892 case PERIPH_ID_RESERVED90:
893 case PERIPH_ID_RESERVED92:
894 case PERIPH_ID_RESERVED93:
895 case PERIPH_ID_RESERVED94:
896 case PERIPH_ID_V_RESERVED2:
897 case PERIPH_ID_V_RESERVED4:
898 case PERIPH_ID_V_RESERVED17:
899 case PERIPH_ID_V_RESERVED18:
900 case PERIPH_ID_V_RESERVED19:
901 case PERIPH_ID_V_RESERVED20:
902 case PERIPH_ID_V_RESERVED21:
903 case PERIPH_ID_V_RESERVED22:
904 case PERIPH_ID_W_RESERVED2:
905 case PERIPH_ID_W_RESERVED3:
906 case PERIPH_ID_W_RESERVED4:
907 case PERIPH_ID_W_RESERVED5:
908 case PERIPH_ID_W_RESERVED6:
909 case PERIPH_ID_W_RESERVED7:
910 case PERIPH_ID_W_RESERVED9:
911 case PERIPH_ID_W_RESERVED10:
912 case PERIPH_ID_W_RESERVED11:
913 case PERIPH_ID_W_RESERVED12:
914 case PERIPH_ID_W_RESERVED13:
915 case PERIPH_ID_W_RESERVED15:
916 case PERIPH_ID_W_RESERVED16:
917 case PERIPH_ID_W_RESERVED17:
918 case PERIPH_ID_W_RESERVED18:
919 case PERIPH_ID_W_RESERVED19:
920 case PERIPH_ID_W_RESERVED20:
921 case PERIPH_ID_W_RESERVED23:
922 case PERIPH_ID_W_RESERVED29:
923 case PERIPH_ID_W_RESERVED30:
924 case PERIPH_ID_W_RESERVED31:
925 return PERIPH_ID_NONE;
930 #endif /* CONFIG_OF_CONTROL */
933 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
934 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
936 void tegra210_setup_pllp(void)
938 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
941 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
944 /* Assert RSTN before enable */
945 reg = PLLP_OUT1_RSTN_EN;
946 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
947 /* Set divisor and reenable */
948 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
949 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
950 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
953 /* Assert RSTN before enable */
954 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
955 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
956 /* Set divisor and reenable */
957 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
958 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
959 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
960 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
961 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
964 * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
965 * you can change PLLP_BASE DIVP here. Currently defaults
966 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
967 * See Table 13 in section 5.1.4 in T210 TRM for more info.
971 void clock_early_init(void)
973 struct clk_rst_ctlr *clkrst =
974 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
975 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
978 tegra210_setup_pllp();
981 * PLLC output frequency set to 600Mhz
982 * PLLD output frequency set to 925Mhz
984 switch (clock_get_osc_freq()) {
985 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
986 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
987 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
990 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
991 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
992 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
995 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
996 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
997 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
999 case CLOCK_OSC_FREQ_19_2:
1000 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
1001 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
1003 case CLOCK_OSC_FREQ_38_4:
1004 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
1005 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
1009 * These are not supported. It is too early to print a
1010 * message and the UART likely won't work anyway due to the
1011 * oscillator being wrong.
1016 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
1017 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
1022 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
1025 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
1029 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
1030 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);
1031 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
1035 unsigned int clk_m_get_rate(unsigned parent_rate)
1037 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1040 value = readl(&clkrst->crc_spare_reg0);
1041 div = ((value >> 2) & 0x3) + 1;
1043 return parent_rate / div;
1046 void arch_timer_init(void)
1048 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
1051 freq = clock_get_rate(CLOCK_ID_CLK_M);
1052 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
1054 if (current_el() == 3)
1055 asm("msr cntfrq_el0, %0\n" : : "r" (freq));
1057 /* Only Tegra114+ has the System Counter regs */
1058 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
1059 writel(freq, &sysctr->cntfid0);
1061 val = readl(&sysctr->cntcr);
1062 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
1063 writel(val, &sysctr->cntcr);
1064 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
1067 #define PLLREFE_MISC 0x4c8
1068 #define PLLREFE_MISC_LOCK BIT(27)
1069 #define PLLREFE_MISC_IDDQ BIT(24)
1071 #define PLLREFE_BASE 0x4c4
1072 #define PLLREFE_BASE_BYPASS BIT(31)
1073 #define PLLREFE_BASE_ENABLE BIT(30)
1074 #define PLLREFE_BASE_REF_DIS BIT(29)
1075 #define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
1076 #define PLLREFE_BASE_KVCO BIT(26)
1077 #define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
1078 #define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
1079 #define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
1081 static int tegra_pllref_enable(void)
1084 unsigned long start;
1087 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1088 * Recovery Mode or Boot from USB", sub-section "PLLREFE".
1091 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1092 value &= ~PLLREFE_MISC_IDDQ;
1093 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1097 value = PLLREFE_BASE_ENABLE |
1098 PLLREFE_BASE_KCP(0) |
1099 PLLREFE_BASE_DIVP(0) |
1100 PLLREFE_BASE_DIVN(0x41) |
1101 PLLREFE_BASE_DIVM(4);
1102 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE);
1104 debug("waiting for pllrefe lock\n");
1105 start = get_timer(0);
1106 while (get_timer(start) < 250) {
1107 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1108 if (value & PLLREFE_MISC_LOCK)
1111 if (!(value & PLLREFE_MISC_LOCK)) {
1112 debug(" timeout\n");
1120 #define PLLE_SS_CNTL 0x68
1121 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
1122 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
1123 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
1124 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
1125 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
1126 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
1127 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
1128 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
1130 #define PLLE_BASE 0x0e8
1131 #define PLLE_BASE_ENABLE (1 << 31)
1132 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
1133 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
1134 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
1136 #define PLLE_MISC 0x0ec
1137 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
1138 #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
1139 #define PLLE_MISC_LOCK (1 << 11)
1140 #define PLLE_PTS (1 << 8)
1141 #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
1142 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
1143 #define PLLE_MISC_KVCO (1 << 0)
1145 #define PLLE_AUX 0x48c
1146 #define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
1147 #define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
1148 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
1149 #define PLLE_AUX_SS_SWCTL (1 << 6)
1150 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
1151 #define PLLE_AUX_USE_LOCKDET (1 << 3)
1153 int tegra_plle_enable(void)
1156 unsigned long start;
1158 /* PLLREF feeds PLLE */
1159 tegra_pllref_enable();
1162 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1163 * Recovery Mode or Boot from USB", sub-section "PLLEs".
1166 /* 1. Select XTAL as the source */
1168 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
1169 value &= ~PLLE_AUX_REF_SEL_PLLREFE;
1170 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
1172 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1173 value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
1174 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1180 * 3. Program the following registers to generate a low jitter 100MHz
1184 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1185 value &= ~PLLE_BASE_PLDIV_CML(0x1f);
1186 value &= ~PLLE_BASE_NDIV(0xff);
1187 value &= ~PLLE_BASE_MDIV(0xff);
1188 value |= PLLE_BASE_PLDIV_CML(0xe);
1189 value |= PLLE_BASE_NDIV(0x7d);
1190 value |= PLLE_BASE_MDIV(2);
1191 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1193 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1195 value &= ~PLLE_MISC_KCP(3);
1196 value &= ~PLLE_MISC_VREG_CTRL(3);
1197 value &= ~PLLE_MISC_KVCO;
1198 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1200 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1201 value |= PLLE_BASE_ENABLE;
1202 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1204 /* 4. Wait for LOCK */
1206 debug("waiting for plle lock\n");
1207 start = get_timer(0);
1208 while (get_timer(start) < 250) {
1209 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1210 if (value & PLLE_MISC_LOCK)
1213 if (!(value & PLLE_MISC_LOCK)) {
1214 debug(" timeout\n");
1221 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1222 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1223 value |= PLLE_SS_CNTL_SSCINC(1);
1224 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1225 value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
1226 value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
1227 value |= PLLE_SS_CNTL_SSCMAX(0x21);
1228 value &= ~PLLE_SS_CNTL_SSCINVERT;
1229 value &= ~PLLE_SS_CNTL_SSCCENTER;
1230 value &= ~PLLE_SS_CNTL_BYPASS_SS;
1231 value &= ~PLLE_SS_CNTL_SSCBYP;
1232 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1234 /* 6. Wait 300 ns */
1237 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1238 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1243 struct periph_clk_init periph_clk_init_table[] = {
1244 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1245 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1246 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1247 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1248 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1249 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1250 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
1251 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1252 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1253 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1254 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
1255 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
1256 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1257 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1258 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1259 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1260 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1261 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },