arch/arm/mach-tegra/tegra124/xusb-padctl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
   7
   8 #include <common.h>
   9 #include <errno.h>
  10 #include <log.h>
  11 #include <dm/of_access.h>
  12 #include <dm/ofnode.h>
  13 #include <linux/delay.h>
  14 #include <asm/global_data.h>
  15
  16 #include "../xusb-padctl-common.h"
  17
  18 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  19
  20 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
  21 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
  22 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
  23 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
  24
  25 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
  26 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
  27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
  28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
  29
  30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
  31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
  32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
  33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
  34
  35 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
  36 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
  37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
  38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
  39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
  40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
  41
  42 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
  43 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
  44 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
  45
  46 enum tegra124_function {
  47         TEGRA124_FUNC_SNPS,
  48         TEGRA124_FUNC_XUSB,
  49         TEGRA124_FUNC_UART,
  50         TEGRA124_FUNC_PCIE,
  51         TEGRA124_FUNC_USB3,
  52         TEGRA124_FUNC_SATA,
  53         TEGRA124_FUNC_RSVD,
  54 };
  55
  56 static const char *const tegra124_functions[] = {
  57         "snps",
  58         "xusb",
  59         "uart",
  60         "pcie",
  61         "usb3",
  62         "sata",
  63         "rsvd",
  64 };
  65
  66 static const unsigned int tegra124_otg_functions[] = {
  67         TEGRA124_FUNC_SNPS,
  68         TEGRA124_FUNC_XUSB,
  69         TEGRA124_FUNC_UART,
  70         TEGRA124_FUNC_RSVD,
  71 };
  72
  73 static const unsigned int tegra124_usb_functions[] = {
  74         TEGRA124_FUNC_SNPS,
  75         TEGRA124_FUNC_XUSB,
  76 };
  77
  78 static const unsigned int tegra124_pci_functions[] = {
  79         TEGRA124_FUNC_PCIE,
  80         TEGRA124_FUNC_USB3,
  81         TEGRA124_FUNC_SATA,
  82         TEGRA124_FUNC_RSVD,
  83 };
  84
  85 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)     \
  86         {                                                               \
  87                 .name = _name,                                          \
  88                 .offset = _offset,                                      \
  89                 .shift = _shift,                                        \
  90                 .mask = _mask,                                          \
  91                 .iddq = _iddq,                                          \
  92                 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
  93                 .funcs = tegra124_##_funcs##_functions,                 \
  94         }
  95
  96 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
  97         TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
  98         TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
  99         TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
 100         TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
 101         TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
 102         TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
 103         TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
 104         TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
 105         TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
 106         TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
 107         TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
 108         TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
 109 };
 110
 111 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
 112 {
 113         u32 value;
 114
 115         if (padctl->enable++ > 0)
 116                 return 0;
 117
 118         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 119         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
 120         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 121
 122         udelay(100);
 123
 124         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 125         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
 126         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 127
 128         udelay(100);
 129
 130         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 131         value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
 132         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 133
 134         return 0;
 135 }
 136
 137 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
 138 {
 139         u32 value;
 140
 141         if (padctl->enable == 0) {
 142                 pr_err("unbalanced enable/disable");
 143                 return 0;
 144         }
 145
 146         if (--padctl->enable > 0)
 147                 return 0;
 148
 149         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 150         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
 151         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 152
 153         udelay(100);
 154
 155         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 156         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
 157         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 158
 159         udelay(100);
 160
 161         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 162         value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
 163         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 164
 165         return 0;
 166 }
 167
 168 static int phy_prepare(struct tegra_xusb_phy *phy)
 169 {
 170         return tegra_xusb_padctl_enable(phy->padctl);
 171 }
 172
 173 static int phy_unprepare(struct tegra_xusb_phy *phy)
 174 {
 175         return tegra_xusb_padctl_disable(phy->padctl);
 176 }
 177
 178 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 179 {
 180         struct tegra_xusb_padctl *padctl = phy->padctl;
 181         int err = -ETIMEDOUT;
 182         unsigned long start;
 183         u32 value;
 184
 185         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 186         value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
 187         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 188
 189         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
 190         value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
 191                  XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
 192                  XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
 193         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
 194
 195         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 196         value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
 197         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 198
 199         start = get_timer(0);
 200
 201         while (get_timer(start) < 50) {
 202                 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 203                 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
 204                         err = 0;
 205                         break;
 206                 }
 207         }
 208
 209         return err;
 210 }
 211
 212 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
 213 {
 214         struct tegra_xusb_padctl *padctl = phy->padctl;
 215         u32 value;
 216
 217         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 218         value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
 219         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
 220
 221         return 0;
 222 }
 223
 224 static int sata_phy_enable(struct tegra_xusb_phy *phy)
 225 {
 226         struct tegra_xusb_padctl *padctl = phy->padctl;
 227         int err = -ETIMEDOUT;
 228         unsigned long start;
 229         u32 value;
 230
 231         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 232         value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
 233         value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
 234         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 235
 236         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 237         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
 238         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
 239         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 240
 241         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 242         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
 243         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 244
 245         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 246         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
 247         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 248
 249         start = get_timer(0);
 250
 251         while (get_timer(start) < 50) {
 252                 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 253                 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
 254                         err = 0;
 255                         break;
 256                 }
 257         }
 258
 259         return err;
 260 }
 261
 262 static int sata_phy_disable(struct tegra_xusb_phy *phy)
 263 {
 264         struct tegra_xusb_padctl *padctl = phy->padctl;
 265         u32 value;
 266
 267         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 268         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
 269         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 270
 271         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 272         value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
 273         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 274
 275         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 276         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
 277         value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
 278         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
 279
 280         value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 281         value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
 282         value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
 283         padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
 284
 285         return 0;
 286 }
 287
 288 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
 289         .prepare = phy_prepare,
 290         .enable = pcie_phy_enable,
 291         .disable = pcie_phy_disable,
 292         .unprepare = phy_unprepare,
 293 };
 294
 295 static const struct tegra_xusb_phy_ops sata_phy_ops = {
 296         .prepare = phy_prepare,
 297         .enable = sata_phy_enable,
 298         .disable = sata_phy_disable,
 299         .unprepare = phy_unprepare,
 300 };
 301
 302 static struct tegra_xusb_phy tegra124_phys[] = {
 303         {
 304                 .type = TEGRA_XUSB_PADCTL_PCIE,
 305                 .ops = &pcie_phy_ops,
 306                 .padctl = &padctl,
 307         },
 308         {
 309                 .type = TEGRA_XUSB_PADCTL_SATA,
 310                 .ops = &sata_phy_ops,
 311                 .padctl = &padctl,
 312         },
 313 };
 314
 315 static const struct tegra_xusb_padctl_soc tegra124_socdata = {
 316         .lanes = tegra124_lanes,
 317         .num_lanes = ARRAY_SIZE(tegra124_lanes),
 318         .functions = tegra124_functions,
 319         .num_functions = ARRAY_SIZE(tegra124_functions),
 320         .phys = tegra124_phys,
 321         .num_phys = ARRAY_SIZE(tegra124_phys),
 322 };
 323
 324 void tegra_xusb_padctl_init(void)
 325 {
 326         ofnode nodes[1];
 327         int count = 0;
 328         int ret;
 329
 330         debug("%s: start\n", __func__);
 331         if (of_live_active()) {
 332                 struct device_node *np = of_find_compatible_node(NULL, NULL,
 333                                                 "nvidia,tegra124-xusb-padctl");
 334
 335                 debug("np=%p\n", np);
 336                 if (np) {
 337                         nodes[0] = np_to_ofnode(np);
 338                         count = 1;
 339                 }
 340         } else {
 341                 int node_offsets[1];
 342                 int i;
 343
 344                 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
 345                                 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
 346                                 node_offsets, ARRAY_SIZE(node_offsets));
 347                 for (i = 0; i < count; i++)
 348                         nodes[i] = offset_to_ofnode(node_offsets[i]);
 349         }
 350
 351         ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
 352         debug("%s: done, ret=%d\n", __func__, ret);
 353 }