1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015
4 * NVIDIA Corporation <www.nvidia.com>
7 /* Tegra124 Clock control functions */
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sysctr.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
22 * Clock types that we can use as a source. The Tegra124 has muxes for the
23 * peripheral clocks, and in most cases there are four options for the clock
24 * source. This gives us a clock 'type' and exploits what commonality exists
27 * Letters are obvious, except for T which means CLK_M, and S which means the
28 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
29 * datasheet) and PLL_M are different things. The former is the basic
30 * clock supplied to the SOC from an external oscillator. The latter is the
33 * See definitions in clock_id in the header file.
36 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
37 CLOCK_TYPE_MCPA, /* and so on */
51 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
54 CLOCK_TYPE_MCPTM2C2C3,
56 CLOCK_TYPE_AC2CC3P_TS2,
59 CLOCK_TYPE_NONE = -1, /* invalid clock type */
63 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
67 * Clock source mux for each clock type. This just converts our enum into
68 * a list of mux sources for use by the code.
71 * The extra column in each clock source array is used to store the mask
72 * bits in its register for the source.
74 #define CLK(x) CLOCK_ID_ ## x
75 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(CLK_M),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
98 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
100 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
101 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
104 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
107 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
108 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
111 /* Additional clock types on Tegra114+ */
112 /* CLOCK_TYPE_PC2CC3M */
113 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
114 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
116 /* CLOCK_TYPE_PC2CC3S_T */
117 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
118 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
120 /* CLOCK_TYPE_PC2CC3M_T */
121 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
122 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
124 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
125 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
126 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
128 /* CLOCK_TYPE_MC2CC3P_A */
129 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
130 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
133 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
134 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
136 /* CLOCK_TYPE_MCPTM2C2C3 */
137 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
138 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
140 /* CLOCK_TYPE_PC2CC3T_S */
141 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
142 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
144 /* CLOCK_TYPE_AC2CC3P_TS2 */
145 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
151 * Clock type for each peripheral clock source. We put the name in each
152 * record just so it is easy to match things up
154 #define TYPE(name, type) type
155 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
157 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
158 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
159 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
160 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
161 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
162 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
163 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
164 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
167 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
168 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
169 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
170 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
171 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
172 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
173 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
174 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
177 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
178 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
179 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
180 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
181 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
182 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
183 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
184 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
187 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
188 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
189 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
190 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
191 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
192 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
193 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
194 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
197 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
198 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
199 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
200 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
201 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
202 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
203 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
204 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
207 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
208 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
209 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
210 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
213 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
214 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
217 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
218 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
219 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
220 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
221 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
222 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
223 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
224 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
227 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
228 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
229 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
231 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
232 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
233 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
234 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
237 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
238 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
239 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
240 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
241 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
242 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
243 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
244 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
247 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
248 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
249 TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
250 TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
251 TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
252 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
253 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
254 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
257 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
258 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
259 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
260 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
261 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
262 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
263 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
264 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
267 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
268 TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE),
269 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
270 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
271 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
272 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
273 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
274 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
277 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
278 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
279 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
280 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
281 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
282 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
283 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
284 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
287 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
288 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
289 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
290 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
291 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
292 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
294 TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
297 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
298 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
299 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
300 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
301 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
302 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
304 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
307 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
308 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
309 TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
310 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
311 TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
312 TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
313 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
314 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
318 * This array translates a periph_id to a periphc_internal_id
320 * Not present/matched up:
321 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
322 * SPDIF - which is both 0x08 and 0x0c
325 #define NONE(name) (-1)
326 #define OFFSET(name, value) PERIPHC_ ## name
327 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
336 PERIPHC_UART2, /* and vfir 0x68 */
368 /* Middle word: 63:32 */
380 PERIPHC_SBC1, /* SBCx = SPIx */
408 /* Upper word 95:64 */
570 * PLL divider shift/mask tables for all PLL IDs.
572 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
574 * T124: same as T114, some deviations from T2x/T30. Adds PLLDP.
575 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
576 * If lock_ena or lock_det are >31, they're not used in that PLL.
579 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
580 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
581 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
582 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
583 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
584 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
585 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
586 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
587 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
588 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
589 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
590 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
591 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
592 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
593 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
594 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
595 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
596 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
597 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
598 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
602 * Get the oscillator frequency, from the corresponding hardware configuration
603 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
604 * to the old T20 freqs. Support for the higher oscillators is TBD.
606 enum clock_osc_freq clock_get_osc_freq(void)
608 struct clk_rst_ctlr *clkrst =
609 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
612 reg = readl(&clkrst->crc_osc_ctrl);
613 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
615 if (reg & 1) /* one of the newer freqs */
616 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
618 return reg >> 2; /* Map to most common (T20) freqs */
621 /* Returns a pointer to the clock source register for a peripheral */
622 u32 *get_periph_source_reg(enum periph_id periph_id)
624 struct clk_rst_ctlr *clkrst =
625 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
626 enum periphc_internal_id internal_id;
628 /* Coresight is a special case */
629 if (periph_id == PERIPH_ID_CSI)
630 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
632 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
633 internal_id = periph_id_to_internal_id[periph_id];
634 assert(internal_id != -1);
635 if (internal_id >= PERIPHC_X_FIRST) {
636 internal_id -= PERIPHC_X_FIRST;
637 return &clkrst->crc_clk_src_x[internal_id];
638 } else if (internal_id >= PERIPHC_VW_FIRST) {
639 internal_id -= PERIPHC_VW_FIRST;
640 return &clkrst->crc_clk_src_vw[internal_id];
642 return &clkrst->crc_clk_src[internal_id];
646 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
647 int *divider_bits, int *type)
649 enum periphc_internal_id internal_id;
651 if (!clock_periph_id_isvalid(periph_id))
654 internal_id = periph_id_to_internal_id[periph_id];
655 if (!periphc_internal_id_isvalid(internal_id))
658 *type = clock_periph_type[internal_id];
659 if (!clock_type_id_isvalid(*type))
662 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
664 if (*type == CLOCK_TYPE_PC2CC3M_T16)
672 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
674 enum periphc_internal_id internal_id;
677 if (!clock_periph_id_isvalid(periph_id))
678 return CLOCK_ID_NONE;
680 internal_id = periph_id_to_internal_id[periph_id];
681 if (!periphc_internal_id_isvalid(internal_id))
682 return CLOCK_ID_NONE;
684 type = clock_periph_type[internal_id];
685 if (!clock_type_id_isvalid(type))
686 return CLOCK_ID_NONE;
688 return clock_source[type][source];
692 * Given a peripheral ID and the required source clock, this returns which
693 * value should be programmed into the source mux for that peripheral.
695 * There is special code here to handle the one source type with 5 sources.
697 * @param periph_id peripheral to start
698 * @param source PLL id of required parent clock
699 * @param mux_bits Set to number of bits in mux register: 2 or 4
700 * @param divider_bits Set to number of divider bits (8 or 16)
701 * @return mux value (0-4, or -1 if not found)
703 int get_periph_clock_source(enum periph_id periph_id,
704 enum clock_id parent, int *mux_bits, int *divider_bits)
706 enum clock_type_id type;
709 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
712 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
713 if (clock_source[type][mux] == parent)
716 /* if we get here, either us or the caller has made a mistake */
717 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
722 void clock_set_enable(enum periph_id periph_id, int enable)
724 struct clk_rst_ctlr *clkrst =
725 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
729 /* Enable/disable the clock to this peripheral */
730 assert(clock_periph_id_isvalid(periph_id));
731 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
732 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
733 else if ((int)periph_id < PERIPH_ID_X_FIRST)
734 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
736 clk = &clkrst->crc_clk_out_enb_x;
739 reg |= PERIPH_MASK(periph_id);
741 reg &= ~PERIPH_MASK(periph_id);
745 void reset_set_enable(enum periph_id periph_id, int enable)
747 struct clk_rst_ctlr *clkrst =
748 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
752 /* Enable/disable reset to the peripheral */
753 assert(clock_periph_id_isvalid(periph_id));
754 if (periph_id < PERIPH_ID_VW_FIRST)
755 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
756 else if ((int)periph_id < PERIPH_ID_X_FIRST)
757 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
759 reset = &clkrst->crc_rst_devices_x;
762 reg |= PERIPH_MASK(periph_id);
764 reg &= ~PERIPH_MASK(periph_id);
768 #if CONFIG_IS_ENABLED(OF_CONTROL)
770 * Convert a device tree clock ID to our peripheral ID. They are mostly
771 * the same but we are very cautious so we check that a valid clock ID is
774 * @param clk_id Clock ID according to tegra124 device tree binding
775 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
777 enum periph_id clk_id_to_periph_id(int clk_id)
779 if (clk_id > PERIPH_ID_COUNT)
780 return PERIPH_ID_NONE;
783 case PERIPH_ID_RESERVED4:
784 case PERIPH_ID_RESERVED25:
785 case PERIPH_ID_RESERVED35:
786 case PERIPH_ID_RESERVED36:
787 case PERIPH_ID_RESERVED38:
788 case PERIPH_ID_RESERVED43:
789 case PERIPH_ID_RESERVED49:
790 case PERIPH_ID_RESERVED53:
791 case PERIPH_ID_RESERVED64:
792 case PERIPH_ID_RESERVED84:
793 case PERIPH_ID_RESERVED85:
794 case PERIPH_ID_RESERVED86:
795 case PERIPH_ID_RESERVED88:
796 case PERIPH_ID_RESERVED90:
797 case PERIPH_ID_RESERVED92:
798 case PERIPH_ID_RESERVED93:
799 case PERIPH_ID_RESERVED94:
800 case PERIPH_ID_V_RESERVED2:
801 case PERIPH_ID_V_RESERVED4:
802 case PERIPH_ID_V_RESERVED17:
803 case PERIPH_ID_V_RESERVED18:
804 case PERIPH_ID_V_RESERVED19:
805 case PERIPH_ID_V_RESERVED20:
806 case PERIPH_ID_V_RESERVED21:
807 case PERIPH_ID_V_RESERVED22:
808 case PERIPH_ID_W_RESERVED2:
809 case PERIPH_ID_W_RESERVED3:
810 case PERIPH_ID_W_RESERVED4:
811 case PERIPH_ID_W_RESERVED5:
812 case PERIPH_ID_W_RESERVED6:
813 case PERIPH_ID_W_RESERVED7:
814 case PERIPH_ID_W_RESERVED9:
815 case PERIPH_ID_W_RESERVED10:
816 case PERIPH_ID_W_RESERVED11:
817 case PERIPH_ID_W_RESERVED12:
818 case PERIPH_ID_W_RESERVED13:
819 case PERIPH_ID_W_RESERVED15:
820 case PERIPH_ID_W_RESERVED16:
821 case PERIPH_ID_W_RESERVED17:
822 case PERIPH_ID_W_RESERVED18:
823 case PERIPH_ID_W_RESERVED19:
824 case PERIPH_ID_W_RESERVED20:
825 case PERIPH_ID_W_RESERVED23:
826 case PERIPH_ID_W_RESERVED29:
827 case PERIPH_ID_W_RESERVED30:
828 case PERIPH_ID_W_RESERVED31:
829 return PERIPH_ID_NONE;
834 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
836 void clock_early_init(void)
838 struct clk_rst_ctlr *clkrst =
839 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
840 struct clk_pll_info *pllinfo;
843 tegra30_set_up_pllp();
845 /* clear IDDQ before accessing any other PLLC registers */
846 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
847 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
851 * PLLC output frequency set to 600Mhz
852 * PLLD output frequency set to 925Mhz
854 switch (clock_get_osc_freq()) {
855 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
856 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
857 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
860 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
861 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
862 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
865 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
866 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
867 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
869 case CLOCK_OSC_FREQ_19_2:
872 * These are not supported. It is too early to print a
873 * message and the UART likely won't work anyway due to the
874 * oscillator being wrong.
879 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
880 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
882 /* PLLC_MISC: Set LOCK_ENABLE */
883 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
884 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
887 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
888 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
889 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
890 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
891 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
896 * clock_early_init_done - Check if clock_early_init() has been called
898 * Check a register that we set up to see if clock_early_init() has already
901 * @return true if clock_early_init() was called, false if not
903 bool clock_early_init_done(void)
905 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
908 val = readl(&clkrst->crc_sclk_brst_pol);
910 return val == 0x20002222;
913 void arch_timer_init(void)
915 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
918 freq = clock_get_rate(CLOCK_ID_CLK_M);
919 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
922 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
924 /* Only Tegra114+ has the System Counter regs */
925 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
926 writel(freq, &sysctr->cntfid0);
928 val = readl(&sysctr->cntcr);
929 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
930 writel(val, &sysctr->cntcr);
931 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
934 #define PLLE_SS_CNTL 0x68
935 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
936 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
937 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
938 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
939 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
940 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
941 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
942 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
944 #define PLLE_BASE 0x0e8
945 #define PLLE_BASE_ENABLE (1 << 30)
946 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
947 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
948 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
949 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
951 #define PLLE_MISC 0x0ec
952 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
953 #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
954 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
955 #define PLLE_MISC_PTS (1 << 8)
956 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
957 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
959 #define PLLE_AUX 0x48c
960 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
961 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
963 int tegra_plle_enable(void)
965 unsigned int m = 1, n = 200, cpcon = 13;
968 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
969 value &= ~PLLE_BASE_LOCK_OVERRIDE;
970 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
972 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
973 value |= PLLE_AUX_ENABLE_SWCTL;
974 value &= ~PLLE_AUX_SEQ_ENABLE;
975 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
979 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
980 value |= PLLE_MISC_IDDQ_SWCTL;
981 value &= ~PLLE_MISC_IDDQ_OVERRIDE;
982 value |= PLLE_MISC_LOCK_ENABLE;
983 value |= PLLE_MISC_PTS;
984 value |= PLLE_MISC_VREG_BG_CTRL(3);
985 value |= PLLE_MISC_VREG_CTRL(2);
986 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
990 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
991 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
992 PLLE_SS_CNTL_BYPASS_SS;
993 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
995 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
996 value &= ~PLLE_BASE_PLDIV_CML(0xf);
997 value &= ~PLLE_BASE_NDIV(0xff);
998 value &= ~PLLE_BASE_MDIV(0xff);
999 value |= PLLE_BASE_PLDIV_CML(cpcon);
1000 value |= PLLE_BASE_NDIV(n);
1001 value |= PLLE_BASE_MDIV(m);
1002 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1006 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1007 value |= PLLE_BASE_ENABLE;
1008 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1013 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1014 value &= ~PLLE_SS_CNTL_SSCINVERT;
1015 value &= ~PLLE_SS_CNTL_SSCCENTER;
1017 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1018 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1019 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
1021 value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
1022 value |= PLLE_SS_CNTL_SSCINC(0x01);
1023 value |= PLLE_SS_CNTL_SSCMAX(0x25);
1025 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1027 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1028 value &= ~PLLE_SS_CNTL_SSCBYP;
1029 value &= ~PLLE_SS_CNTL_BYPASS_SS;
1030 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1034 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1035 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1036 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1043 void clock_sor_enable_edp_clock(void)
1047 /* uses PLLP, has a non-standard bit layout. */
1048 reg = get_periph_source_reg(PERIPH_ID_SOR0);
1049 setbits_le32(reg, SOR0_CLK_SEL0);
1052 u32 clock_set_display_rate(u32 frequency)
1055 * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
1056 * = (cf * n) >> p, where 1MHz < cf < 6MHz
1057 * = ((ref / m) * n) >> p
1059 * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
1060 * safe vco, then find best (m, n). since m has only 5 bits, we can
1061 * iterate all possible values. Note Tegra 124 supports 11 bits for n,
1062 * but our pll_fields has only 10 bits for n.
1064 * Note values undershoot or overshoot target output frequency may not
1065 * work if the values are not in "safe" range by panel specification.
1067 u32 ref = clock_get_rate(CLOCK_ID_OSC);
1068 u32 divm, divn, divp, cpcon;
1069 u32 cf, vco, rounded_rate = frequency;
1070 u32 diff, best_diff, best_m = 0, best_n = 0, best_p;
1071 const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
1072 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
1073 min_cf = 1 * mhz, max_cf = 6 * mhz;
1074 int mux_bits, divider_bits, source;
1076 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++)
1079 if (vco < min_vco || vco > max_vco) {
1080 printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
1081 __func__, frequency);
1088 for (divm = 1; divm < max_m && best_diff; divm++) {
1099 diff = vco - divn * cf;
1100 if (divn + 1 < max_n && diff > cf / 2) {
1105 if (diff >= best_diff)
1115 else if (best_n < 300)
1117 else if (best_n < 600)
1123 printf("%s: Failed to match output frequency %u, best difference is %u\n",
1124 __func__, frequency, best_diff);
1125 rounded_rate = (ref / best_m * best_n) >> best_p;
1128 debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
1129 __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon);
1131 source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY,
1132 &mux_bits, ÷r_bits);
1133 clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source);
1134 clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon);
1136 return rounded_rate;
1139 void clock_set_up_plldp(void)
1141 struct clk_rst_ctlr *clkrst =
1142 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1145 value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;
1146 writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);
1147 clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0);
1148 writel(value, &clkrst->crc_plldp_ss_cfg);
1151 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
1153 struct clk_rst_ctlr *clkrst =
1154 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1156 if (clkid == CLOCK_ID_DP)
1157 return &clkrst->plldp;
1162 struct periph_clk_init periph_clk_init_table[] = {
1163 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1164 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1165 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1166 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1167 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1168 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1169 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
1170 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
1171 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1172 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1173 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1174 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
1175 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
1176 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1177 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1178 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1179 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1180 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1181 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },