2 * drivers/powergate/tegra-powergate.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/debugfs.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/export.h>
26 #include <linux/init.h>
28 #include <linux/reset.h>
29 #include <linux/seq_file.h>
30 #include <linux/spinlock.h>
31 #include <linux/clk/tegra.h>
32 #include <linux/tegra-powergate.h>
37 #define PWRGATE_TOGGLE 0x30
38 #define PWRGATE_TOGGLE_START (1 << 8)
40 #define REMOVE_CLAMPING 0x34
42 #define PWRGATE_STATUS 0x38
44 #define GPU_RG_CNTRL 0x2d4
46 static int tegra_num_powerdomains;
47 static int tegra_num_cpu_domains;
48 static const u8 *tegra_cpu_domains;
50 static const u8 tegra30_cpu_domains[] = {
57 static const u8 tegra114_cpu_domains[] = {
64 static const u8 tegra124_cpu_domains[] = {
71 static DEFINE_SPINLOCK(tegra_powergate_lock);
73 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
75 static u32 pmc_read(unsigned long reg)
77 return readl(pmc + reg);
80 static void pmc_write(u32 val, unsigned long reg)
82 writel(val, pmc + reg);
85 static int tegra_powergate_set(int id, bool new_state)
90 spin_lock_irqsave(&tegra_powergate_lock, flags);
92 status = pmc_read(PWRGATE_STATUS) & (1 << id);
94 if (status == new_state) {
95 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
99 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
101 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
106 int tegra_powergate_power_on(int id)
108 if (id < 0 || id >= tegra_num_powerdomains)
111 return tegra_powergate_set(id, true);
114 int tegra_powergate_power_off(int id)
116 if (id < 0 || id >= tegra_num_powerdomains)
119 return tegra_powergate_set(id, false);
121 EXPORT_SYMBOL(tegra_powergate_power_off);
123 int tegra_powergate_is_powered(int id)
127 if (id < 0 || id >= tegra_num_powerdomains)
130 status = pmc_read(PWRGATE_STATUS) & (1 << id);
134 int tegra_powergate_remove_clamping(int id)
138 if (id < 0 || id >= tegra_num_powerdomains)
142 * The Tegra124 GPU has a separate register (with different semantics)
145 if (tegra_chip_id == TEGRA124) {
146 if (id == TEGRA_POWERGATE_3D) {
147 pmc_write(0, GPU_RG_CNTRL);
153 * Tegra 2 has a bug where PCIE and VDE clamping masks are
154 * swapped relatively to the partition ids
156 if (id == TEGRA_POWERGATE_VDEC)
157 mask = (1 << TEGRA_POWERGATE_PCIE);
158 else if (id == TEGRA_POWERGATE_PCIE)
159 mask = (1 << TEGRA_POWERGATE_VDEC);
163 pmc_write(mask, REMOVE_CLAMPING);
167 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
169 /* Must be called with clk disabled, and returns with clk enabled */
170 int tegra_powergate_sequence_power_up(int id, struct clk *clk,
171 struct reset_control *rst)
175 reset_control_assert(rst);
177 ret = tegra_powergate_power_on(id);
181 ret = clk_prepare_enable(clk);
187 ret = tegra_powergate_remove_clamping(id);
192 reset_control_deassert(rst);
197 clk_disable_unprepare(clk);
199 tegra_powergate_power_off(id);
203 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
205 int tegra_cpu_powergate_id(int cpuid)
207 if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
208 return tegra_cpu_domains[cpuid];
213 int __init tegra_powergate_init(void)
215 switch (tegra_chip_id) {
217 tegra_num_powerdomains = 7;
220 tegra_num_powerdomains = 14;
221 tegra_num_cpu_domains = 4;
222 tegra_cpu_domains = tegra30_cpu_domains;
225 tegra_num_powerdomains = 23;
226 tegra_num_cpu_domains = 4;
227 tegra_cpu_domains = tegra114_cpu_domains;
230 tegra_num_powerdomains = 25;
231 tegra_num_cpu_domains = 4;
232 tegra_cpu_domains = tegra124_cpu_domains;
235 /* Unknown Tegra variant. Disable powergating */
236 tegra_num_powerdomains = 0;
243 #ifdef CONFIG_DEBUG_FS
245 static const char * const *powergate_name;
247 static const char * const powergate_name_t20[] = {
248 [TEGRA_POWERGATE_CPU] = "cpu",
249 [TEGRA_POWERGATE_3D] = "3d",
250 [TEGRA_POWERGATE_VENC] = "venc",
251 [TEGRA_POWERGATE_VDEC] = "vdec",
252 [TEGRA_POWERGATE_PCIE] = "pcie",
253 [TEGRA_POWERGATE_L2] = "l2",
254 [TEGRA_POWERGATE_MPE] = "mpe",
257 static const char * const powergate_name_t30[] = {
258 [TEGRA_POWERGATE_CPU] = "cpu0",
259 [TEGRA_POWERGATE_3D] = "3d0",
260 [TEGRA_POWERGATE_VENC] = "venc",
261 [TEGRA_POWERGATE_VDEC] = "vdec",
262 [TEGRA_POWERGATE_PCIE] = "pcie",
263 [TEGRA_POWERGATE_L2] = "l2",
264 [TEGRA_POWERGATE_MPE] = "mpe",
265 [TEGRA_POWERGATE_HEG] = "heg",
266 [TEGRA_POWERGATE_SATA] = "sata",
267 [TEGRA_POWERGATE_CPU1] = "cpu1",
268 [TEGRA_POWERGATE_CPU2] = "cpu2",
269 [TEGRA_POWERGATE_CPU3] = "cpu3",
270 [TEGRA_POWERGATE_CELP] = "celp",
271 [TEGRA_POWERGATE_3D1] = "3d1",
274 static const char * const powergate_name_t114[] = {
275 [TEGRA_POWERGATE_CPU] = "crail",
276 [TEGRA_POWERGATE_3D] = "3d",
277 [TEGRA_POWERGATE_VENC] = "venc",
278 [TEGRA_POWERGATE_VDEC] = "vdec",
279 [TEGRA_POWERGATE_MPE] = "mpe",
280 [TEGRA_POWERGATE_HEG] = "heg",
281 [TEGRA_POWERGATE_CPU1] = "cpu1",
282 [TEGRA_POWERGATE_CPU2] = "cpu2",
283 [TEGRA_POWERGATE_CPU3] = "cpu3",
284 [TEGRA_POWERGATE_CELP] = "celp",
285 [TEGRA_POWERGATE_CPU0] = "cpu0",
286 [TEGRA_POWERGATE_C0NC] = "c0nc",
287 [TEGRA_POWERGATE_C1NC] = "c1nc",
288 [TEGRA_POWERGATE_DIS] = "dis",
289 [TEGRA_POWERGATE_DISB] = "disb",
290 [TEGRA_POWERGATE_XUSBA] = "xusba",
291 [TEGRA_POWERGATE_XUSBB] = "xusbb",
292 [TEGRA_POWERGATE_XUSBC] = "xusbc",
295 static const char * const powergate_name_t124[] = {
296 [TEGRA_POWERGATE_CPU] = "crail",
297 [TEGRA_POWERGATE_3D] = "3d",
298 [TEGRA_POWERGATE_VENC] = "venc",
299 [TEGRA_POWERGATE_PCIE] = "pcie",
300 [TEGRA_POWERGATE_VDEC] = "vdec",
301 [TEGRA_POWERGATE_L2] = "l2",
302 [TEGRA_POWERGATE_MPE] = "mpe",
303 [TEGRA_POWERGATE_HEG] = "heg",
304 [TEGRA_POWERGATE_SATA] = "sata",
305 [TEGRA_POWERGATE_CPU1] = "cpu1",
306 [TEGRA_POWERGATE_CPU2] = "cpu2",
307 [TEGRA_POWERGATE_CPU3] = "cpu3",
308 [TEGRA_POWERGATE_CELP] = "celp",
309 [TEGRA_POWERGATE_CPU0] = "cpu0",
310 [TEGRA_POWERGATE_C0NC] = "c0nc",
311 [TEGRA_POWERGATE_C1NC] = "c1nc",
312 [TEGRA_POWERGATE_SOR] = "sor",
313 [TEGRA_POWERGATE_DIS] = "dis",
314 [TEGRA_POWERGATE_DISB] = "disb",
315 [TEGRA_POWERGATE_XUSBA] = "xusba",
316 [TEGRA_POWERGATE_XUSBB] = "xusbb",
317 [TEGRA_POWERGATE_XUSBC] = "xusbc",
318 [TEGRA_POWERGATE_VIC] = "vic",
319 [TEGRA_POWERGATE_IRAM] = "iram",
322 static int powergate_show(struct seq_file *s, void *data)
326 seq_printf(s, " powergate powered\n");
327 seq_printf(s, "------------------\n");
329 for (i = 0; i < tegra_num_powerdomains; i++) {
330 if (!powergate_name[i])
333 seq_printf(s, " %9s %7s\n", powergate_name[i],
334 tegra_powergate_is_powered(i) ? "yes" : "no");
340 static int powergate_open(struct inode *inode, struct file *file)
342 return single_open(file, powergate_show, inode->i_private);
345 static const struct file_operations powergate_fops = {
346 .open = powergate_open,
349 .release = single_release,
352 int __init tegra_powergate_debugfs_init(void)
356 switch (tegra_chip_id) {
358 powergate_name = powergate_name_t20;
361 powergate_name = powergate_name_t30;
364 powergate_name = powergate_name_t114;
367 powergate_name = powergate_name_t124;
371 if (powergate_name) {
372 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,