2 * arch/arm/mach-tegra/cpu-tegra.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
8 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/sched.h>
25 #include <linux/cpufreq.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
31 #include <linux/suspend.h>
33 /* Frequency table index must be sequential starting at 0 */
34 static struct cpufreq_frequency_table freq_table[] = {
43 { 8, CPUFREQ_TABLE_END },
48 static struct clk *cpu_clk;
49 static struct clk *pll_x_clk;
50 static struct clk *pll_p_clk;
51 static struct clk *emc_clk;
53 static unsigned long target_cpu_speed[NUM_CPUS];
54 static DEFINE_MUTEX(tegra_cpu_lock);
55 static bool is_suspended;
57 static int tegra_verify_speed(struct cpufreq_policy *policy)
59 return cpufreq_frequency_table_verify(policy, freq_table);
62 static unsigned int tegra_getspeed(unsigned int cpu)
69 rate = clk_get_rate(cpu_clk) / 1000;
73 static int tegra_cpu_clk_set_rate(unsigned long rate)
78 * Take an extra reference to the main pll so it doesn't turn
79 * off when we move the cpu off of it
81 clk_prepare_enable(pll_x_clk);
83 ret = clk_set_parent(cpu_clk, pll_p_clk);
85 pr_err("Failed to switch cpu to clock pll_p\n");
89 if (rate == clk_get_rate(pll_p_clk))
92 ret = clk_set_rate(pll_x_clk, rate);
94 pr_err("Failed to change pll_x to %lu\n", rate);
98 ret = clk_set_parent(cpu_clk, pll_x_clk);
100 pr_err("Failed to switch cpu to clock pll_x\n");
105 clk_disable_unprepare(pll_x_clk);
109 static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
113 struct cpufreq_freqs freqs;
115 freqs.old = tegra_getspeed(0);
118 if (freqs.old == freqs.new)
122 * Vote on memory bus frequency based on cpu frequency
123 * This sets the minimum frequency, display or avp may request higher
126 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
127 else if (rate >= 456000)
128 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
130 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
132 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
134 #ifdef CONFIG_CPU_FREQ_DEBUG
135 printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
136 freqs.old, freqs.new);
139 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
141 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
146 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
151 static unsigned long tegra_cpu_highest_speed(void)
153 unsigned long rate = 0;
156 for_each_online_cpu(i)
157 rate = max(rate, target_cpu_speed[i]);
161 static int tegra_target(struct cpufreq_policy *policy,
162 unsigned int target_freq,
163 unsigned int relation)
169 mutex_lock(&tegra_cpu_lock);
176 cpufreq_frequency_table_target(policy, freq_table, target_freq,
179 freq = freq_table[idx].frequency;
181 target_cpu_speed[policy->cpu] = freq;
183 ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
186 mutex_unlock(&tegra_cpu_lock);
190 static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
193 mutex_lock(&tegra_cpu_lock);
194 if (event == PM_SUSPEND_PREPARE) {
195 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
197 pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
198 freq_table[0].frequency);
199 tegra_update_cpu_speed(policy, freq_table[0].frequency);
200 cpufreq_cpu_put(policy);
201 } else if (event == PM_POST_SUSPEND) {
202 is_suspended = false;
204 mutex_unlock(&tegra_cpu_lock);
209 static struct notifier_block tegra_cpu_pm_notifier = {
210 .notifier_call = tegra_pm_notify,
213 static int tegra_cpu_init(struct cpufreq_policy *policy)
215 if (policy->cpu >= NUM_CPUS)
218 clk_prepare_enable(emc_clk);
219 clk_prepare_enable(cpu_clk);
221 cpufreq_frequency_table_cpuinfo(policy, freq_table);
222 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
223 policy->cur = tegra_getspeed(policy->cpu);
224 target_cpu_speed[policy->cpu] = policy->cur;
226 /* FIXME: what's the actual transition time? */
227 policy->cpuinfo.transition_latency = 300 * 1000;
229 cpumask_copy(policy->cpus, cpu_possible_mask);
231 if (policy->cpu == 0)
232 register_pm_notifier(&tegra_cpu_pm_notifier);
237 static int tegra_cpu_exit(struct cpufreq_policy *policy)
239 cpufreq_frequency_table_cpuinfo(policy, freq_table);
240 clk_disable_unprepare(emc_clk);
244 static struct freq_attr *tegra_cpufreq_attr[] = {
245 &cpufreq_freq_attr_scaling_available_freqs,
249 static struct cpufreq_driver tegra_cpufreq_driver = {
250 .verify = tegra_verify_speed,
251 .target = tegra_target,
252 .get = tegra_getspeed,
253 .init = tegra_cpu_init,
254 .exit = tegra_cpu_exit,
256 .attr = tegra_cpufreq_attr,
259 static int __init tegra_cpufreq_init(void)
261 cpu_clk = clk_get_sys(NULL, "cpu");
263 return PTR_ERR(cpu_clk);
265 pll_x_clk = clk_get_sys(NULL, "pll_x");
266 if (IS_ERR(pll_x_clk))
267 return PTR_ERR(pll_x_clk);
269 pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
270 if (IS_ERR(pll_p_clk))
271 return PTR_ERR(pll_p_clk);
273 emc_clk = clk_get_sys("cpu", "emc");
274 if (IS_ERR(emc_clk)) {
276 return PTR_ERR(emc_clk);
279 return cpufreq_register_driver(&tegra_cpufreq_driver);
282 static void __exit tegra_cpufreq_exit(void)
284 cpufreq_unregister_driver(&tegra_cpufreq_driver);
290 MODULE_AUTHOR("Colin Cross <ccross@android.com>");
291 MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
292 MODULE_LICENSE("GPL");
293 module_init(tegra_cpufreq_init);
294 module_exit(tegra_cpufreq_exit);