arch/arm/mach-sunxi/dram_sun8i_h3.c

   1 /*
   2  * sun8i H3 platform dram controller init
   3  *
   4  * (C) Copyright 2007-2015 Allwinner Technology Co.
   5  *                         Jerry Wang <wangflord@allwinnertech.com>
   6  * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
   7  * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
   8  * (C) Copyright 2015      Jens Kuske <jenskuske@gmail.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/dram.h>
  16 #include <linux/kconfig.h>
  17
  18 struct dram_para {
  19         u32 read_delays;
  20         u32 write_delays;
  21         u16 page_size;
  22         u8 bus_width;
  23         u8 dual_rank;
  24         u8 row_bits;
  25 };
  26
  27 static inline int ns_to_t(int nanoseconds)
  28 {
  29         const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
  30
  31         return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
  32 }
  33
  34 static u32 bin_to_mgray(int val)
  35 {
  36         static const u8 lookup_table[32] = {
  37                 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
  38                 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
  39                 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
  40                 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
  41         };
  42
  43         return lookup_table[clamp(val, 0, 31)];
  44 }
  45
  46 static int mgray_to_bin(u32 val)
  47 {
  48         static const u8 lookup_table[32] = {
  49                 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
  50                 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
  51                 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
  52                 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
  53         };
  54
  55         return lookup_table[val & 0x1f];
  56 }
  57
  58 static void mctl_phy_init(u32 val)
  59 {
  60         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  61                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  62
  63         writel(val | PIR_INIT, &mctl_ctl->pir);
  64         mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
  65 }
  66
  67 static void mctl_dq_delay(u32 read, u32 write)
  68 {
  69         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  70                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  71         int i, j;
  72         u32 val;
  73
  74         for (i = 0; i < 4; i++) {
  75                 val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
  76                       DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
  77
  78                 for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
  79                         writel(val, &mctl_ctl->datx[i].iocr[j]);
  80         }
  81
  82         clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
  83
  84         for (i = 0; i < 4; i++) {
  85                 val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
  86                       DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
  87
  88                 writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
  89                 writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
  90         }
  91
  92         setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
  93
  94         udelay(1);
  95 }
  96
  97 enum {
  98         MBUS_PORT_CPU           = 0,
  99         MBUS_PORT_GPU           = 1,
 100         MBUS_PORT_UNUSED        = 2,
 101         MBUS_PORT_DMA           = 3,
 102         MBUS_PORT_VE            = 4,
 103         MBUS_PORT_CSI           = 5,
 104         MBUS_PORT_NAND          = 6,
 105         MBUS_PORT_SS            = 7,
 106         MBUS_PORT_TS            = 8,
 107         MBUS_PORT_DI            = 9,
 108         MBUS_PORT_DE            = 10,
 109         MBUS_PORT_DE_CFD        = 11,
 110 };
 111
 112 enum {
 113         MBUS_QOS_LOWEST = 0,
 114         MBUS_QOS_LOW,
 115         MBUS_QOS_HIGH,
 116         MBUS_QOS_HIGHEST
 117 };
 118
 119 inline void mbus_configure_port(u8 port,
 120                                 bool bwlimit,
 121                                 bool priority,
 122                                 u8 qos,         /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
 123                                 u8 waittime,    /* 0 .. 0xf */
 124                                 u8 acs,         /* 0 .. 0xff */
 125                                 u16 bwl0,       /* 0 .. 0xffff, bandwidth limit in MB/s */
 126                                 u16 bwl1,
 127                                 u16 bwl2)
 128 {
 129         struct sunxi_mctl_com_reg * const mctl_com =
 130                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 131
 132         const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
 133                            | (priority ? (1 << 1) : 0)
 134                            | ((qos & 0x3) << 2)
 135                            | ((waittime & 0xf) << 4)
 136                            | ((acs & 0xff) << 8)
 137                            | (bwl0 << 16) );
 138         const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
 139
 140         debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
 141         writel(cfg0, &mctl_com->mcr[port][0]);
 142         writel(cfg1, &mctl_com->mcr[port][1]);
 143 }
 144
 145 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2)    \
 146         mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
 147                             MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
 148
 149 static void mctl_set_master_priority(void)
 150 {
 151         struct sunxi_mctl_com_reg * const mctl_com =
 152                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 153
 154         /* enable bandwidth limit windows and set windows size 1us */
 155         writel(0x00010190, &mctl_com->bwcr);
 156
 157         /* set cpu high priority */
 158         writel(0x00000001, &mctl_com->mapr);
 159
 160         MBUS_CONF(   CPU,  true, HIGHEST, 0,  512,  256,  128);
 161         MBUS_CONF(   GPU,  true,    HIGH, 0, 1536, 1024,  256);
 162         MBUS_CONF(UNUSED,  true, HIGHEST, 0,  512,  256,   96);
 163         MBUS_CONF(   DMA,  true, HIGHEST, 0,  256,  128,   32);
 164         MBUS_CONF(    VE,  true,    HIGH, 0, 1792, 1600,  256);
 165         MBUS_CONF(   CSI,  true, HIGHEST, 0,  256,  128,   32);
 166         MBUS_CONF(  NAND,  true,    HIGH, 0,  256,  128,   64);
 167         MBUS_CONF(    SS,  true, HIGHEST, 0,  256,  128,   64);
 168         MBUS_CONF(    TS,  true, HIGHEST, 0,  256,  128,   64);
 169         MBUS_CONF(    DI,  true,    HIGH, 0, 1024,  256,   64);
 170         MBUS_CONF(    DE,  true, HIGHEST, 3, 8192, 6120, 1024);
 171         MBUS_CONF(DE_CFD,  true,    HIGH, 0, 1024,  288,   64);
 172 }
 173
 174 static void mctl_set_timing_params(struct dram_para *para)
 175 {
 176         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 177                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 178
 179         u8 tccd         = 2;
 180         u8 tfaw         = ns_to_t(50);
 181         u8 trrd         = max(ns_to_t(10), 4);
 182         u8 trcd         = ns_to_t(15);
 183         u8 trc          = ns_to_t(53);
 184         u8 txp          = max(ns_to_t(8), 3);
 185         u8 twtr         = max(ns_to_t(8), 4);
 186         u8 trtp         = max(ns_to_t(8), 4);
 187         u8 twr          = max(ns_to_t(15), 3);
 188         u8 trp          = ns_to_t(15);
 189         u8 tras         = ns_to_t(38);
 190         u16 trefi       = ns_to_t(7800) / 32;
 191         u16 trfc        = ns_to_t(350);
 192
 193         u8 tmrw         = 0;
 194         u8 tmrd         = 4;
 195         u8 tmod         = 12;
 196         u8 tcke         = 3;
 197         u8 tcksrx       = 5;
 198         u8 tcksre       = 5;
 199         u8 tckesr       = 4;
 200         u8 trasmax      = 24;
 201
 202         u8 tcl          = 6; /* CL 12 */
 203         u8 tcwl         = 4; /* CWL 8 */
 204         u8 t_rdata_en   = 4;
 205         u8 wr_latency   = 2;
 206
 207         u32 tdinit0     = (500 * CONFIG_DRAM_CLK) + 1;          /* 500us */
 208         u32 tdinit1     = (360 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 360ns */
 209         u32 tdinit2     = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
 210         u32 tdinit3     = (1 * CONFIG_DRAM_CLK) + 1;            /* 1us */
 211
 212         u8 twtp         = tcwl + 2 + twr;       /* WL + BL / 2 + tWR */
 213         u8 twr2rd       = tcwl + 2 + twtr;      /* WL + BL / 2 + tWTR */
 214         u8 trd2wr       = tcl + 2 + 1 - tcwl;   /* RL + BL / 2 + 2 - WL */
 215
 216         /* set mode register */
 217         writel(0x1c70, &mctl_ctl->mr[0]);       /* CL=11, WR=12 */
 218         writel(0x40, &mctl_ctl->mr[1]);
 219         writel(0x18, &mctl_ctl->mr[2]);         /* CWL=8 */
 220         writel(0x0, &mctl_ctl->mr[3]);
 221
 222         /* set DRAM timing */
 223         writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
 224                DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
 225                &mctl_ctl->dramtmg[0]);
 226         writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
 227                &mctl_ctl->dramtmg[1]);
 228         writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
 229                DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
 230                &mctl_ctl->dramtmg[2]);
 231         writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
 232                &mctl_ctl->dramtmg[3]);
 233         writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
 234                DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
 235         writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
 236                DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
 237                &mctl_ctl->dramtmg[5]);
 238
 239         /* set two rank timing */
 240         clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
 241                         (0x66 << 8) | (0x10 << 0));
 242
 243         /* set PHY interface timing, write latency and read latency configure */
 244         writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
 245                (wr_latency << 0), &mctl_ctl->pitmg[0]);
 246
 247         /* set PHY timing, PTR0-2 use default */
 248         writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
 249         writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
 250
 251         /* set refresh timing */
 252         writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
 253 }
 254
 255 static void mctl_zq_calibration(struct dram_para *para)
 256 {
 257         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 258                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 259
 260         if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
 261             (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
 262                 u32 reg_val;
 263
 264                 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
 265                                 CONFIG_DRAM_ZQ & 0xffff);
 266
 267                 writel(PIR_CLRSR, &mctl_ctl->pir);
 268                 mctl_phy_init(PIR_ZCAL);
 269
 270                 reg_val = readl(&mctl_ctl->zqdr[0]);
 271                 reg_val &= (0x1f << 16) | (0x1f << 0);
 272                 reg_val |= reg_val << 8;
 273                 writel(reg_val, &mctl_ctl->zqdr[0]);
 274
 275                 reg_val = readl(&mctl_ctl->zqdr[1]);
 276                 reg_val &= (0x1f << 16) | (0x1f << 0);
 277                 reg_val |= reg_val << 8;
 278                 writel(reg_val, &mctl_ctl->zqdr[1]);
 279                 writel(reg_val, &mctl_ctl->zqdr[2]);
 280         } else {
 281                 int i;
 282                 u16 zq_val[6];
 283                 u8 val;
 284
 285                 writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
 286
 287                 for (i = 0; i < 6; i++) {
 288                         u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
 289
 290                         writel((zq << 20) | (zq << 16) | (zq << 12) |
 291                                         (zq << 8) | (zq << 4) | (zq << 0),
 292                                         &mctl_ctl->zqcr);
 293
 294                         writel(PIR_CLRSR, &mctl_ctl->pir);
 295                         mctl_phy_init(PIR_ZCAL);
 296
 297                         zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
 298                         writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
 299
 300                         writel(PIR_CLRSR, &mctl_ctl->pir);
 301                         mctl_phy_init(PIR_ZCAL);
 302
 303                         val = readl(&mctl_ctl->zqdr[0]) >> 24;
 304                         zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
 305                 }
 306
 307                 writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
 308                 writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
 309                 writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
 310         }
 311 }
 312
 313 static void mctl_set_cr(struct dram_para *para)
 314 {
 315         struct sunxi_mctl_com_reg * const mctl_com =
 316                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 317
 318         writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
 319                MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
 320                (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
 321                MCTL_CR_PAGE_SIZE(para->page_size) |
 322                MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
 323 }
 324
 325 static void mctl_sys_init(struct dram_para *para)
 326 {
 327         struct sunxi_ccm_reg * const ccm =
 328                         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 329         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 330                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 331
 332         clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
 333         clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 334         clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 335         clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 336         clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
 337         udelay(10);
 338
 339         clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 340         udelay(1000);
 341
 342         clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
 343         clrsetbits_le32(&ccm->dram_clk_cfg,
 344                         CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
 345                         CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
 346                         CCM_DRAMCLK_CFG_UPD);
 347         mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
 348
 349         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 350         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 351         setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 352         setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
 353
 354         setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 355         udelay(10);
 356
 357         writel(0xc00e, &mctl_ctl->clken);
 358         udelay(500);
 359 }
 360
 361 static int mctl_channel_init(struct dram_para *para)
 362 {
 363         struct sunxi_mctl_com_reg * const mctl_com =
 364                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 365         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 366                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 367
 368         unsigned int i;
 369
 370         mctl_set_cr(para);
 371         mctl_set_timing_params(para);
 372         mctl_set_master_priority();
 373
 374         /* setting VTC, default disable all VT */
 375         clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
 376         clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
 377
 378         /* increase DFI_PHY_UPD clock */
 379         writel(PROTECT_MAGIC, &mctl_com->protect);
 380         udelay(100);
 381         clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
 382         writel(0x0, &mctl_com->protect);
 383         udelay(100);
 384
 385         /* set dramc odt */
 386         for (i = 0; i < 4; i++)
 387                 clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
 388                                 (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
 389                                 (0x3 << 14),
 390                                 IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
 391
 392         /* AC PDR should always ON */
 393         setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
 394
 395         /* set DQS auto gating PD mode */
 396         setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
 397
 398         /* dx ddr_clk & hdr_clk dynamic mode */
 399         clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
 400
 401         /* dphy & aphy phase select 270 degree */
 402         clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 403                         (0x1 << 10) | (0x2 << 8));
 404
 405         /* set half DQ */
 406         if (para->bus_width != 32) {
 407                 writel(0x0, &mctl_ctl->datx[2].gcr);
 408                 writel(0x0, &mctl_ctl->datx[3].gcr);
 409         }
 410
 411         /* data training configuration */
 412         clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
 413                         (para->dual_rank ? 0x3 : 0x1) << 24);
 414
 415
 416         if (para->read_delays || para->write_delays) {
 417                 mctl_dq_delay(para->read_delays, para->write_delays);
 418                 udelay(50);
 419         }
 420
 421         mctl_zq_calibration(para);
 422
 423         mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
 424                       PIR_DRAMINIT | PIR_QSGATE);
 425
 426         /* detect ranks and bus width */
 427         if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
 428                 /* only one rank */
 429                 if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
 430                     ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
 431                         clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
 432                         para->dual_rank = 0;
 433                 }
 434
 435                 /* only half DQ width */
 436                 if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
 437                     ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
 438                         writel(0x0, &mctl_ctl->datx[2].gcr);
 439                         writel(0x0, &mctl_ctl->datx[3].gcr);
 440                         para->bus_width = 16;
 441                 }
 442
 443                 mctl_set_cr(para);
 444                 udelay(20);
 445
 446                 /* re-train */
 447                 mctl_phy_init(PIR_QSGATE);
 448                 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
 449                         return 1;
 450         }
 451
 452         /* check the dramc status */
 453         mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
 454
 455         /* liuke added for refresh debug */
 456         setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
 457         udelay(10);
 458         clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
 459         udelay(10);
 460
 461         /* set PGCR3, CKE polarity */
 462         writel(0x00aa0060, &mctl_ctl->pgcr[3]);
 463
 464         /* power down zq calibration module for power save */
 465         setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
 466
 467         /* enable master access */
 468         writel(0xffffffff, &mctl_com->maer);
 469
 470         return 0;
 471 }
 472
 473 static void mctl_auto_detect_dram_size(struct dram_para *para)
 474 {
 475         /* detect row address bits */
 476         para->page_size = 512;
 477         para->row_bits = 16;
 478         mctl_set_cr(para);
 479
 480         for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
 481                 if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
 482                         break;
 483
 484         /* detect page size */
 485         para->page_size = 8192;
 486         mctl_set_cr(para);
 487
 488         for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
 489                 if (mctl_mem_matches(para->page_size))
 490                         break;
 491 }
 492
 493 unsigned long sunxi_dram_init(void)
 494 {
 495         struct sunxi_mctl_com_reg * const mctl_com =
 496                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 497         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 498                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 499
 500         struct dram_para para = {
 501                 .read_delays = 0x00007979,      /* dram_tpr12 */
 502                 .write_delays = 0x6aaa0000,     /* dram_tpr11 */
 503                 .dual_rank = 0,
 504                 .bus_width = 32,
 505                 .row_bits = 15,
 506                 .page_size = 4096,
 507         };
 508
 509         mctl_sys_init(&para);
 510         if (mctl_channel_init(&para))
 511                 return 0;
 512
 513         if (para.dual_rank)
 514                 writel(0x00000303, &mctl_ctl->odtmap);
 515         else
 516                 writel(0x00000201, &mctl_ctl->odtmap);
 517         udelay(1);
 518
 519         /* odt delay */
 520         writel(0x0c000400, &mctl_ctl->odtcfg);
 521
 522         /* clear credit value */
 523         setbits_le32(&mctl_com->cccr, 1 << 31);
 524         udelay(10);
 525
 526         mctl_auto_detect_dram_size(&para);
 527         mctl_set_cr(&para);
 528
 529         return (1 << (para.row_bits + 3)) * para.page_size *
 530                                                 (para.dual_rank ? 2 : 1);
 531 }