2 * sun50i H6 platform dram controller init
4 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/dram.h>
12 #include <asm/arch/cpu.h>
13 #include <linux/bitops.h>
14 #include <linux/kconfig.h>
17 * The DRAM controller structure on H6 is similar to the ones on A23/A80:
18 * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
19 * /H5/R40 CTL and PHY is composed).
21 * COM is allwinner-specific. On H6, the address mapping function is moved
22 * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
25 * CTL (controller) and PHY is from DesignWare.
27 * The CTL part is a bit similar to the one on A23/A80 (because they all
28 * originate from DesignWare), but gets more registers added.
30 * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
31 * not seen on other SoCs in U-Boot. The only SoC that is also known to have
32 * similar PHY is ZynqMP.
35 static void mctl_sys_init(struct dram_para *para);
36 static void mctl_com_init(struct dram_para *para);
37 static void mctl_channel_init(struct dram_para *para);
39 static void mctl_core_init(struct dram_para *para)
44 case SUNXI_DRAM_TYPE_LPDDR3:
45 mctl_set_timing_params(para);
48 panic("Unsupported DRAM type!");
50 mctl_channel_init(para);
53 /* PHY initialisation */
54 static void mctl_phy_pir_init(u32 val)
56 struct sunxi_mctl_phy_reg * const mctl_phy =
57 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
59 writel(val, &mctl_phy->pir);
60 writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
61 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
91 inline void mbus_configure_port(u8 port,
101 struct sunxi_mctl_com_reg * const mctl_com =
102 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
104 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
105 | (priority ? (1 << 1) : 0)
107 | ((waittime & 0xf) << 4)
108 | ((acs & 0xff) << 8)
110 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
112 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
113 writel(cfg0, &mctl_com->master[port].cfg0);
114 writel(cfg1, &mctl_com->master[port].cfg1);
117 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
118 mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
119 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
121 static void mctl_set_master_priority(void)
123 struct sunxi_mctl_com_reg * const mctl_com =
124 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
126 /* enable bandwidth limit windows and set windows size 1us */
127 writel(399, &mctl_com->tmr);
128 writel(BIT(16), &mctl_com->bwcr);
130 MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
131 MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
132 MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
133 MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
134 MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
135 MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
136 MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
137 MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
138 MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
139 MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
140 MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
141 MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
142 MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
143 MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
144 MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
145 MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
146 MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
149 static void mctl_sys_init(struct dram_para *para)
151 struct sunxi_ccm_reg * const ccm =
152 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
153 struct sunxi_mctl_com_reg * const mctl_com =
154 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
155 struct sunxi_mctl_ctl_reg * const mctl_ctl =
156 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
158 /* Put all DRAM-related blocks to reset state */
159 clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
160 clrbits_le32(&ccm->dram_gate_reset, BIT(0));
162 writel(0, &ccm->dram_gate_reset);
163 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
164 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
168 /* Set PLL5 rate to doubled DRAM clock rate */
169 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
170 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
171 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
173 /* Configure DRAM mod clock */
174 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
175 setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
176 writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
178 setbits_le32(&ccm->dram_gate_reset, BIT(0));
180 /* Disable all channels */
181 writel(0, &mctl_com->maer0);
182 writel(0, &mctl_com->maer1);
183 writel(0, &mctl_com->maer2);
185 /* Configure MBUS and enable DRAM mod reset */
186 setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
187 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
188 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
191 /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
192 writel(0x8000, &mctl_ctl->unk_0x00c);
195 static void mctl_set_addrmap(struct dram_para *para)
197 struct sunxi_mctl_ctl_reg * const mctl_ctl =
198 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
199 u8 cols = para->cols;
200 u8 rows = para->rows;
201 u8 ranks = para->ranks;
205 mctl_ctl->addrmap[0] = rows + cols - 3;
207 mctl_ctl->addrmap[0] = 0x1F;
209 /* Banks, hardcoded to 8 banks now */
210 mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
213 mctl_ctl->addrmap[2] = 0;
216 mctl_ctl->addrmap[3] = 0x1F1F0000;
217 mctl_ctl->addrmap[4] = 0x1F1F;
220 mctl_ctl->addrmap[3] = 0x1F000000;
221 mctl_ctl->addrmap[4] = 0x1F1F;
224 mctl_ctl->addrmap[3] = 0;
225 mctl_ctl->addrmap[4] = 0x1F1F;
228 mctl_ctl->addrmap[3] = 0;
229 mctl_ctl->addrmap[4] = 0x1F00;
232 mctl_ctl->addrmap[3] = 0;
233 mctl_ctl->addrmap[4] = 0;
236 panic("Unsupported DRAM configuration: column number invalid\n");
240 mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
243 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
244 mctl_ctl->addrmap[7] = 0x0F0F;
247 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
248 mctl_ctl->addrmap[7] = 0x0F0F;
251 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
252 mctl_ctl->addrmap[7] = 0x0F0F;
255 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
256 mctl_ctl->addrmap[7] = 0x0F0F;
259 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
260 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
263 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
264 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
267 panic("Unsupported DRAM configuration: row number invalid\n");
270 /* Bank groups, DDR4 only */
271 mctl_ctl->addrmap[8] = 0x3F3F;
274 static void mctl_com_init(struct dram_para *para)
276 struct sunxi_mctl_com_reg * const mctl_com =
277 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
278 struct sunxi_mctl_ctl_reg * const mctl_ctl =
279 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
280 struct sunxi_mctl_phy_reg * const mctl_phy =
281 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
284 mctl_set_addrmap(para);
286 setbits_le32(&mctl_com->cr, BIT(31));
288 * This address is magic; it's in SID memory area, but there's no
289 * known definition of it.
290 * On my Pine H64 board it has content 7.
292 if (readl(0x03006100) == 7)
293 clrbits_le32(&mctl_com->cr, BIT(27));
294 else if (readl(0x03006100) == 3)
295 setbits_le32(&mctl_com->cr, BIT(27));
299 else if (para->clk > 246)
303 clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
305 /* TODO: half DQ, non-LPDDR3 types */
306 writel(MSTR_DEVICETYPE_LPDDR3 | MSTR_BUSWIDTH_FULL |
307 MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) |
308 0x80000000, &mctl_ctl->mstr);
309 writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr);
311 if (para->ranks == 2)
312 writel(0x0303, &mctl_ctl->odtmap);
314 writel(0x0201, &mctl_ctl->odtmap);
316 /* TODO: non-LPDDR3 types */
317 tmp = para->clk * 7 / 2000;
319 reg_val |= (tmp + 7) << 24;
320 reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
321 writel(reg_val, &mctl_ctl->odtcfg);
326 static void mctl_bit_delay_set(struct dram_para *para)
328 struct sunxi_mctl_phy_reg * const mctl_phy =
329 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
333 for (i = 0; i < 4; i++) {
334 val = readl(&mctl_phy->dx[i].bdlr0);
335 for (j = 0; j < 4; j++)
336 val += para->dx_write_delays[i][j] << (j * 8);
337 writel(val, &mctl_phy->dx[i].bdlr0);
339 val = readl(&mctl_phy->dx[i].bdlr1);
340 for (j = 0; j < 4; j++)
341 val += para->dx_write_delays[i][j + 4] << (j * 8);
342 writel(val, &mctl_phy->dx[i].bdlr1);
344 val = readl(&mctl_phy->dx[i].bdlr2);
345 for (j = 0; j < 4; j++)
346 val += para->dx_write_delays[i][j + 8] << (j * 8);
347 writel(val, &mctl_phy->dx[i].bdlr2);
349 clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
351 for (i = 0; i < 4; i++) {
352 val = readl(&mctl_phy->dx[i].bdlr3);
353 for (j = 0; j < 4; j++)
354 val += para->dx_read_delays[i][j] << (j * 8);
355 writel(val, &mctl_phy->dx[i].bdlr3);
357 val = readl(&mctl_phy->dx[i].bdlr4);
358 for (j = 0; j < 4; j++)
359 val += para->dx_read_delays[i][j + 4] << (j * 8);
360 writel(val, &mctl_phy->dx[i].bdlr4);
362 val = readl(&mctl_phy->dx[i].bdlr5);
363 for (j = 0; j < 4; j++)
364 val += para->dx_read_delays[i][j + 8] << (j * 8);
365 writel(val, &mctl_phy->dx[i].bdlr5);
367 val = readl(&mctl_phy->dx[i].bdlr6);
368 val += (para->dx_read_delays[i][12] << 8) |
369 (para->dx_read_delays[i][13] << 16);
370 writel(val, &mctl_phy->dx[i].bdlr6);
372 setbits_le32(&mctl_phy->pgcr[0], BIT(26));
375 for (i = 1; i < 14; i++) {
376 val = readl(&mctl_phy->acbdlr[i]);
378 writel(val, &mctl_phy->acbdlr[i]);
382 static void mctl_channel_init(struct dram_para *para)
384 struct sunxi_mctl_com_reg * const mctl_com =
385 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
386 struct sunxi_mctl_ctl_reg * const mctl_ctl =
387 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
388 struct sunxi_mctl_phy_reg * const mctl_phy =
389 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
393 setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
394 setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
395 writel(0x2f05, &mctl_ctl->sched[0]);
396 setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
397 setbits_le32(&mctl_ctl->dfimisc, BIT(0));
398 setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
399 clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
400 /* TODO: non-LPDDR3 types */
401 clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
402 clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
403 clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
404 /* TODO: VT compensation */
405 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
406 clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
408 for (i = 0; i < 4; i++)
409 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
410 for (i = 0; i < 4; i++)
411 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
412 for (i = 0; i < 4; i++)
413 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
417 if (para->ranks == 2)
418 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
420 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
422 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
423 if (para->ranks == 2) {
424 writel(0x00010001, &mctl_phy->rankidr);
425 writel(0x20000, &mctl_phy->odtcr);
427 writel(0x0, &mctl_phy->rankidr);
428 writel(0x10000, &mctl_phy->odtcr);
431 /* TODO: non-LPDDR3 types */
432 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
433 if (para->clk <= 792) {
434 if (para->clk <= 672) {
435 if (para->clk <= 600)
445 /* FIXME: NOT REVIEWED YET */
446 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
447 clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
448 CONFIG_DRAM_ZQ & 0xff);
449 clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
450 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
451 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
452 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
453 clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
454 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
455 setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
456 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
457 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
458 for (i = 1; i < 14; i++)
459 writel(0x06060606, &mctl_phy->acbdlr[i]);
462 /* TODO: non-LPDDR3 types */
463 mctl_phy_pir_init(PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT |
464 PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE |
467 /* TODO: non-LPDDR3 types */
468 for (i = 0; i < 4; i++)
469 writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
471 for (i = 0; i < 4; i++) {
472 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
476 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
478 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
482 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
485 mctl_bit_delay_set(para);
488 setbits_le32(&mctl_phy->pgcr[6], BIT(0));
489 clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
490 for (i = 0; i < 4; i++)
491 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
494 if (readl(&mctl_phy->pgsr[0]) & 0x400000)
497 * Detect single rank.
498 * TODO: also detect half DQ.
500 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
501 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
502 (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
503 (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
505 /* Restart DRAM initialization from scratch. */
506 mctl_core_init(para);
510 panic("This DRAM setup is currently not supported.\n");
514 if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
515 /* Oops! There's something wrong! */
516 debug("PLL = %x\n", readl(0x3001010));
517 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
518 for (i = 0; i < 4; i++)
519 debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
520 panic("Error while initializing DRAM PHY!\n");
523 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
524 clrbits_le32(&mctl_phy->pgcr[1], 0x40);
525 clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
526 writel(1, &mctl_ctl->swctl);
527 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
528 clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
530 setbits_le32(&mctl_com->unk_0x014, BIT(31));
531 writel(0xffffffff, &mctl_com->maer0);
532 writel(0x7ff, &mctl_com->maer1);
533 writel(0xffff, &mctl_com->maer2);
536 static void mctl_auto_detect_dram_size(struct dram_para *para)
538 /* TODO: non-LPDDR3, half DQ */
540 * Detect rank number by the code in mctl_channel_init. Furtherly
541 * when DQ detection is available it will also be executed there.
543 mctl_core_init(para);
545 /* detect row address bits */
548 mctl_core_init(para);
550 for (para->rows = 13; para->rows < 18; para->rows++) {
551 /* 8 banks, 8 bit per byte and 32 bit width */
552 if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
556 /* detect column address bits */
558 mctl_core_init(para);
560 for (para->cols = 8; para->cols < 11; para->cols++) {
561 /* 8 bits per byte and 32 bit width */
562 if (mctl_mem_matches(1 << (para->cols + 2)))
567 unsigned long mctl_calc_size(struct dram_para *para)
569 /* TODO: non-LPDDR3, half DQ */
571 /* 8 banks, 32-bit (4 byte) data width */
572 return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
575 #define SUN50I_H6_DX_WRITE_DELAYS \
576 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
577 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
578 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
579 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
580 #define SUN50I_H6_DX_READ_DELAYS \
581 {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
582 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
583 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
584 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
586 unsigned long sunxi_dram_init(void)
588 struct sunxi_mctl_com_reg * const mctl_com =
589 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
590 struct dram_para para = {
591 .clk = CONFIG_DRAM_CLK,
592 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
593 .type = SUNXI_DRAM_TYPE_LPDDR3,
597 .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
598 .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
604 /* RES_CAL_CTRL_REG in BSP U-boot*/
605 setbits_le32(0x7010310, BIT(8));
606 clrbits_le32(0x7010318, 0x3f);
608 mctl_auto_detect_dram_size(¶);
610 mctl_core_init(¶);
612 size = mctl_calc_size(¶);
614 clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
616 mctl_set_master_priority();