1 // SPDX-License-Identifier: GPL-2.0+
3 * sun50i H6 platform dram controller init
5 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/dram.h>
13 #include <asm/arch/cpu.h>
14 #include <linux/bitops.h>
15 #include <linux/kconfig.h>
18 * The DRAM controller structure on H6 is similar to the ones on A23/A80:
19 * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
20 * /H5/R40 CTL and PHY is composed).
22 * COM is allwinner-specific. On H6, the address mapping function is moved
23 * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
26 * CTL (controller) and PHY is from DesignWare.
28 * The CTL part is a bit similar to the one on A23/A80 (because they all
29 * originate from DesignWare), but gets more registers added.
31 * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
32 * not seen on other SoCs in U-Boot. The only SoC that is also known to have
33 * similar PHY is ZynqMP.
36 static void mctl_sys_init(struct dram_para *para);
37 static void mctl_com_init(struct dram_para *para);
38 static void mctl_channel_init(struct dram_para *para);
40 static void mctl_core_init(struct dram_para *para)
45 case SUNXI_DRAM_TYPE_LPDDR3:
46 case SUNXI_DRAM_TYPE_DDR3:
47 mctl_set_timing_params(para);
50 panic("Unsupported DRAM type!");
52 mctl_channel_init(para);
55 /* PHY initialisation */
56 static void mctl_phy_pir_init(u32 val)
58 struct sunxi_mctl_phy_reg * const mctl_phy =
59 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
61 writel(val, &mctl_phy->pir);
62 writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
63 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
93 inline void mbus_configure_port(u8 port,
103 struct sunxi_mctl_com_reg * const mctl_com =
104 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
106 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
107 | (priority ? (1 << 1) : 0)
109 | ((waittime & 0xf) << 4)
110 | ((acs & 0xff) << 8)
112 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
114 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
115 writel(cfg0, &mctl_com->master[port].cfg0);
116 writel(cfg1, &mctl_com->master[port].cfg1);
119 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
120 mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
121 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
123 static void mctl_set_master_priority(void)
125 struct sunxi_mctl_com_reg * const mctl_com =
126 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
128 /* enable bandwidth limit windows and set windows size 1us */
129 writel(399, &mctl_com->tmr);
130 writel(BIT(16), &mctl_com->bwcr);
132 MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
133 MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
134 MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
135 MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
136 MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
137 MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
138 MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
139 MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
140 MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
141 MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
142 MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
143 MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
144 MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
145 MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
146 MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
147 MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
148 MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
151 static void mctl_sys_init(struct dram_para *para)
153 struct sunxi_ccm_reg * const ccm =
154 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
155 struct sunxi_mctl_com_reg * const mctl_com =
156 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
157 struct sunxi_mctl_ctl_reg * const mctl_ctl =
158 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
160 /* Put all DRAM-related blocks to reset state */
161 clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
162 clrbits_le32(&ccm->dram_gate_reset, BIT(0));
164 writel(0, &ccm->dram_gate_reset);
165 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
166 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
170 /* Set PLL5 rate to doubled DRAM clock rate */
171 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
172 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
173 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
175 /* Configure DRAM mod clock */
176 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
177 setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
178 writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
180 setbits_le32(&ccm->dram_gate_reset, BIT(0));
182 /* Disable all channels */
183 writel(0, &mctl_com->maer0);
184 writel(0, &mctl_com->maer1);
185 writel(0, &mctl_com->maer2);
187 /* Configure MBUS and enable DRAM mod reset */
188 setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
189 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
190 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
193 /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
194 writel(0x8000, &mctl_ctl->unk_0x00c);
197 static void mctl_set_addrmap(struct dram_para *para)
199 struct sunxi_mctl_ctl_reg * const mctl_ctl =
200 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
201 u8 cols = para->cols;
202 u8 rows = para->rows;
203 u8 ranks = para->ranks;
205 if (!para->bus_full_width)
210 mctl_ctl->addrmap[0] = rows + cols - 3;
212 mctl_ctl->addrmap[0] = 0x1F;
214 /* Banks, hardcoded to 8 banks now */
215 mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
218 mctl_ctl->addrmap[2] = 0;
221 mctl_ctl->addrmap[3] = 0x1F1F1F00;
222 mctl_ctl->addrmap[4] = 0x1F1F;
225 mctl_ctl->addrmap[3] = 0x1F1F0000;
226 mctl_ctl->addrmap[4] = 0x1F1F;
229 mctl_ctl->addrmap[3] = 0x1F000000;
230 mctl_ctl->addrmap[4] = 0x1F1F;
233 mctl_ctl->addrmap[3] = 0;
234 mctl_ctl->addrmap[4] = 0x1F1F;
237 mctl_ctl->addrmap[3] = 0;
238 mctl_ctl->addrmap[4] = 0x1F00;
241 mctl_ctl->addrmap[3] = 0;
242 mctl_ctl->addrmap[4] = 0;
245 panic("Unsupported DRAM configuration: column number invalid\n");
249 mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
252 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
253 mctl_ctl->addrmap[7] = 0x0F0F;
256 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
257 mctl_ctl->addrmap[7] = 0x0F0F;
260 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
261 mctl_ctl->addrmap[7] = 0x0F0F;
264 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
265 mctl_ctl->addrmap[7] = 0x0F0F;
268 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
269 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
272 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
273 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
276 panic("Unsupported DRAM configuration: row number invalid\n");
279 /* Bank groups, DDR4 only */
280 mctl_ctl->addrmap[8] = 0x3F3F;
283 static void mctl_com_init(struct dram_para *para)
285 struct sunxi_mctl_com_reg * const mctl_com =
286 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
287 struct sunxi_mctl_ctl_reg * const mctl_ctl =
288 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
289 struct sunxi_mctl_phy_reg * const mctl_phy =
290 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
293 mctl_set_addrmap(para);
295 setbits_le32(&mctl_com->cr, BIT(31));
297 /* The bonding ID seems to be always 7. */
298 if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
299 clrbits_le32(&mctl_com->cr, BIT(27));
300 else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
301 setbits_le32(&mctl_com->cr, BIT(27));
305 else if (para->clk > 246)
309 clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
312 reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
313 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
314 reg_val |= MSTR_DEVICETYPE_LPDDR3;
315 if (para->type == SUNXI_DRAM_TYPE_DDR3)
316 reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
317 if (para->bus_full_width)
318 reg_val |= MSTR_BUSWIDTH_FULL;
320 reg_val |= MSTR_BUSWIDTH_HALF;
321 writel(reg_val | BIT(31), &mctl_ctl->mstr);
323 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
324 reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
325 if (para->type == SUNXI_DRAM_TYPE_DDR3)
326 reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
327 writel(reg_val | 0x400, &mctl_phy->dcr);
329 if (para->ranks == 2)
330 writel(0x0303, &mctl_ctl->odtmap);
332 writel(0x0201, &mctl_ctl->odtmap);
335 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
336 tmp = para->clk * 7 / 2000;
338 reg_val |= (tmp + 7) << 24;
339 reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
340 } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
341 reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
343 panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
345 writel(reg_val, &mctl_ctl->odtcfg);
347 if (!para->bus_full_width) {
348 writel(0x0, &mctl_phy->dx[2].gcr[0]);
349 writel(0x0, &mctl_phy->dx[3].gcr[0]);
353 static void mctl_bit_delay_set(struct dram_para *para)
355 struct sunxi_mctl_phy_reg * const mctl_phy =
356 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
360 for (i = 0; i < 4; i++) {
361 val = readl(&mctl_phy->dx[i].bdlr0);
362 for (j = 0; j < 4; j++)
363 val += para->dx_write_delays[i][j] << (j * 8);
364 writel(val, &mctl_phy->dx[i].bdlr0);
366 val = readl(&mctl_phy->dx[i].bdlr1);
367 for (j = 0; j < 4; j++)
368 val += para->dx_write_delays[i][j + 4] << (j * 8);
369 writel(val, &mctl_phy->dx[i].bdlr1);
371 val = readl(&mctl_phy->dx[i].bdlr2);
372 for (j = 0; j < 4; j++)
373 val += para->dx_write_delays[i][j + 8] << (j * 8);
374 writel(val, &mctl_phy->dx[i].bdlr2);
376 clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
378 for (i = 0; i < 4; i++) {
379 val = readl(&mctl_phy->dx[i].bdlr3);
380 for (j = 0; j < 4; j++)
381 val += para->dx_read_delays[i][j] << (j * 8);
382 writel(val, &mctl_phy->dx[i].bdlr3);
384 val = readl(&mctl_phy->dx[i].bdlr4);
385 for (j = 0; j < 4; j++)
386 val += para->dx_read_delays[i][j + 4] << (j * 8);
387 writel(val, &mctl_phy->dx[i].bdlr4);
389 val = readl(&mctl_phy->dx[i].bdlr5);
390 for (j = 0; j < 4; j++)
391 val += para->dx_read_delays[i][j + 8] << (j * 8);
392 writel(val, &mctl_phy->dx[i].bdlr5);
394 val = readl(&mctl_phy->dx[i].bdlr6);
395 val += (para->dx_read_delays[i][12] << 8) |
396 (para->dx_read_delays[i][13] << 16);
397 writel(val, &mctl_phy->dx[i].bdlr6);
399 setbits_le32(&mctl_phy->pgcr[0], BIT(26));
402 if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
405 for (i = 1; i < 14; i++) {
406 val = readl(&mctl_phy->acbdlr[i]);
408 writel(val, &mctl_phy->acbdlr[i]);
412 static void mctl_channel_init(struct dram_para *para)
414 struct sunxi_mctl_com_reg * const mctl_com =
415 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
416 struct sunxi_mctl_ctl_reg * const mctl_ctl =
417 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
418 struct sunxi_mctl_phy_reg * const mctl_phy =
419 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
423 setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
424 setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
425 writel(0x2f05, &mctl_ctl->sched[0]);
426 setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
427 setbits_le32(&mctl_ctl->dfimisc, BIT(0));
428 setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
429 clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
430 /* TODO: non-LPDDR3 types */
431 clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
432 clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
433 clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
434 /* TODO: VT compensation */
435 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
436 clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
438 for (i = 0; i < 4; i++)
439 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
440 for (i = 0; i < 4; i++)
441 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
442 for (i = 0; i < 4; i++)
443 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
447 if (para->ranks == 2)
448 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
450 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
452 if (sunxi_dram_is_lpddr(para->type))
453 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
454 if (para->ranks == 2) {
455 writel(0x00010001, &mctl_phy->rankidr);
456 writel(0x20000, &mctl_phy->odtcr);
458 writel(0x0, &mctl_phy->rankidr);
459 writel(0x10000, &mctl_phy->odtcr);
462 /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
463 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
464 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
466 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
467 if (para->clk <= 792) {
468 if (para->clk <= 672) {
469 if (para->clk <= 600)
479 /* FIXME: NOT REVIEWED YET */
480 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
481 clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
482 CONFIG_DRAM_ZQ & 0xff);
483 clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
484 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
485 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
486 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
487 clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
488 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
489 setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
490 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
491 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
492 for (i = 1; i < 14; i++)
493 writel(0x06060606, &mctl_phy->acbdlr[i]);
496 val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
497 PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
498 if (para->type == SUNXI_DRAM_TYPE_DDR3)
499 val |= PIR_DRAMRST | PIR_WL;
500 mctl_phy_pir_init(val);
502 /* TODO: DDR4 types ? */
503 for (i = 0; i < 4; i++)
504 writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
506 for (i = 0; i < 4; i++) {
507 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
511 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
513 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
517 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
520 mctl_bit_delay_set(para);
523 setbits_le32(&mctl_phy->pgcr[6], BIT(0));
524 clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
525 for (i = 0; i < 4; i++)
526 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
529 if (readl(&mctl_phy->pgsr[0]) & 0x400000)
531 /* Check for single rank and optionally half DQ. */
532 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
533 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
536 if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
537 (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
538 para->bus_full_width = 0;
540 /* Restart DRAM initialization from scratch. */
541 mctl_core_init(para);
546 * Check for dual rank and half DQ. NOTE: This combination
547 * is highly unlikely and was not tested. Condition is the
548 * same as in libdram, though.
550 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
551 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
552 para->bus_full_width = 0;
554 /* Restart DRAM initialization from scratch. */
555 mctl_core_init(para);
559 panic("This DRAM setup is currently not supported.\n");
562 if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
563 /* Oops! There's something wrong! */
564 debug("PLL = %x\n", readl(0x3001010));
565 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
566 for (i = 0; i < 4; i++)
567 debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
568 panic("Error while initializing DRAM PHY!\n");
571 if (sunxi_dram_is_lpddr(para->type))
572 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
573 clrbits_le32(&mctl_phy->pgcr[1], 0x40);
574 clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
575 writel(1, &mctl_ctl->swctl);
576 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
577 clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
579 setbits_le32(&mctl_com->unk_0x014, BIT(31));
580 writel(0xffffffff, &mctl_com->maer0);
581 writel(0x7ff, &mctl_com->maer1);
582 writel(0xffff, &mctl_com->maer2);
585 static void mctl_auto_detect_dram_size(struct dram_para *para)
587 /* TODO: non-(LP)DDR3 */
588 /* Detect rank number and half DQ by the code in mctl_channel_init. */
589 mctl_core_init(para);
591 /* detect row address bits */
594 mctl_core_init(para);
596 for (para->rows = 13; para->rows < 18; para->rows++) {
597 /* 8 banks, 8 bit per byte and 16/32 bit width */
598 if (mctl_mem_matches((1 << (para->rows + para->cols +
599 4 + para->bus_full_width))))
603 /* detect column address bits */
605 mctl_core_init(para);
607 for (para->cols = 8; para->cols < 11; para->cols++) {
608 /* 8 bits per byte and 16/32 bit width */
609 if (mctl_mem_matches(1 << (para->cols + 1 +
610 para->bus_full_width)))
615 unsigned long mctl_calc_size(struct dram_para *para)
617 u8 width = para->bus_full_width ? 4 : 2;
619 /* TODO: non-(LP)DDR3 */
622 return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
625 #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
626 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
627 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
628 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
629 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
630 #define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
631 {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
632 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
633 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
634 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
636 #define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
637 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
641 #define SUN50I_H6_DDR3_DX_READ_DELAYS \
642 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
643 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
644 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
645 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
647 unsigned long sunxi_dram_init(void)
649 struct sunxi_mctl_com_reg * const mctl_com =
650 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
651 struct dram_para para = {
652 .clk = CONFIG_DRAM_CLK,
657 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
658 .type = SUNXI_DRAM_TYPE_LPDDR3,
659 .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
660 .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
661 #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
662 .type = SUNXI_DRAM_TYPE_DDR3,
663 .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
664 .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
670 /* RES_CAL_CTRL_REG in BSP U-boot*/
671 setbits_le32(0x7010310, BIT(8));
672 clrbits_le32(0x7010318, 0x3f);
674 mctl_auto_detect_dram_size(¶);
676 mctl_core_init(¶);
678 size = mctl_calc_size(¶);
680 clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
682 mctl_set_master_priority();