1 // SPDX-License-Identifier: GPL-2.0+
3 * sun50i H6 platform dram controller init
5 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/dram.h>
14 #include <asm/arch/cpu.h>
15 #include <linux/bitops.h>
16 #include <linux/kconfig.h>
19 * The DRAM controller structure on H6 is similar to the ones on A23/A80:
20 * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
21 * /H5/R40 CTL and PHY is composed).
23 * COM is allwinner-specific. On H6, the address mapping function is moved
24 * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
27 * CTL (controller) and PHY is from DesignWare.
29 * The CTL part is a bit similar to the one on A23/A80 (because they all
30 * originate from DesignWare), but gets more registers added.
32 * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
33 * not seen on other SoCs in U-Boot. The only SoC that is also known to have
34 * similar PHY is ZynqMP.
37 static void mctl_sys_init(struct dram_para *para);
38 static void mctl_com_init(struct dram_para *para);
39 static void mctl_channel_init(struct dram_para *para);
41 static void mctl_core_init(struct dram_para *para)
46 case SUNXI_DRAM_TYPE_LPDDR3:
47 case SUNXI_DRAM_TYPE_DDR3:
48 mctl_set_timing_params(para);
51 panic("Unsupported DRAM type!");
53 mctl_channel_init(para);
56 /* PHY initialisation */
57 static void mctl_phy_pir_init(u32 val)
59 struct sunxi_mctl_phy_reg * const mctl_phy =
60 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
62 writel(val, &mctl_phy->pir);
63 writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
64 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
94 inline void mbus_configure_port(u8 port,
104 struct sunxi_mctl_com_reg * const mctl_com =
105 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
107 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
108 | (priority ? (1 << 1) : 0)
110 | ((waittime & 0xf) << 4)
111 | ((acs & 0xff) << 8)
113 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
115 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
116 writel(cfg0, &mctl_com->master[port].cfg0);
117 writel(cfg1, &mctl_com->master[port].cfg1);
120 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
121 mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
122 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
124 static void mctl_set_master_priority(void)
126 struct sunxi_mctl_com_reg * const mctl_com =
127 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
129 /* enable bandwidth limit windows and set windows size 1us */
130 writel(399, &mctl_com->tmr);
131 writel(BIT(16), &mctl_com->bwcr);
133 MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
134 MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
135 MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
136 MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
137 MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
138 MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
139 MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
140 MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
141 MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
142 MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
143 MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
144 MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
145 MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
146 MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
147 MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
148 MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
149 MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
152 static void mctl_sys_init(struct dram_para *para)
154 struct sunxi_ccm_reg * const ccm =
155 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
156 struct sunxi_mctl_com_reg * const mctl_com =
157 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
158 struct sunxi_mctl_ctl_reg * const mctl_ctl =
159 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
161 /* Put all DRAM-related blocks to reset state */
162 clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
163 clrbits_le32(&ccm->dram_gate_reset, BIT(0));
165 writel(0, &ccm->dram_gate_reset);
166 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
167 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
171 /* Set PLL5 rate to doubled DRAM clock rate */
172 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
173 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
174 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
176 /* Configure DRAM mod clock */
177 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
178 setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
179 writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
181 setbits_le32(&ccm->dram_gate_reset, BIT(0));
183 /* Disable all channels */
184 writel(0, &mctl_com->maer0);
185 writel(0, &mctl_com->maer1);
186 writel(0, &mctl_com->maer2);
188 /* Configure MBUS and enable DRAM mod reset */
189 setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
190 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
191 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
194 /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
195 writel(0x8000, &mctl_ctl->unk_0x00c);
198 static void mctl_set_addrmap(struct dram_para *para)
200 struct sunxi_mctl_ctl_reg * const mctl_ctl =
201 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
202 u8 cols = para->cols;
203 u8 rows = para->rows;
204 u8 ranks = para->ranks;
206 if (!para->bus_full_width)
211 mctl_ctl->addrmap[0] = rows + cols - 3;
213 mctl_ctl->addrmap[0] = 0x1F;
215 /* Banks, hardcoded to 8 banks now */
216 mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
219 mctl_ctl->addrmap[2] = 0;
222 mctl_ctl->addrmap[3] = 0x1F1F1F00;
223 mctl_ctl->addrmap[4] = 0x1F1F;
226 mctl_ctl->addrmap[3] = 0x1F1F0000;
227 mctl_ctl->addrmap[4] = 0x1F1F;
230 mctl_ctl->addrmap[3] = 0x1F000000;
231 mctl_ctl->addrmap[4] = 0x1F1F;
234 mctl_ctl->addrmap[3] = 0;
235 mctl_ctl->addrmap[4] = 0x1F1F;
238 mctl_ctl->addrmap[3] = 0;
239 mctl_ctl->addrmap[4] = 0x1F00;
242 mctl_ctl->addrmap[3] = 0;
243 mctl_ctl->addrmap[4] = 0;
246 panic("Unsupported DRAM configuration: column number invalid\n");
250 mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
253 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
254 mctl_ctl->addrmap[7] = 0x0F0F;
257 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
258 mctl_ctl->addrmap[7] = 0x0F0F;
261 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
262 mctl_ctl->addrmap[7] = 0x0F0F;
265 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
266 mctl_ctl->addrmap[7] = 0x0F0F;
269 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
270 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
273 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
274 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
277 panic("Unsupported DRAM configuration: row number invalid\n");
280 /* Bank groups, DDR4 only */
281 mctl_ctl->addrmap[8] = 0x3F3F;
284 static void mctl_com_init(struct dram_para *para)
286 struct sunxi_mctl_com_reg * const mctl_com =
287 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
288 struct sunxi_mctl_ctl_reg * const mctl_ctl =
289 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
290 struct sunxi_mctl_phy_reg * const mctl_phy =
291 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
294 mctl_set_addrmap(para);
296 setbits_le32(&mctl_com->cr, BIT(31));
298 /* The bonding ID seems to be always 7. */
299 if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
300 clrbits_le32(&mctl_com->cr, BIT(27));
301 else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
302 setbits_le32(&mctl_com->cr, BIT(27));
306 else if (para->clk > 246)
310 clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
313 reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
314 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
315 reg_val |= MSTR_DEVICETYPE_LPDDR3;
316 if (para->type == SUNXI_DRAM_TYPE_DDR3)
317 reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
318 if (para->bus_full_width)
319 reg_val |= MSTR_BUSWIDTH_FULL;
321 reg_val |= MSTR_BUSWIDTH_HALF;
322 writel(reg_val | BIT(31), &mctl_ctl->mstr);
324 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
325 reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
326 if (para->type == SUNXI_DRAM_TYPE_DDR3)
327 reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
328 writel(reg_val | 0x400, &mctl_phy->dcr);
330 if (para->ranks == 2)
331 writel(0x0303, &mctl_ctl->odtmap);
333 writel(0x0201, &mctl_ctl->odtmap);
336 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
337 tmp = para->clk * 7 / 2000;
339 reg_val |= (tmp + 7) << 24;
340 reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
341 } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
342 reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
344 panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
346 writel(reg_val, &mctl_ctl->odtcfg);
348 if (!para->bus_full_width) {
349 writel(0x0, &mctl_phy->dx[2].gcr[0]);
350 writel(0x0, &mctl_phy->dx[3].gcr[0]);
354 static void mctl_bit_delay_set(struct dram_para *para)
356 struct sunxi_mctl_phy_reg * const mctl_phy =
357 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
361 for (i = 0; i < 4; i++) {
362 val = readl(&mctl_phy->dx[i].bdlr0);
363 for (j = 0; j < 4; j++)
364 val += para->dx_write_delays[i][j] << (j * 8);
365 writel(val, &mctl_phy->dx[i].bdlr0);
367 val = readl(&mctl_phy->dx[i].bdlr1);
368 for (j = 0; j < 4; j++)
369 val += para->dx_write_delays[i][j + 4] << (j * 8);
370 writel(val, &mctl_phy->dx[i].bdlr1);
372 val = readl(&mctl_phy->dx[i].bdlr2);
373 for (j = 0; j < 4; j++)
374 val += para->dx_write_delays[i][j + 8] << (j * 8);
375 writel(val, &mctl_phy->dx[i].bdlr2);
377 clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
379 for (i = 0; i < 4; i++) {
380 val = readl(&mctl_phy->dx[i].bdlr3);
381 for (j = 0; j < 4; j++)
382 val += para->dx_read_delays[i][j] << (j * 8);
383 writel(val, &mctl_phy->dx[i].bdlr3);
385 val = readl(&mctl_phy->dx[i].bdlr4);
386 for (j = 0; j < 4; j++)
387 val += para->dx_read_delays[i][j + 4] << (j * 8);
388 writel(val, &mctl_phy->dx[i].bdlr4);
390 val = readl(&mctl_phy->dx[i].bdlr5);
391 for (j = 0; j < 4; j++)
392 val += para->dx_read_delays[i][j + 8] << (j * 8);
393 writel(val, &mctl_phy->dx[i].bdlr5);
395 val = readl(&mctl_phy->dx[i].bdlr6);
396 val += (para->dx_read_delays[i][12] << 8) |
397 (para->dx_read_delays[i][13] << 16);
398 writel(val, &mctl_phy->dx[i].bdlr6);
400 setbits_le32(&mctl_phy->pgcr[0], BIT(26));
403 if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
406 for (i = 1; i < 14; i++) {
407 val = readl(&mctl_phy->acbdlr[i]);
409 writel(val, &mctl_phy->acbdlr[i]);
413 static void mctl_channel_init(struct dram_para *para)
415 struct sunxi_mctl_com_reg * const mctl_com =
416 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
417 struct sunxi_mctl_ctl_reg * const mctl_ctl =
418 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
419 struct sunxi_mctl_phy_reg * const mctl_phy =
420 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
424 setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
425 setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
426 writel(0x2f05, &mctl_ctl->sched[0]);
427 setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
428 setbits_le32(&mctl_ctl->dfimisc, BIT(0));
429 setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
430 clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
431 /* TODO: non-LPDDR3 types */
432 clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
433 clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
434 clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
435 /* TODO: VT compensation */
436 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
437 clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
439 for (i = 0; i < 4; i++)
440 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
441 for (i = 0; i < 4; i++)
442 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
443 for (i = 0; i < 4; i++)
444 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
448 if (para->ranks == 2)
449 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
451 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
453 if (sunxi_dram_is_lpddr(para->type))
454 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
455 if (para->ranks == 2) {
456 writel(0x00010001, &mctl_phy->rankidr);
457 writel(0x20000, &mctl_phy->odtcr);
459 writel(0x0, &mctl_phy->rankidr);
460 writel(0x10000, &mctl_phy->odtcr);
463 /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
464 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
465 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
467 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
468 if (para->clk <= 792) {
469 if (para->clk <= 672) {
470 if (para->clk <= 600)
480 /* FIXME: NOT REVIEWED YET */
481 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
482 clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
483 CONFIG_DRAM_ZQ & 0xff);
484 clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
485 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
486 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
487 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
488 clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
489 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
490 setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
491 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
492 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
493 for (i = 1; i < 14; i++)
494 writel(0x06060606, &mctl_phy->acbdlr[i]);
497 val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
498 PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
499 if (para->type == SUNXI_DRAM_TYPE_DDR3)
500 val |= PIR_DRAMRST | PIR_WL;
501 mctl_phy_pir_init(val);
503 /* TODO: DDR4 types ? */
504 for (i = 0; i < 4; i++)
505 writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
507 for (i = 0; i < 4; i++) {
508 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
512 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
514 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
518 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
521 mctl_bit_delay_set(para);
524 setbits_le32(&mctl_phy->pgcr[6], BIT(0));
525 clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
526 for (i = 0; i < 4; i++)
527 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
530 if (readl(&mctl_phy->pgsr[0]) & 0x400000)
532 /* Check for single rank and optionally half DQ. */
533 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
534 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
537 if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
538 (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
539 para->bus_full_width = 0;
541 /* Restart DRAM initialization from scratch. */
542 mctl_core_init(para);
547 * Check for dual rank and half DQ. NOTE: This combination
548 * is highly unlikely and was not tested. Condition is the
549 * same as in libdram, though.
551 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
552 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
553 para->bus_full_width = 0;
555 /* Restart DRAM initialization from scratch. */
556 mctl_core_init(para);
560 panic("This DRAM setup is currently not supported.\n");
563 if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
564 /* Oops! There's something wrong! */
565 debug("PLL = %x\n", readl(0x3001010));
566 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
567 for (i = 0; i < 4; i++)
568 debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
569 panic("Error while initializing DRAM PHY!\n");
572 if (sunxi_dram_is_lpddr(para->type))
573 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
574 clrbits_le32(&mctl_phy->pgcr[1], 0x40);
575 clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
576 writel(1, &mctl_ctl->swctl);
577 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
578 clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
580 setbits_le32(&mctl_com->unk_0x014, BIT(31));
581 writel(0xffffffff, &mctl_com->maer0);
582 writel(0x7ff, &mctl_com->maer1);
583 writel(0xffff, &mctl_com->maer2);
586 static void mctl_auto_detect_dram_size(struct dram_para *para)
588 /* TODO: non-(LP)DDR3 */
589 /* Detect rank number and half DQ by the code in mctl_channel_init. */
590 mctl_core_init(para);
592 /* detect row address bits */
595 mctl_core_init(para);
597 for (para->rows = 13; para->rows < 18; para->rows++) {
598 /* 8 banks, 8 bit per byte and 16/32 bit width */
599 if (mctl_mem_matches((1 << (para->rows + para->cols +
600 4 + para->bus_full_width))))
604 /* detect column address bits */
606 mctl_core_init(para);
608 for (para->cols = 8; para->cols < 11; para->cols++) {
609 /* 8 bits per byte and 16/32 bit width */
610 if (mctl_mem_matches(1 << (para->cols + 1 +
611 para->bus_full_width)))
616 unsigned long mctl_calc_size(struct dram_para *para)
618 u8 width = para->bus_full_width ? 4 : 2;
620 /* TODO: non-(LP)DDR3 */
623 return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
626 #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
627 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
628 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
629 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
630 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
631 #define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
632 {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
633 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
634 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
635 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
637 #define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
638 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
641 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
642 #define SUN50I_H6_DDR3_DX_READ_DELAYS \
643 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
644 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
645 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
646 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
648 unsigned long sunxi_dram_init(void)
650 struct sunxi_mctl_com_reg * const mctl_com =
651 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
652 struct dram_para para = {
653 .clk = CONFIG_DRAM_CLK,
658 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
659 .type = SUNXI_DRAM_TYPE_LPDDR3,
660 .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
661 .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
662 #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
663 .type = SUNXI_DRAM_TYPE_DDR3,
664 .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
665 .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
671 /* RES_CAL_CTRL_REG in BSP U-boot*/
672 setbits_le32(0x7010310, BIT(8));
673 clrbits_le32(0x7010318, 0x3f);
675 mctl_auto_detect_dram_size(¶);
677 mctl_core_init(¶);
679 size = mctl_calc_size(¶);
681 clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
683 mctl_set_master_priority();