arch/arm/mach-sunxi/clock_sun4i.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sun4i, sun5i and sun7i specific clock code
   4  *
   5  * (C) Copyright 2007-2012
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * Tom Cubie <tangliang@allwinnertech.com>
   8  *
   9  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 #ifdef CONFIG_SPL_BUILD
  18 void clock_init_safe(void)
  19 {
  20         struct sunxi_ccm_reg * const ccm =
  21                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  22
  23         /* Set safe defaults until PMU is configured */
  24         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
  25                AHB_DIV_2 << AHB_DIV_SHIFT |
  26                APB0_DIV_1 << APB0_DIV_SHIFT |
  27                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
  28                &ccm->cpu_ahb_apb0_cfg);
  29         writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
  30         sdelay(200);
  31         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
  32                AHB_DIV_2 << AHB_DIV_SHIFT |
  33                APB0_DIV_1 << APB0_DIV_SHIFT |
  34                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
  35                &ccm->cpu_ahb_apb0_cfg);
  36 #ifdef CONFIG_MACH_SUN7I
  37         setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
  38 #endif
  39         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  40 #ifdef CONFIG_SUNXI_AHCI
  41         setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
  42         setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
  43 #endif
  44 }
  45 #endif
  46
  47 void clock_init_uart(void)
  48 {
  49         struct sunxi_ccm_reg *const ccm =
  50                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  51
  52         /* uart clock source is apb1 */
  53         writel(APB1_CLK_SRC_OSC24M|
  54                APB1_CLK_RATE_N_1|
  55                APB1_CLK_RATE_M(1),
  56                &ccm->apb1_clk_div_cfg);
  57
  58         /* open the clock for uart */
  59         setbits_le32(&ccm->apb1_gate,
  60                 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));
  61 }
  62
  63 int clock_twi_onoff(int port, int state)
  64 {
  65         struct sunxi_ccm_reg *const ccm =
  66                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  67
  68         /* set the apb clock gate for twi */
  69         if (state)
  70                 setbits_le32(&ccm->apb1_gate,
  71                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
  72         else
  73                 clrbits_le32(&ccm->apb1_gate,
  74                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
  75
  76         return 0;
  77 }
  78
  79 #ifdef CONFIG_SPL_BUILD
  80 #define PLL1_CFG(N, K, M, P)    ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
  81                                   0 << CCM_PLL1_CFG_VCO_RST_SHIFT |  \
  82                                   8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
  83                                   0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
  84                                  16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
  85                                  (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
  86                                   2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
  87                                  (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
  88                                  (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
  89                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
  90                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
  91                                  (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
  92
  93 static struct {
  94         u32 pll1_cfg;
  95         unsigned int freq;
  96 } pll1_para[] = {
  97         /* This array must be ordered by frequency. */
  98         { PLL1_CFG(31, 1, 0, 0), 1488000000},
  99         { PLL1_CFG(30, 1, 0, 0), 1440000000},
 100         { PLL1_CFG(29, 1, 0, 0), 1392000000},
 101         { PLL1_CFG(28, 1, 0, 0), 1344000000},
 102         { PLL1_CFG(27, 1, 0, 0), 1296000000},
 103         { PLL1_CFG(26, 1, 0, 0), 1248000000},
 104         { PLL1_CFG(25, 1, 0, 0), 1200000000},
 105         { PLL1_CFG(24, 1, 0, 0), 1152000000},
 106         { PLL1_CFG(23, 1, 0, 0), 1104000000},
 107         { PLL1_CFG(22, 1, 0, 0), 1056000000},
 108         { PLL1_CFG(21, 1, 0, 0), 1008000000},
 109         { PLL1_CFG(20, 1, 0, 0), 960000000 },
 110         { PLL1_CFG(19, 1, 0, 0), 912000000 },
 111         { PLL1_CFG(16, 1, 0, 0), 768000000 },
 112         /* Final catchall entry 384MHz*/
 113         { PLL1_CFG(16, 0, 0, 0), 0 },
 114
 115 };
 116
 117 void clock_set_pll1(unsigned int hz)
 118 {
 119         int i = 0;
 120         int axi, ahb, apb0;
 121         struct sunxi_ccm_reg * const ccm =
 122                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 123
 124         /* Find target frequency */
 125         while (pll1_para[i].freq > hz)
 126                 i++;
 127
 128         hz = pll1_para[i].freq;
 129         if (! hz)
 130                 hz = 384000000;
 131
 132         /* Calculate system clock divisors */
 133         axi = DIV_ROUND_UP(hz, 432000000);      /* Max 450MHz */
 134         ahb = DIV_ROUND_UP(hz/axi, 204000000);  /* Max 250MHz */
 135         apb0 = 2;                               /* Max 150MHz */
 136
 137         printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
 138
 139         /* Map divisors to register values */
 140         axi = axi - 1;
 141         if (ahb > 4)
 142                 ahb = 3;
 143         else if (ahb > 2)
 144                 ahb = 2;
 145         else if (ahb > 1)
 146                 ahb = 1;
 147         else
 148                 ahb = 0;
 149
 150         apb0 = apb0 - 1;
 151
 152         /* Switch to 24MHz clock while changing PLL1 */
 153         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
 154                AHB_DIV_2 << AHB_DIV_SHIFT |
 155                APB0_DIV_1 << APB0_DIV_SHIFT |
 156                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 157                &ccm->cpu_ahb_apb0_cfg);
 158         sdelay(20);
 159
 160         /* Configure sys clock divisors */
 161         writel(axi << AXI_DIV_SHIFT |
 162                ahb << AHB_DIV_SHIFT |
 163                apb0 << APB0_DIV_SHIFT |
 164                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 165                &ccm->cpu_ahb_apb0_cfg);
 166
 167         /* Configure PLL1 at the desired frequency */
 168         writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
 169         sdelay(200);
 170
 171         /* Switch CPU to PLL1 */
 172         writel(axi << AXI_DIV_SHIFT |
 173                ahb << AHB_DIV_SHIFT |
 174                apb0 << APB0_DIV_SHIFT |
 175                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 176                &ccm->cpu_ahb_apb0_cfg);
 177         sdelay(20);
 178 }
 179 #endif
 180
 181 void clock_set_pll3(unsigned int clk)
 182 {
 183         struct sunxi_ccm_reg * const ccm =
 184                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 185
 186         if (clk == 0) {
 187                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 188                 return;
 189         }
 190
 191         /* PLL3 rate = 3000000 * m */
 192         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 193                CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
 194 }
 195
 196 unsigned int clock_get_pll3(void)
 197 {
 198         struct sunxi_ccm_reg *const ccm =
 199                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 200         uint32_t rval = readl(&ccm->pll3_cfg);
 201         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT);
 202         return 3000000 * m;
 203 }
 204
 205 unsigned int clock_get_pll5p(void)
 206 {
 207         struct sunxi_ccm_reg *const ccm =
 208                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 209         uint32_t rval = readl(&ccm->pll5_cfg);
 210         int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
 211         int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
 212         int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
 213         return (24000000 * n * k) >> p;
 214 }
 215
 216 unsigned int clock_get_pll6(void)
 217 {
 218         struct sunxi_ccm_reg *const ccm =
 219                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 220         uint32_t rval = readl(&ccm->pll6_cfg);
 221         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
 222         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 223         return 24000000 * n * k / 2;
 224 }
 225
 226 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 227 {
 228         int pll = clock_get_pll5p();
 229         int div = 1;
 230
 231         while ((pll / div) > hz)
 232                 div++;
 233
 234         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
 235                CCM_DE_CTRL_M(div), clk_cfg);
 236 }