arch/arm/mach-sunxi/clock.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2012
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Tom Cubie <tangliang@allwinnertech.com>
   6  *
   7  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/prcm.h>
  14 #include <asm/arch/gtbus.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 __weak void clock_init_sec(void)
  18 {
  19 }
  20
  21 __weak void gtbus_init(void)
  22 {
  23 }
  24
  25 int clock_init(void)
  26 {
  27 #ifdef CONFIG_SPL_BUILD
  28         clock_init_safe();
  29         gtbus_init();
  30 #endif
  31         clock_init_uart();
  32         clock_init_sec();
  33
  34         return 0;
  35 }
  36
  37 /* These functions are shared between various SoCs so put them here. */
  38 #if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
  39 int clock_twi_onoff(int port, int state)
  40 {
  41         struct sunxi_ccm_reg *const ccm =
  42                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  43
  44         if (port == 5) {
  45                 if (state)
  46                         prcm_apb0_enable(
  47                                 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
  48                 else
  49                         prcm_apb0_disable(
  50                                 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
  51                 return 0;
  52         }
  53
  54         /* set the apb clock gate and reset for twi */
  55         if (state) {
  56                 setbits_le32(&ccm->apb2_gate,
  57                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
  58                 setbits_le32(&ccm->apb2_reset_cfg,
  59                              1 << (APB2_RESET_TWI_SHIFT + port));
  60         } else {
  61                 clrbits_le32(&ccm->apb2_reset_cfg,
  62                              1 << (APB2_RESET_TWI_SHIFT + port));
  63                 clrbits_le32(&ccm->apb2_gate,
  64                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
  65         }
  66
  67         return 0;
  68 }
  69 #endif