1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some init for sunxi platform.
20 #include <asm/cache.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/spl.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/timer.h>
28 #include <asm/arch/tzpc.h>
29 #include <asm/arch/mmc.h>
31 #include <linux/compiler.h>
42 struct fel_stash fel_stash __attribute__((section(".data")));
45 #include <asm/armv8/mmu.h>
47 static struct mm_region sunxi_mem_map[] = {
49 /* SRAM, MMIO regions */
53 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
60 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
67 struct mm_region *mem_map = sunxi_mem_map;
70 static int gpio_init(void)
72 __maybe_unused uint val;
73 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
74 #if defined(CONFIG_MACH_SUN4I) || \
75 defined(CONFIG_MACH_SUN7I) || \
76 defined(CONFIG_MACH_SUN8I_R40)
77 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
78 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
79 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
81 #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
82 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
83 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
85 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
86 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
88 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
89 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
90 defined(CONFIG_MACH_SUN7I) || \
91 defined(CONFIG_MACH_SUN8I_R40))
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
94 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
95 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
98 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
99 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
102 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
103 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
104 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
106 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
107 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
108 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
110 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
111 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
114 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
115 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
118 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
119 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
122 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
123 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
126 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
127 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
130 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
131 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
134 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
135 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
136 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
137 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
138 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
139 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
140 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
141 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
142 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
143 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
144 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
145 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
146 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
148 #error Unsupported console port number. Please fix pin mux settings in board.c
151 #ifdef CONFIG_SUN50I_GEN_H6
152 /* Update PIO power bias configuration by copy hardware detected value */
153 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
154 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
155 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
156 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
162 #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
163 static int spl_board_load_image(struct spl_image_info *spl_image,
164 struct spl_boot_device *bootdev)
166 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
167 return_to_fel(fel_stash.sp, fel_stash.lr);
171 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
177 * Undocumented magic taken from boot0, without this DRAM
178 * access gets messed up (seems cache related).
179 * The boot0 sources describe this as: "config ema for cache sram"
181 #if defined CONFIG_MACH_SUN6I
182 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
183 #elif defined CONFIG_MACH_SUN8I
184 __maybe_unused uint version;
186 /* Unlock sram version info reg, read it, relock */
187 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
188 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
189 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
192 * Ideally this would be a switch case, but we do not know exactly
193 * which versions there are and which version needs which settings,
194 * so reproduce the per SoC code from the BSP.
196 #if defined CONFIG_MACH_SUN8I_A23
197 if (version == 0x1650)
198 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
200 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
201 #elif defined CONFIG_MACH_SUN8I_A33
202 if (version != 0x1667)
203 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
205 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
206 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
209 #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
210 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
212 "mrc p15, 0, r0, c1, c0, 1\n"
213 "orr r0, r0, #1 << 6\n"
214 "mcr p15, 0, r0, c1, c0, 1\n"
217 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
218 /* Enable non-secure access to some peripherals */
225 #ifndef CONFIG_DM_I2C
231 #define SUNXI_INVALID_BOOT_SOURCE -1
233 static int sunxi_get_boot_source(void)
235 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
236 return SUNXI_INVALID_BOOT_SOURCE;
238 return readb(SPL_ADDR + 0x28);
241 /* The sunxi internal brom will try to loader external bootloader
242 * from mmc0, nand flash, mmc2.
244 uint32_t sunxi_get_boot_device(void)
246 int boot_source = sunxi_get_boot_source();
249 * When booting from the SD card or NAND memory, the "eGON.BT0"
250 * signature is expected to be found in memory at the address 0x0004
251 * (see the "mksunxiboot" tool, which generates this header).
253 * When booting in the FEL mode over USB, this signature is patched in
254 * memory and replaced with something else by the 'fel' tool. This other
255 * signature is selected in such a way, that it can't be present in a
256 * valid bootable SD card image (because the BROM would refuse to
257 * execute the SPL in this case).
259 * This checks for the signature and if it is not found returns to
260 * the FEL code in the BROM to wait and receive the main u-boot
261 * binary over USB. If it is found, it determines where SPL was
264 switch (boot_source) {
265 case SUNXI_INVALID_BOOT_SOURCE:
266 return BOOT_DEVICE_BOARD;
267 case SUNXI_BOOTED_FROM_MMC0:
268 case SUNXI_BOOTED_FROM_MMC0_HIGH:
269 return BOOT_DEVICE_MMC1;
270 case SUNXI_BOOTED_FROM_NAND:
271 return BOOT_DEVICE_NAND;
272 case SUNXI_BOOTED_FROM_MMC2:
273 case SUNXI_BOOTED_FROM_MMC2_HIGH:
274 return BOOT_DEVICE_MMC2;
275 case SUNXI_BOOTED_FROM_SPI:
276 return BOOT_DEVICE_SPI;
279 panic("Unknown boot source %d\n", boot_source);
280 return -1; /* Never reached */
283 #ifdef CONFIG_SPL_BUILD
284 static u32 sunxi_get_spl_size(void)
286 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
289 return readl(SPL_ADDR + 0x10);
293 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
294 * an eMMC device. The boot source has bit 4 set in the latter case.
295 * By adding 120KB to the normal offset when booting from a "high" location
296 * we can support both cases.
297 * Also U-Boot proper is located at least 32KB after the SPL, but will
298 * immediately follow the SPL if that is bigger than that.
300 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
301 unsigned long raw_sect)
303 unsigned long spl_size = sunxi_get_spl_size();
304 unsigned long sector;
306 sector = max(raw_sect, spl_size / 512);
308 switch (sunxi_get_boot_source()) {
309 case SUNXI_BOOTED_FROM_MMC0_HIGH:
310 case SUNXI_BOOTED_FROM_MMC2_HIGH:
311 sector += (128 - 8) * 2;
318 u32 spl_boot_device(void)
320 return sunxi_get_boot_device();
323 void board_init_f(ulong dummy)
326 preloader_console_init();
328 #ifdef CONFIG_SPL_I2C_SUPPORT
329 /* Needed early by sunxi_board_init if PMU is enabled */
330 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
336 void reset_cpu(ulong addr)
338 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
339 static const struct sunxi_wdog *wdog =
340 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
342 /* Set the watchdog for its shortest interval (.5s) and wait */
343 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
344 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
347 /* sun5i sometimes gets stuck without this */
348 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
350 #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
351 #if defined(CONFIG_MACH_SUN50I_H6)
352 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
353 static const struct sunxi_wdog *wdog =
354 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
356 static const struct sunxi_wdog *wdog =
357 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
359 /* Set the watchdog for its shortest interval (.5s) and wait */
360 writel(WDT_CFG_RESET, &wdog->cfg);
361 writel(WDT_MODE_EN, &wdog->mode);
362 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
367 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
368 void enable_caches(void)
370 /* Enable D-cache. I-cache is already enabled in start.S */