1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some init for sunxi platform.
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/spl.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/timer.h>
25 #include <asm/arch/tzpc.h>
26 #include <asm/arch/mmc.h>
28 #include <linux/compiler.h>
39 struct fel_stash fel_stash __attribute__((section(".data")));
42 #include <asm/armv8/mmu.h>
44 static struct mm_region sunxi_mem_map[] = {
46 /* SRAM, MMIO regions */
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
64 struct mm_region *mem_map = sunxi_mem_map;
67 static int gpio_init(void)
69 __maybe_unused uint val;
70 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
71 #if defined(CONFIG_MACH_SUN4I) || \
72 defined(CONFIG_MACH_SUN7I) || \
73 defined(CONFIG_MACH_SUN8I_R40)
74 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
75 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
76 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
78 #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
79 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
80 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
82 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
83 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
85 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
86 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
87 defined(CONFIG_MACH_SUN7I) || \
88 defined(CONFIG_MACH_SUN8I_R40))
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
91 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
92 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
94 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
95 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
96 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
99 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
100 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
102 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
103 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
104 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
105 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
106 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
107 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
108 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
111 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
112 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
115 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
116 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
118 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
119 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
120 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
122 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
123 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
124 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
126 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
127 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
128 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
130 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
131 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
132 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
133 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
135 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
136 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
137 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
138 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
139 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
141 #error Unsupported console port number. Please fix pin mux settings in board.c
144 #ifdef CONFIG_MACH_SUN50I_H6
145 /* Update PIO power bias configuration by copy hardware detected value */
146 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
147 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
148 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
149 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
155 #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
156 static int spl_board_load_image(struct spl_image_info *spl_image,
157 struct spl_boot_device *bootdev)
159 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
160 return_to_fel(fel_stash.sp, fel_stash.lr);
164 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
170 * Undocumented magic taken from boot0, without this DRAM
171 * access gets messed up (seems cache related).
172 * The boot0 sources describe this as: "config ema for cache sram"
174 #if defined CONFIG_MACH_SUN6I
175 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
176 #elif defined CONFIG_MACH_SUN8I
177 __maybe_unused uint version;
179 /* Unlock sram version info reg, read it, relock */
180 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
181 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
182 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
185 * Ideally this would be a switch case, but we do not know exactly
186 * which versions there are and which version needs which settings,
187 * so reproduce the per SoC code from the BSP.
189 #if defined CONFIG_MACH_SUN8I_A23
190 if (version == 0x1650)
191 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
193 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
194 #elif defined CONFIG_MACH_SUN8I_A33
195 if (version != 0x1667)
196 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
198 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
199 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
202 #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
203 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
205 "mrc p15, 0, r0, c1, c0, 1\n"
206 "orr r0, r0, #1 << 6\n"
207 "mcr p15, 0, r0, c1, c0, 1\n"
210 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
211 /* Enable non-secure access to some peripherals */
218 #ifndef CONFIG_DM_I2C
224 /* The sunxi internal brom will try to loader external bootloader
225 * from mmc0, nand flash, mmc2.
227 uint32_t sunxi_get_boot_device(void)
232 * When booting from the SD card or NAND memory, the "eGON.BT0"
233 * signature is expected to be found in memory at the address 0x0004
234 * (see the "mksunxiboot" tool, which generates this header).
236 * When booting in the FEL mode over USB, this signature is patched in
237 * memory and replaced with something else by the 'fel' tool. This other
238 * signature is selected in such a way, that it can't be present in a
239 * valid bootable SD card image (because the BROM would refuse to
240 * execute the SPL in this case).
242 * This checks for the signature and if it is not found returns to
243 * the FEL code in the BROM to wait and receive the main u-boot
244 * binary over USB. If it is found, it determines where SPL was
247 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
248 return BOOT_DEVICE_BOARD;
250 boot_source = readb(SPL_ADDR + 0x28);
251 switch (boot_source) {
252 case SUNXI_BOOTED_FROM_MMC0:
253 case SUNXI_BOOTED_FROM_MMC0_HIGH:
254 return BOOT_DEVICE_MMC1;
255 case SUNXI_BOOTED_FROM_NAND:
256 return BOOT_DEVICE_NAND;
257 case SUNXI_BOOTED_FROM_MMC2:
258 case SUNXI_BOOTED_FROM_MMC2_HIGH:
259 return BOOT_DEVICE_MMC2;
260 case SUNXI_BOOTED_FROM_SPI:
261 return BOOT_DEVICE_SPI;
264 panic("Unknown boot source %d\n", boot_source);
265 return -1; /* Never reached */
268 #ifdef CONFIG_SPL_BUILD
269 u32 spl_boot_device(void)
271 return sunxi_get_boot_device();
274 void board_init_f(ulong dummy)
277 preloader_console_init();
279 #ifdef CONFIG_SPL_I2C_SUPPORT
280 /* Needed early by sunxi_board_init if PMU is enabled */
281 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
287 void reset_cpu(ulong addr)
289 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
290 static const struct sunxi_wdog *wdog =
291 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
293 /* Set the watchdog for its shortest interval (.5s) and wait */
294 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
295 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
298 /* sun5i sometimes gets stuck without this */
299 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
301 #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
302 #if defined(CONFIG_MACH_SUN50I_H6)
303 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
304 static const struct sunxi_wdog *wdog =
305 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
307 static const struct sunxi_wdog *wdog =
308 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
310 /* Set the watchdog for its shortest interval (.5s) and wait */
311 writel(WDT_CFG_RESET, &wdog->cfg);
312 writel(WDT_MODE_EN, &wdog->mode);
313 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
318 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
319 void enable_caches(void)
321 /* Enable D-cache. I-cache is already enabled in start.S */