1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some init for sunxi platform.
20 #include <asm/cache.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
30 #include <linux/compiler.h>
41 struct fel_stash fel_stash __section(".data");
44 #include <asm/armv8/mmu.h>
46 static struct mm_region sunxi_mem_map[] = {
48 /* SRAM, MMIO regions */
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 .size = CONFIG_SUNXI_DRAM_MAX_SIZE,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
66 struct mm_region *mem_map = sunxi_mem_map;
68 ulong board_get_usable_ram_top(ulong total_size)
70 /* Some devices (like the EMAC) have a 32-bit DMA limit. */
71 if (gd->ram_top > (1ULL << 32))
78 #ifdef CONFIG_SPL_BUILD
79 static int gpio_init(void)
81 __maybe_unused uint val;
82 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
83 #if defined(CONFIG_MACH_SUN4I) || \
84 defined(CONFIG_MACH_SUN7I) || \
85 defined(CONFIG_MACH_SUN8I_R40)
86 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
90 #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
91 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
92 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
94 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
97 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
98 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
99 defined(CONFIG_MACH_SUN7I) || \
100 defined(CONFIG_MACH_SUN8I_R40))
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
102 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
103 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
104 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
107 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
108 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
109 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
110 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
111 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
112 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
115 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
116 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
117 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
118 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
119 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
120 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
122 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
123 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
124 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
126 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
127 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
128 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
129 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
130 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
131 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
132 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
133 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
135 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
136 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
137 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
138 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
139 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
140 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
141 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
143 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
144 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
145 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
146 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
147 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
148 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
149 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
151 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
152 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
153 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
154 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
155 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
156 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
157 !defined(CONFIG_MACH_SUN8I_R40)
158 sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
159 sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
160 sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
162 #error Unsupported console port number. Please fix pin mux settings in board.c
165 #ifdef CONFIG_SUN50I_GEN_H6
166 /* Update PIO power bias configuration by copy hardware detected value */
167 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
168 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
169 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
170 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
176 static int spl_board_load_image(struct spl_image_info *spl_image,
177 struct spl_boot_device *bootdev)
179 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
180 return_to_fel(fel_stash.sp, fel_stash.lr);
184 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
187 #define SUNXI_INVALID_BOOT_SOURCE -1
189 static int sunxi_get_boot_source(void)
191 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
192 return SUNXI_INVALID_BOOT_SOURCE;
194 return readb(SPL_ADDR + 0x28);
197 /* The sunxi internal brom will try to loader external bootloader
198 * from mmc0, nand flash, mmc2.
200 uint32_t sunxi_get_boot_device(void)
202 int boot_source = sunxi_get_boot_source();
205 * When booting from the SD card or NAND memory, the "eGON.BT0"
206 * signature is expected to be found in memory at the address 0x0004
207 * (see the "mksunxiboot" tool, which generates this header).
209 * When booting in the FEL mode over USB, this signature is patched in
210 * memory and replaced with something else by the 'fel' tool. This other
211 * signature is selected in such a way, that it can't be present in a
212 * valid bootable SD card image (because the BROM would refuse to
213 * execute the SPL in this case).
215 * This checks for the signature and if it is not found returns to
216 * the FEL code in the BROM to wait and receive the main u-boot
217 * binary over USB. If it is found, it determines where SPL was
220 switch (boot_source) {
221 case SUNXI_INVALID_BOOT_SOURCE:
222 return BOOT_DEVICE_BOARD;
223 case SUNXI_BOOTED_FROM_MMC0:
224 case SUNXI_BOOTED_FROM_MMC0_HIGH:
225 return BOOT_DEVICE_MMC1;
226 case SUNXI_BOOTED_FROM_NAND:
227 return BOOT_DEVICE_NAND;
228 case SUNXI_BOOTED_FROM_MMC2:
229 case SUNXI_BOOTED_FROM_MMC2_HIGH:
230 return BOOT_DEVICE_MMC2;
231 case SUNXI_BOOTED_FROM_SPI:
232 return BOOT_DEVICE_SPI;
235 panic("Unknown boot source %d\n", boot_source);
236 return -1; /* Never reached */
239 #ifdef CONFIG_SPL_BUILD
240 static u32 sunxi_get_spl_size(void)
242 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
245 return readl(SPL_ADDR + 0x10);
249 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
250 * an eMMC device. The boot source has bit 4 set in the latter case.
251 * By adding 120KB to the normal offset when booting from a "high" location
252 * we can support both cases.
253 * Also U-Boot proper is located at least 32KB after the SPL, but will
254 * immediately follow the SPL if that is bigger than that.
256 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
257 unsigned long raw_sect)
259 unsigned long spl_size = sunxi_get_spl_size();
260 unsigned long sector;
262 sector = max(raw_sect, spl_size / 512);
264 switch (sunxi_get_boot_source()) {
265 case SUNXI_BOOTED_FROM_MMC0_HIGH:
266 case SUNXI_BOOTED_FROM_MMC2_HIGH:
267 sector += (128 - 8) * 2;
274 u32 spl_boot_device(void)
276 return sunxi_get_boot_device();
279 __weak void sunxi_sram_init(void)
283 void board_init_f(ulong dummy)
287 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
288 /* Enable non-secure access to some peripherals */
298 preloader_console_init();
300 #if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
301 /* Needed early by sunxi_board_init if PMU is enabled */
303 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
309 #if !CONFIG_IS_ENABLED(SYSRESET)
312 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
313 static const struct sunxi_wdog *wdog =
314 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
316 /* Set the watchdog for its shortest interval (.5s) and wait */
317 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
318 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
321 /* sun5i sometimes gets stuck without this */
322 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
324 #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
325 #if defined(CONFIG_MACH_SUN50I_H6)
326 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
327 static const struct sunxi_wdog *wdog =
328 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
330 static const struct sunxi_wdog *wdog =
331 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
333 /* Set the watchdog for its shortest interval (.5s) and wait */
334 writel(WDT_CFG_RESET, &wdog->cfg);
335 writel(WDT_MODE_EN, &wdog->mode);
336 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
342 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
343 void enable_caches(void)
345 /* Enable D-cache. I-cache is already enabled in start.S */