4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
154 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
157 bool "sun9i (Allwinner A80)"
159 select SUNXI_HIGH_SRAM
160 select SUNXI_GEN_SUN6I
164 bool "sun50i (Allwinner A64)"
168 select SUNXI_GEN_SUN6I
169 select SUNXI_HIGH_SRAM
172 select SUNXI_DRAM_DW_32BIT
176 config MACH_SUN50I_H5
177 bool "sun50i (Allwinner H5)"
179 select MACH_SUNXI_H3_H5
180 select SUNXI_HIGH_SRAM
186 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
189 default y if MACH_SUN8I_A23
190 default y if MACH_SUN8I_A33
191 default y if MACH_SUN8I_A83T
192 default y if MACH_SUNXI_H3_H5
193 default y if MACH_SUN8I_R40
194 default y if MACH_SUN8I_V3S
196 config RESERVE_ALLWINNER_BOOT0_HEADER
197 bool "reserve space for Allwinner boot0 header"
198 select ENABLE_ARM_SOC_BOOT0_HOOK
200 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
201 filled with magic values post build. The Allwinner provided boot0
202 blob relies on this information to load and execute U-Boot.
203 Only needed on 64-bit Allwinner boards so far when using boot0.
205 config ARM_BOOT_HOOK_RMR
209 select ENABLE_ARM_SOC_BOOT0_HOOK
211 Insert some ARM32 code at the very beginning of the U-Boot binary
212 which uses an RMR register write to bring the core into AArch64 mode.
213 The very first instruction acts as a switch, since it's carefully
214 chosen to be a NOP in one mode and a branch in the other, so the
215 code would only be executed if not already in AArch64.
216 This allows both the SPL and the U-Boot proper to be entered in
217 either mode and switch to AArch64 if needed.
220 config SUNXI_DRAM_DDR3
224 prompt "DRAM Type and Timing"
225 default SUNXI_DRAM_DDR3_1333
227 config SUNXI_DRAM_DDR3_1333
229 select SUNXI_DRAM_DDR3
231 This option is the original only supported memory type, which suits
232 many H3/H5/A64 boards available now.
238 int "sunxi dram type"
239 depends on MACH_SUN8I_A83T
242 Set the dram type, 3: DDR3, 7: LPDDR3
245 int "sunxi dram clock speed"
246 default 792 if MACH_SUN9I
247 default 648 if MACH_SUN8I_R40
248 default 312 if MACH_SUN6I || MACH_SUN8I
249 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
250 default 672 if MACH_SUN50I
252 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
253 must be a multiple of 24. For the sun9i (A80), the tested values
254 (for DDR3-1600) are 312 to 792.
256 if MACH_SUN5I || MACH_SUN7I
258 int "sunxi mbus clock speed"
261 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
266 int "sunxi dram zq value"
267 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
268 default 127 if MACH_SUN7I
269 default 3881979 if MACH_SUN8I_R40
270 default 4145117 if MACH_SUN9I
271 default 3881915 if MACH_SUN50I
273 Set the dram zq value.
276 bool "sunxi dram odt enable"
277 default n if !MACH_SUN8I_A23
278 default y if MACH_SUN8I_A23
279 default y if MACH_SUN8I_R40
280 default y if MACH_SUN50I
282 Select this to enable dram odt (on die termination).
284 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
286 int "sunxi dram emr1 value"
287 default 0 if MACH_SUN4I
288 default 4 if MACH_SUN5I || MACH_SUN7I
290 Set the dram controller emr1 value.
293 hex "sunxi dram tpr3 value"
296 Set the dram controller tpr3 parameter. This parameter configures
297 the delay on the command lane and also phase shifts, which are
298 applied for sampling incoming read data. The default value 0
299 means that no phase/delay adjustments are necessary. Properly
300 configuring this parameter increases reliability at high DRAM
303 config DRAM_DQS_GATING_DELAY
304 hex "sunxi dram dqs_gating_delay value"
307 Set the dram controller dqs_gating_delay parmeter. Each byte
308 encodes the DQS gating delay for each byte lane. The delay
309 granularity is 1/4 cycle. For example, the value 0x05060606
310 means that the delay is 5 quarter-cycles for one lane (1.25
311 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
312 The default value 0 means autodetection. The results of hardware
313 autodetection are not very reliable and depend on the chip
314 temperature (sometimes producing different results on cold start
315 and warm reboot). But the accuracy of hardware autodetection
316 is usually good enough, unless running at really high DRAM
317 clocks speeds (up to 600MHz). If unsure, keep as 0.
320 prompt "sunxi dram timings"
321 default DRAM_TIMINGS_VENDOR_MAGIC
323 Select the timings of the DDR3 chips.
325 config DRAM_TIMINGS_VENDOR_MAGIC
326 bool "Magic vendor timings from Android"
328 The same DRAM timings as in the Allwinner boot0 bootloader.
330 config DRAM_TIMINGS_DDR3_1066F_1333H
331 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
333 Use the timings of the standard JEDEC DDR3-1066F speed bin for
334 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
335 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
336 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
337 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
338 that down binning to DDR3-1066F is supported (because DDR3-1066F
339 uses a bit faster timings than DDR3-1333H).
341 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
342 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
344 Use the timings of the slowest possible JEDEC speed bin for the
345 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
346 DDR3-800E, DDR3-1066G or DDR3-1333J.
353 config DRAM_ODT_CORRECTION
354 int "sunxi dram odt correction value"
357 Set the dram odt correction value (range -255 - 255). In allwinner
358 fex files, this option is found in bits 8-15 of the u32 odt_en variable
359 in the [dram] section. When bit 31 of the odt_en variable is set
360 then the correction is negative. Usually the value for this is 0.
364 default 1008000000 if MACH_SUN4I
365 default 1008000000 if MACH_SUN5I
366 default 1008000000 if MACH_SUN6I
367 default 912000000 if MACH_SUN7I
368 default 1008000000 if MACH_SUN8I
369 default 1008000000 if MACH_SUN9I
370 default 816000000 if MACH_SUN50I
372 config SYS_CONFIG_NAME
373 default "sun4i" if MACH_SUN4I
374 default "sun5i" if MACH_SUN5I
375 default "sun6i" if MACH_SUN6I
376 default "sun7i" if MACH_SUN7I
377 default "sun8i" if MACH_SUN8I
378 default "sun9i" if MACH_SUN9I
379 default "sun50i" if MACH_SUN50I
388 bool "UART0 on MicroSD breakout board"
391 Repurpose the SD card slot for getting access to the UART0 serial
392 console. Primarily useful only for low level u-boot debugging on
393 tablets, where normal UART0 is difficult to access and requires
394 device disassembly and/or soldering. As the SD card can't be used
395 at the same time, the system can be only booted in the FEL mode.
396 Only enable this if you really know what you are doing.
398 config OLD_SUNXI_KERNEL_COMPAT
399 bool "Enable workarounds for booting old kernels"
402 Set this to enable various workarounds for old kernels, this results in
403 sub-optimal settings for newer kernels, only enable if needed.
406 string "MAC power pin"
409 Set the pin used to power the MAC. This takes a string in the format
410 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
413 string "Card detect pin for mmc0"
414 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
417 Set the card detect pin for mmc0, leave empty to not use cd. This
418 takes a string in the format understood by sunxi_name_to_gpio, e.g.
419 PH1 for pin 1 of port H.
422 string "Card detect pin for mmc1"
425 See MMC0_CD_PIN help text.
428 string "Card detect pin for mmc2"
431 See MMC0_CD_PIN help text.
434 string "Card detect pin for mmc3"
437 See MMC0_CD_PIN help text.
440 string "Pins for mmc1"
443 Set the pins used for mmc1, when applicable. This takes a string in the
444 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
447 string "Pins for mmc2"
450 See MMC1_PINS help text.
453 string "Pins for mmc3"
456 See MMC1_PINS help text.
458 config MMC_SUNXI_SLOT_EXTRA
459 int "mmc extra slot number"
462 sunxi builds always enable mmc0, some boards also have a second sdcard
463 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
466 config INITIAL_USB_SCAN_DELAY
467 int "delay initial usb scan by x ms to allow builtin devices to init"
470 Some boards have on board usb devices which need longer than the
471 USB spec's 1 second to connect from board powerup. Set this config
472 option to a non 0 value to add an extra delay before the first usb
476 string "Vbus enable pin for usb0 (otg)"
479 Set the Vbus enable pin for usb0 (otg). This takes a string in the
480 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
483 string "Vbus detect pin for usb0 (otg)"
486 Set the Vbus detect pin for usb0 (otg). This takes a string in the
487 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
490 string "ID detect pin for usb0 (otg)"
493 Set the ID detect pin for usb0 (otg). This takes a string in the
494 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
497 string "Vbus enable pin for usb1 (ehci0)"
498 default "PH6" if MACH_SUN4I || MACH_SUN7I
499 default "PH27" if MACH_SUN6I
501 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
502 a string in the format understood by sunxi_name_to_gpio, e.g.
503 PH1 for pin 1 of port H.
506 string "Vbus enable pin for usb2 (ehci1)"
507 default "PH3" if MACH_SUN4I || MACH_SUN7I
508 default "PH24" if MACH_SUN6I
510 See USB1_VBUS_PIN help text.
513 string "Vbus enable pin for usb3 (ehci2)"
516 See USB1_VBUS_PIN help text.
519 bool "Enable I2C/TWI controller 0"
520 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
521 default n if MACH_SUN6I || MACH_SUN8I
524 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
525 its clock and setting up the bus. This is especially useful on devices
526 with slaves connected to the bus or with pins exposed through e.g. an
527 expansion port/header.
530 bool "Enable I2C/TWI controller 1"
534 See I2C0_ENABLE help text.
537 bool "Enable I2C/TWI controller 2"
541 See I2C0_ENABLE help text.
543 if MACH_SUN6I || MACH_SUN7I
545 bool "Enable I2C/TWI controller 3"
549 See I2C0_ENABLE help text.
554 bool "Enable the PRCM I2C/TWI controller"
555 # This is used for the pmic on H3
556 default y if SY8106A_POWER
559 Set this to y to enable the I2C controller which is part of the PRCM.
564 bool "Enable I2C/TWI controller 4"
568 See I2C0_ENABLE help text.
572 bool "Enable support for gpio-s on axp PMICs"
575 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
578 bool "Enable graphical uboot console on HDMI, LCD or VGA"
579 depends on !MACH_SUN8I_A83T
580 depends on !MACH_SUNXI_H3_H5
581 depends on !MACH_SUN8I_R40
582 depends on !MACH_SUN8I_V3S
583 depends on !MACH_SUN9I
584 depends on !MACH_SUN50I
587 Say Y here to add support for using a cfb console on the HDMI, LCD
588 or VGA output found on most sunxi devices. See doc/README.video for
589 info on how to select the video output and mode.
592 bool "HDMI output support"
593 depends on VIDEO && !MACH_SUN8I
596 Say Y here to add support for outputting video over HDMI.
599 bool "VGA output support"
600 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
603 Say Y here to add support for outputting video over VGA.
605 config VIDEO_VGA_VIA_LCD
606 bool "VGA via LCD controller support"
607 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
610 Say Y here to add support for external DACs connected to the parallel
611 LCD interface driving a VGA connector, such as found on the
614 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
615 bool "Force sync active high for VGA via LCD controller support"
616 depends on VIDEO_VGA_VIA_LCD
619 Say Y here if you've a board which uses opendrain drivers for the vga
620 hsync and vsync signals. Opendrain drivers cannot generate steep enough
621 positive edges for a stable video output, so on boards with opendrain
622 drivers the sync signals must always be active high.
624 config VIDEO_VGA_EXTERNAL_DAC_EN
625 string "LCD panel power enable pin"
626 depends on VIDEO_VGA_VIA_LCD
629 Set the enable pin for the external VGA DAC. This takes a string in the
630 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
632 config VIDEO_COMPOSITE
633 bool "Composite video output support"
634 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
637 Say Y here to add support for outputting composite video.
639 config VIDEO_LCD_MODE
640 string "LCD panel timing details"
644 LCD panel timing details string, leave empty if there is no LCD panel.
645 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
646 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
647 Also see: http://linux-sunxi.org/LCD
649 config VIDEO_LCD_DCLK_PHASE
650 int "LCD panel display clock phase"
654 Select LCD panel display clock phase shift, range 0-3.
656 config VIDEO_LCD_POWER
657 string "LCD panel power enable pin"
661 Set the power enable pin for the LCD panel. This takes a string in the
662 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
664 config VIDEO_LCD_RESET
665 string "LCD panel reset pin"
669 Set the reset pin for the LCD panel. This takes a string in the format
670 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
672 config VIDEO_LCD_BL_EN
673 string "LCD panel backlight enable pin"
677 Set the backlight enable pin for the LCD panel. This takes a string in the
678 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
681 config VIDEO_LCD_BL_PWM
682 string "LCD panel backlight pwm pin"
686 Set the backlight pwm pin for the LCD panel. This takes a string in the
687 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
689 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
690 bool "LCD panel backlight pwm is inverted"
694 Set this if the backlight pwm output is active low.
696 config VIDEO_LCD_PANEL_I2C
697 bool "LCD panel needs to be configured via i2c"
702 Say y here if the LCD panel needs to be configured via i2c. This
703 will add a bitbang i2c controller using gpios to talk to the LCD.
705 config VIDEO_LCD_PANEL_I2C_SDA
706 string "LCD panel i2c interface SDA pin"
707 depends on VIDEO_LCD_PANEL_I2C
710 Set the SDA pin for the LCD i2c interface. This takes a string in the
711 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
713 config VIDEO_LCD_PANEL_I2C_SCL
714 string "LCD panel i2c interface SCL pin"
715 depends on VIDEO_LCD_PANEL_I2C
718 Set the SCL pin for the LCD i2c interface. This takes a string in the
719 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
722 # Note only one of these may be selected at a time! But hidden choices are
723 # not supported by Kconfig
724 config VIDEO_LCD_IF_PARALLEL
727 config VIDEO_LCD_IF_LVDS
735 bool "Display Engine 2 video driver"
741 Say y here if you want to build DE2 video driver which is present on
742 newer SoCs. Currently only HDMI output is supported.
746 prompt "LCD panel support"
749 Select which type of LCD panel to support.
751 config VIDEO_LCD_PANEL_PARALLEL
752 bool "Generic parallel interface LCD panel"
753 select VIDEO_LCD_IF_PARALLEL
755 config VIDEO_LCD_PANEL_LVDS
756 bool "Generic lvds interface LCD panel"
757 select VIDEO_LCD_IF_LVDS
759 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
760 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
761 select VIDEO_LCD_SSD2828
762 select VIDEO_LCD_IF_PARALLEL
764 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
766 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
767 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
768 select VIDEO_LCD_ANX9804
769 select VIDEO_LCD_IF_PARALLEL
770 select VIDEO_LCD_PANEL_I2C
772 Select this for eDP LCD panels with 4 lanes running at 1.62G,
773 connected via an ANX9804 bridge chip.
775 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
776 bool "Hitachi tx18d42vm LCD panel"
777 select VIDEO_LCD_HITACHI_TX18D42VM
778 select VIDEO_LCD_IF_LVDS
780 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
782 config VIDEO_LCD_TL059WV5C0
783 bool "tl059wv5c0 LCD panel"
784 select VIDEO_LCD_PANEL_I2C
785 select VIDEO_LCD_IF_PARALLEL
787 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
788 Aigo M60/M608/M606 tablets.
793 string "SATA power pin"
796 Set the pins used to power the SATA. This takes a string in the
797 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
801 int "GMAC Transmit Clock Delay Chain"
804 Set the GMAC Transmit Clock Delay Chain value.
806 config SPL_STACK_R_ADDR
807 default 0x4fe00000 if MACH_SUN4I
808 default 0x4fe00000 if MACH_SUN5I
809 default 0x4fe00000 if MACH_SUN6I
810 default 0x4fe00000 if MACH_SUN7I
811 default 0x4fe00000 if MACH_SUN8I
812 default 0x2fe00000 if MACH_SUN9I
813 default 0x4fe00000 if MACH_SUN50I