4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun9i platforms,
34 bool "Allwinner sun6i internal P2WI controller"
36 If you say yes to this option, support will be included for the
37 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
39 The P2WI looks like an SMBus controller (which supports only byte
40 accesses), except that it only supports one slave device.
41 This interface is used to connect to specific PMIC devices (like the
47 Support for the PRCM (Power/Reset/Clock Management) unit available
51 bool "Sunxi AXP PMIC bus access helpers"
53 Select this PMIC bus access helpers for Sunxi platform PRCM or other
54 AXP family PMIC devices.
57 bool "Allwinner sunXi Reduced Serial Bus Driver"
59 Say y here to enable support for Allwinner's Reduced Serial Bus
60 (RSB) support. This controller is responsible for communicating
61 with various RSB based devices, such as AXP223, AXP8XX PMICs,
64 config SUNXI_HIGH_SRAM
68 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
69 with the first SRAM region being located at address 0.
70 Some newer SoCs map the boot ROM at address 0 instead and move the
71 SRAM to 64KB, just behind the mask ROM.
72 Chips using the latter setup are supposed to select this option to
73 adjust the addresses accordingly.
75 # Note only one of these may be selected at a time! But hidden choices are
76 # not supported by Kconfig
77 config SUNXI_GEN_SUN4I
80 Select this for sunxi SoCs which have resets and clocks set up
81 as the original A10 (mach-sun4i).
83 config SUNXI_GEN_SUN6I
86 Select this for sunxi SoCs which have sun6i like periphery, like
87 separate ahb reset control registers, custom pmic bus, new style
93 Select this for sunxi SoCs which uses a DRAM controller like the
94 DesignWare controller used in H3, mainly SoCs after H3, which do
95 not have official open-source DRAM initialization code, but can
96 use modified H3 DRAM initialization code.
99 config SUNXI_DRAM_DW_16BIT
102 Select this for sunxi SoCs with DesignWare DRAM controller and
103 have only 16-bit memory buswidth.
105 config SUNXI_DRAM_DW_32BIT
108 Select this for sunxi SoCs with DesignWare DRAM controller with
109 32-bit memory buswidth.
112 config MACH_SUNXI_H3_H5
117 select SUNXI_DRAM_DW_32BIT
118 select SUNXI_GEN_SUN6I
122 prompt "Sunxi SoC Variant"
126 bool "sun4i (Allwinner A10)"
128 select ARM_CORTEX_CPU_IS_UP
130 select SUNXI_GEN_SUN4I
134 bool "sun5i (Allwinner A13)"
136 select ARM_CORTEX_CPU_IS_UP
138 select SUNXI_GEN_SUN4I
140 imply CONS_INDEX_2 if !DM_SERIAL
143 bool "sun6i (Allwinner A31)"
145 select CPU_V7_HAS_NONSEC
146 select CPU_V7_HAS_VIRT
147 select ARCH_SUPPORT_PSCI
151 select SUNXI_GEN_SUN6I
153 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
156 bool "sun7i (Allwinner A20)"
158 select CPU_V7_HAS_NONSEC
159 select CPU_V7_HAS_VIRT
160 select ARCH_SUPPORT_PSCI
162 select SUNXI_GEN_SUN4I
164 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
166 config MACH_SUN8I_A23
167 bool "sun8i (Allwinner A23)"
169 select CPU_V7_HAS_NONSEC
170 select CPU_V7_HAS_VIRT
171 select ARCH_SUPPORT_PSCI
172 select DRAM_SUN8I_A23
173 select SUNXI_GEN_SUN6I
175 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
176 imply CONS_INDEX_5 if !DM_SERIAL
178 config MACH_SUN8I_A33
179 bool "sun8i (Allwinner A33)"
181 select CPU_V7_HAS_NONSEC
182 select CPU_V7_HAS_VIRT
183 select ARCH_SUPPORT_PSCI
184 select SUNXI_GEN_SUN6I
186 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187 imply CONS_INDEX_5 if !DM_SERIAL
189 config MACH_SUN8I_A83T
190 bool "sun8i (Allwinner A83T)"
192 select SUNXI_GEN_SUN6I
193 select MMC_SUNXI_HAS_NEW_MODE
197 bool "sun8i (Allwinner H3)"
199 select CPU_V7_HAS_NONSEC
200 select CPU_V7_HAS_VIRT
201 select ARCH_SUPPORT_PSCI
202 select MACH_SUNXI_H3_H5
203 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
205 config MACH_SUN8I_R40
206 bool "sun8i (Allwinner R40)"
208 select CPU_V7_HAS_NONSEC
209 select CPU_V7_HAS_VIRT
210 select ARCH_SUPPORT_PSCI
211 select SUNXI_GEN_SUN6I
214 select SUNXI_DRAM_DW_32BIT
216 config MACH_SUN8I_V3S
217 bool "sun8i (Allwinner V3s)"
219 select CPU_V7_HAS_NONSEC
220 select CPU_V7_HAS_VIRT
221 select ARCH_SUPPORT_PSCI
222 select SUNXI_GEN_SUN6I
224 select SUNXI_DRAM_DW_16BIT
226 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
229 bool "sun9i (Allwinner A80)"
233 select SUNXI_HIGH_SRAM
234 select SUNXI_GEN_SUN6I
239 bool "sun50i (Allwinner A64)"
243 select SUNXI_GEN_SUN6I
244 select SUNXI_HIGH_SRAM
247 select SUNXI_DRAM_DW_32BIT
251 config MACH_SUN50I_H5
252 bool "sun50i (Allwinner H5)"
254 select MACH_SUNXI_H3_H5
255 select SUNXI_HIGH_SRAM
261 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
266 default y if MACH_SUN8I_A23
267 default y if MACH_SUN8I_A33
268 default y if MACH_SUN8I_A83T
269 default y if MACH_SUNXI_H3_H5
270 default y if MACH_SUN8I_R40
271 default y if MACH_SUN8I_V3S
273 config RESERVE_ALLWINNER_BOOT0_HEADER
274 bool "reserve space for Allwinner boot0 header"
275 select ENABLE_ARM_SOC_BOOT0_HOOK
277 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
278 filled with magic values post build. The Allwinner provided boot0
279 blob relies on this information to load and execute U-Boot.
280 Only needed on 64-bit Allwinner boards so far when using boot0.
282 config ARM_BOOT_HOOK_RMR
286 select ENABLE_ARM_SOC_BOOT0_HOOK
288 Insert some ARM32 code at the very beginning of the U-Boot binary
289 which uses an RMR register write to bring the core into AArch64 mode.
290 The very first instruction acts as a switch, since it's carefully
291 chosen to be a NOP in one mode and a branch in the other, so the
292 code would only be executed if not already in AArch64.
293 This allows both the SPL and the U-Boot proper to be entered in
294 either mode and switch to AArch64 if needed.
297 config SUNXI_DRAM_DDR3
300 config SUNXI_DRAM_DDR2
303 config SUNXI_DRAM_LPDDR3
307 prompt "DRAM Type and Timing"
308 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
309 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
311 config SUNXI_DRAM_DDR3_1333
313 select SUNXI_DRAM_DDR3
314 depends on !MACH_SUN8I_V3S
316 This option is the original only supported memory type, which suits
317 many H3/H5/A64 boards available now.
319 config SUNXI_DRAM_LPDDR3_STOCK
320 bool "LPDDR3 with Allwinner stock configuration"
321 select SUNXI_DRAM_LPDDR3
323 This option is the LPDDR3 timing used by the stock boot0 by
326 config SUNXI_DRAM_DDR2_V3S
327 bool "DDR2 found in V3s chip"
328 select SUNXI_DRAM_DDR2
329 depends on MACH_SUN8I_V3S
331 This option is only for the DDR2 memory chip which is co-packaged in
338 int "sunxi dram type"
339 depends on MACH_SUN8I_A83T
342 Set the dram type, 3: DDR3, 7: LPDDR3
345 int "sunxi dram clock speed"
346 default 792 if MACH_SUN9I
347 default 648 if MACH_SUN8I_R40
348 default 312 if MACH_SUN6I || MACH_SUN8I
349 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
351 default 672 if MACH_SUN50I
353 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
354 must be a multiple of 24. For the sun9i (A80), the tested values
355 (for DDR3-1600) are 312 to 792.
357 if MACH_SUN5I || MACH_SUN7I
359 int "sunxi mbus clock speed"
362 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
367 int "sunxi dram zq value"
368 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
369 default 127 if MACH_SUN7I
370 default 14779 if MACH_SUN8I_V3S
371 default 3881979 if MACH_SUN8I_R40
372 default 4145117 if MACH_SUN9I
373 default 3881915 if MACH_SUN50I
375 Set the dram zq value.
378 bool "sunxi dram odt enable"
379 default n if !MACH_SUN8I_A23
380 default y if MACH_SUN8I_A23
381 default y if MACH_SUN8I_R40
382 default y if MACH_SUN50I
384 Select this to enable dram odt (on die termination).
386 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
388 int "sunxi dram emr1 value"
389 default 0 if MACH_SUN4I
390 default 4 if MACH_SUN5I || MACH_SUN7I
392 Set the dram controller emr1 value.
395 hex "sunxi dram tpr3 value"
398 Set the dram controller tpr3 parameter. This parameter configures
399 the delay on the command lane and also phase shifts, which are
400 applied for sampling incoming read data. The default value 0
401 means that no phase/delay adjustments are necessary. Properly
402 configuring this parameter increases reliability at high DRAM
405 config DRAM_DQS_GATING_DELAY
406 hex "sunxi dram dqs_gating_delay value"
409 Set the dram controller dqs_gating_delay parmeter. Each byte
410 encodes the DQS gating delay for each byte lane. The delay
411 granularity is 1/4 cycle. For example, the value 0x05060606
412 means that the delay is 5 quarter-cycles for one lane (1.25
413 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
414 The default value 0 means autodetection. The results of hardware
415 autodetection are not very reliable and depend on the chip
416 temperature (sometimes producing different results on cold start
417 and warm reboot). But the accuracy of hardware autodetection
418 is usually good enough, unless running at really high DRAM
419 clocks speeds (up to 600MHz). If unsure, keep as 0.
422 prompt "sunxi dram timings"
423 default DRAM_TIMINGS_VENDOR_MAGIC
425 Select the timings of the DDR3 chips.
427 config DRAM_TIMINGS_VENDOR_MAGIC
428 bool "Magic vendor timings from Android"
430 The same DRAM timings as in the Allwinner boot0 bootloader.
432 config DRAM_TIMINGS_DDR3_1066F_1333H
433 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
435 Use the timings of the standard JEDEC DDR3-1066F speed bin for
436 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
437 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
438 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
439 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
440 that down binning to DDR3-1066F is supported (because DDR3-1066F
441 uses a bit faster timings than DDR3-1333H).
443 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
444 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
446 Use the timings of the slowest possible JEDEC speed bin for the
447 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
448 DDR3-800E, DDR3-1066G or DDR3-1333J.
455 config DRAM_ODT_CORRECTION
456 int "sunxi dram odt correction value"
459 Set the dram odt correction value (range -255 - 255). In allwinner
460 fex files, this option is found in bits 8-15 of the u32 odt_en variable
461 in the [dram] section. When bit 31 of the odt_en variable is set
462 then the correction is negative. Usually the value for this is 0.
466 default 1008000000 if MACH_SUN4I
467 default 1008000000 if MACH_SUN5I
468 default 1008000000 if MACH_SUN6I
469 default 912000000 if MACH_SUN7I
470 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
471 default 1008000000 if MACH_SUN8I
472 default 1008000000 if MACH_SUN9I
474 config SYS_CONFIG_NAME
475 default "sun4i" if MACH_SUN4I
476 default "sun5i" if MACH_SUN5I
477 default "sun6i" if MACH_SUN6I
478 default "sun7i" if MACH_SUN7I
479 default "sun8i" if MACH_SUN8I
480 default "sun9i" if MACH_SUN9I
481 default "sun50i" if MACH_SUN50I
490 bool "UART0 on MicroSD breakout board"
493 Repurpose the SD card slot for getting access to the UART0 serial
494 console. Primarily useful only for low level u-boot debugging on
495 tablets, where normal UART0 is difficult to access and requires
496 device disassembly and/or soldering. As the SD card can't be used
497 at the same time, the system can be only booted in the FEL mode.
498 Only enable this if you really know what you are doing.
500 config OLD_SUNXI_KERNEL_COMPAT
501 bool "Enable workarounds for booting old kernels"
504 Set this to enable various workarounds for old kernels, this results in
505 sub-optimal settings for newer kernels, only enable if needed.
508 string "MAC power pin"
511 Set the pin used to power the MAC. This takes a string in the format
512 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
515 string "Card detect pin for mmc0"
516 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
519 Set the card detect pin for mmc0, leave empty to not use cd. This
520 takes a string in the format understood by sunxi_name_to_gpio, e.g.
521 PH1 for pin 1 of port H.
524 string "Card detect pin for mmc1"
527 See MMC0_CD_PIN help text.
530 string "Card detect pin for mmc2"
533 See MMC0_CD_PIN help text.
536 string "Card detect pin for mmc3"
539 See MMC0_CD_PIN help text.
542 string "Pins for mmc1"
545 Set the pins used for mmc1, when applicable. This takes a string in the
546 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
549 string "Pins for mmc2"
552 See MMC1_PINS help text.
555 string "Pins for mmc3"
558 See MMC1_PINS help text.
560 config MMC_SUNXI_SLOT_EXTRA
561 int "mmc extra slot number"
564 sunxi builds always enable mmc0, some boards also have a second sdcard
565 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
568 config INITIAL_USB_SCAN_DELAY
569 int "delay initial usb scan by x ms to allow builtin devices to init"
572 Some boards have on board usb devices which need longer than the
573 USB spec's 1 second to connect from board powerup. Set this config
574 option to a non 0 value to add an extra delay before the first usb
578 string "Vbus enable pin for usb0 (otg)"
581 Set the Vbus enable pin for usb0 (otg). This takes a string in the
582 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
585 string "Vbus detect pin for usb0 (otg)"
588 Set the Vbus detect pin for usb0 (otg). This takes a string in the
589 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
592 string "ID detect pin for usb0 (otg)"
595 Set the ID detect pin for usb0 (otg). This takes a string in the
596 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
599 string "Vbus enable pin for usb1 (ehci0)"
600 default "PH6" if MACH_SUN4I || MACH_SUN7I
601 default "PH27" if MACH_SUN6I
603 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
604 a string in the format understood by sunxi_name_to_gpio, e.g.
605 PH1 for pin 1 of port H.
608 string "Vbus enable pin for usb2 (ehci1)"
609 default "PH3" if MACH_SUN4I || MACH_SUN7I
610 default "PH24" if MACH_SUN6I
612 See USB1_VBUS_PIN help text.
615 string "Vbus enable pin for usb3 (ehci2)"
618 See USB1_VBUS_PIN help text.
621 bool "Enable I2C/TWI controller 0"
622 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
623 default n if MACH_SUN6I || MACH_SUN8I
626 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
627 its clock and setting up the bus. This is especially useful on devices
628 with slaves connected to the bus or with pins exposed through e.g. an
629 expansion port/header.
632 bool "Enable I2C/TWI controller 1"
636 See I2C0_ENABLE help text.
639 bool "Enable I2C/TWI controller 2"
643 See I2C0_ENABLE help text.
645 if MACH_SUN6I || MACH_SUN7I
647 bool "Enable I2C/TWI controller 3"
651 See I2C0_ENABLE help text.
656 bool "Enable the PRCM I2C/TWI controller"
657 # This is used for the pmic on H3
658 default y if SY8106A_POWER
661 Set this to y to enable the I2C controller which is part of the PRCM.
666 bool "Enable I2C/TWI controller 4"
670 See I2C0_ENABLE help text.
674 bool "Enable support for gpio-s on axp PMICs"
677 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
680 bool "Enable graphical uboot console on HDMI, LCD or VGA"
681 depends on !MACH_SUN8I_A83T
682 depends on !MACH_SUNXI_H3_H5
683 depends on !MACH_SUN8I_R40
684 depends on !MACH_SUN8I_V3S
685 depends on !MACH_SUN9I
686 depends on !MACH_SUN50I
688 imply VIDEO_DT_SIMPLEFB
691 Say Y here to add support for using a cfb console on the HDMI, LCD
692 or VGA output found on most sunxi devices. See doc/README.video for
693 info on how to select the video output and mode.
696 bool "HDMI output support"
697 depends on VIDEO_SUNXI && !MACH_SUN8I
700 Say Y here to add support for outputting video over HDMI.
703 bool "VGA output support"
704 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
707 Say Y here to add support for outputting video over VGA.
709 config VIDEO_VGA_VIA_LCD
710 bool "VGA via LCD controller support"
711 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
714 Say Y here to add support for external DACs connected to the parallel
715 LCD interface driving a VGA connector, such as found on the
718 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
719 bool "Force sync active high for VGA via LCD controller support"
720 depends on VIDEO_VGA_VIA_LCD
723 Say Y here if you've a board which uses opendrain drivers for the vga
724 hsync and vsync signals. Opendrain drivers cannot generate steep enough
725 positive edges for a stable video output, so on boards with opendrain
726 drivers the sync signals must always be active high.
728 config VIDEO_VGA_EXTERNAL_DAC_EN
729 string "LCD panel power enable pin"
730 depends on VIDEO_VGA_VIA_LCD
733 Set the enable pin for the external VGA DAC. This takes a string in the
734 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
736 config VIDEO_COMPOSITE
737 bool "Composite video output support"
738 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
741 Say Y here to add support for outputting composite video.
743 config VIDEO_LCD_MODE
744 string "LCD panel timing details"
745 depends on VIDEO_SUNXI
748 LCD panel timing details string, leave empty if there is no LCD panel.
749 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
750 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
751 Also see: http://linux-sunxi.org/LCD
753 config VIDEO_LCD_DCLK_PHASE
754 int "LCD panel display clock phase"
755 depends on VIDEO_SUNXI || DM_VIDEO
758 Select LCD panel display clock phase shift, range 0-3.
760 config VIDEO_LCD_POWER
761 string "LCD panel power enable pin"
762 depends on VIDEO_SUNXI
765 Set the power enable pin for the LCD panel. This takes a string in the
766 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
768 config VIDEO_LCD_RESET
769 string "LCD panel reset pin"
770 depends on VIDEO_SUNXI
773 Set the reset pin for the LCD panel. This takes a string in the format
774 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
776 config VIDEO_LCD_BL_EN
777 string "LCD panel backlight enable pin"
778 depends on VIDEO_SUNXI
781 Set the backlight enable pin for the LCD panel. This takes a string in the
782 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
785 config VIDEO_LCD_BL_PWM
786 string "LCD panel backlight pwm pin"
787 depends on VIDEO_SUNXI
790 Set the backlight pwm pin for the LCD panel. This takes a string in the
791 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
793 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
794 bool "LCD panel backlight pwm is inverted"
795 depends on VIDEO_SUNXI
798 Set this if the backlight pwm output is active low.
800 config VIDEO_LCD_PANEL_I2C
801 bool "LCD panel needs to be configured via i2c"
802 depends on VIDEO_SUNXI
806 Say y here if the LCD panel needs to be configured via i2c. This
807 will add a bitbang i2c controller using gpios to talk to the LCD.
809 config VIDEO_LCD_PANEL_I2C_SDA
810 string "LCD panel i2c interface SDA pin"
811 depends on VIDEO_LCD_PANEL_I2C
814 Set the SDA pin for the LCD i2c interface. This takes a string in the
815 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
817 config VIDEO_LCD_PANEL_I2C_SCL
818 string "LCD panel i2c interface SCL pin"
819 depends on VIDEO_LCD_PANEL_I2C
822 Set the SCL pin for the LCD i2c interface. This takes a string in the
823 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
826 # Note only one of these may be selected at a time! But hidden choices are
827 # not supported by Kconfig
828 config VIDEO_LCD_IF_PARALLEL
831 config VIDEO_LCD_IF_LVDS
839 bool "Display Engine 2 video driver"
843 imply VIDEO_DT_SIMPLEFB
846 Say y here if you want to build DE2 video driver which is present on
847 newer SoCs. Currently only HDMI output is supported.
851 prompt "LCD panel support"
852 depends on VIDEO_SUNXI
854 Select which type of LCD panel to support.
856 config VIDEO_LCD_PANEL_PARALLEL
857 bool "Generic parallel interface LCD panel"
858 select VIDEO_LCD_IF_PARALLEL
860 config VIDEO_LCD_PANEL_LVDS
861 bool "Generic lvds interface LCD panel"
862 select VIDEO_LCD_IF_LVDS
864 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
865 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
866 select VIDEO_LCD_SSD2828
867 select VIDEO_LCD_IF_PARALLEL
869 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
871 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
872 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
873 select VIDEO_LCD_ANX9804
874 select VIDEO_LCD_IF_PARALLEL
875 select VIDEO_LCD_PANEL_I2C
877 Select this for eDP LCD panels with 4 lanes running at 1.62G,
878 connected via an ANX9804 bridge chip.
880 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
881 bool "Hitachi tx18d42vm LCD panel"
882 select VIDEO_LCD_HITACHI_TX18D42VM
883 select VIDEO_LCD_IF_LVDS
885 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
887 config VIDEO_LCD_TL059WV5C0
888 bool "tl059wv5c0 LCD panel"
889 select VIDEO_LCD_PANEL_I2C
890 select VIDEO_LCD_IF_PARALLEL
892 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
893 Aigo M60/M608/M606 tablets.
898 string "SATA power pin"
901 Set the pins used to power the SATA. This takes a string in the
902 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
906 int "GMAC Transmit Clock Delay Chain"
909 Set the GMAC Transmit Clock Delay Chain value.
911 config SPL_STACK_R_ADDR
912 default 0x4fe00000 if MACH_SUN4I
913 default 0x4fe00000 if MACH_SUN5I
914 default 0x4fe00000 if MACH_SUN6I
915 default 0x4fe00000 if MACH_SUN7I
916 default 0x4fe00000 if MACH_SUN8I
917 default 0x2fe00000 if MACH_SUN9I
918 default 0x4fe00000 if MACH_SUN50I
921 bool "Support for SPI Flash on Allwinner SoCs in SPL"
922 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
924 Enable support for SPI Flash. This option allows SPL to read from
925 sunxi SPI Flash. It uses the same method as the boot ROM, so does
926 not need any extra configuration.