4 default " Allwinner Technology"
9 Select this dram controller driver for Sun4/5/7i platforms,
15 Select this dram controller driver for Sun6i platforms,
21 Select this dram controller driver for Sun8i platforms,
27 Select this dram controller driver for Sun8i platforms,
30 config DRAM_SUN8I_A83T
33 Select this dram controller driver for Sun8i platforms,
39 Select this dram controller driver for Sun9i platforms,
45 Select this dram controller driver for some sun50i platforms,
48 config DRAM_SUN50I_H616
51 Select this dram controller driver for some sun50i platforms,
55 config DRAM_SUN50I_H616_DX_ODT
56 hex "H616 DRAM DX ODT parameter"
58 DX ODT value from vendor DRAM settings.
60 config DRAM_SUN50I_H616_DX_DRI
61 hex "H616 DRAM DX DRI parameter"
63 DX DRI value from vendor DRAM settings.
65 config DRAM_SUN50I_H616_CA_DRI
66 hex "H616 DRAM CA DRI parameter"
68 CA DRI value from vendor DRAM settings.
70 config DRAM_SUN50I_H616_ODT_EN
71 hex "H616 DRAM ODT EN parameter"
74 ODT EN value from vendor DRAM settings.
76 config DRAM_SUN50I_H616_TPR0
77 hex "H616 DRAM TPR0 parameter"
80 TPR0 value from vendor DRAM settings.
82 config DRAM_SUN50I_H616_TPR2
83 hex "H616 DRAM TPR2 parameter"
86 TPR2 value from vendor DRAM settings.
88 config DRAM_SUN50I_H616_TPR10
89 hex "H616 DRAM TPR10 parameter"
91 TPR10 value from vendor DRAM settings. It tells which features
92 should be configured, like write leveling, read calibration, etc.
94 config DRAM_SUN50I_H616_TPR11
95 hex "H616 DRAM TPR11 parameter"
98 TPR11 value from vendor DRAM settings.
100 config DRAM_SUN50I_H616_TPR12
101 hex "H616 DRAM TPR12 parameter"
104 TPR12 value from vendor DRAM settings.
110 Support for the PRCM (Power/Reset/Clock Management) unit available
115 select DM_PMIC if DM_I2C
116 select PMIC_AXP if DM_I2C
118 Select this PMIC bus access helpers for Sunxi platform PRCM or other
119 AXP family PMIC devices.
121 config SUNXI_SRAM_ADDRESS
123 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
124 default 0x20000 if SUN50I_GEN_H6
127 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
128 with the first SRAM region being located at address 0.
129 Some newer SoCs map the boot ROM at address 0 instead and move the
130 SRAM to a different address.
132 config SUNXI_RVBAR_ADDRESS
135 default 0x09010040 if SUN50I_GEN_H6
138 The read-only RVBAR system register holds the address of the first
139 instruction to execute after a reset. Allwinner cores provide a
140 writable MMIO backing store for this register, to allow to set the
141 entry point when switching to AArch64. This store is on different
142 addresses, depending on the SoC.
144 config SUNXI_RVBAR_ALTERNATIVE
147 default 0x08100040 if MACH_SUN50I_H616
148 default SUNXI_RVBAR_ADDRESS
150 The H616 die exists in at least two variants, with one having the
151 RVBAR registers at a different address. If the SoC variant ID
152 (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the
154 Set this alternative address to the same as the normal address
155 for all other SoCs, so the content of the SRAM_VER_REG becomes
156 irrelevant there, and we can use the same code.
158 config SUNXI_A64_TIMER_ERRATUM
161 # Note only one of these may be selected at a time! But hidden choices are
162 # not supported by Kconfig
163 config SUNXI_GEN_SUN4I
166 Select this for sunxi SoCs which have resets and clocks set up
167 as the original A10 (mach-sun4i).
169 config SUNXI_GEN_SUN6I
172 Select this for sunxi SoCs which have sun6i like periphery, like
173 separate ahb reset control registers, custom pmic bus, new style
180 select MMC_SUNXI_HAS_NEW_MODE
183 Select this for sunxi SoCs which have H6 like peripherals, clocks
189 Select this for sunxi SoCs which uses a DRAM controller like the
190 DesignWare controller used in H3, mainly SoCs after H3, which do
191 not have official open-source DRAM initialization code, but can
192 use modified H3 DRAM initialization code.
195 config SUNXI_DRAM_DW_16BIT
198 Select this for sunxi SoCs with DesignWare DRAM controller and
199 have only 16-bit memory buswidth.
201 config SUNXI_DRAM_DW_32BIT
204 Select this for sunxi SoCs with DesignWare DRAM controller with
205 32-bit memory buswidth.
208 config MACH_SUNXI_H3_H5
212 select SUNXI_DRAM_DW_32BIT
213 select SUNXI_GEN_SUN6I
216 # TODO: try out A80's 8GiB DRAM space
217 config SUNXI_DRAM_MAX_SIZE
219 default 0x100000000 if MACH_SUN50I_H616
220 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
224 prompt "Sunxi SoC Variant"
228 bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)"
230 select SUNXI_GEN_SUN6I
232 select SKIP_LOWLEVEL_INIT_ONLY
233 select SPL_SKIP_LOWLEVEL_INIT_ONLY
236 bool "sun4i (Allwinner A10)"
239 select SUNXI_GEN_SUN4I
241 imply SPL_SYS_I2C_LEGACY
245 bool "sun5i (Allwinner A13)"
248 select SUNXI_GEN_SUN4I
250 imply SPL_SYS_I2C_LEGACY
254 bool "sun6i (Allwinner A31)"
256 select CPU_V7_HAS_NONSEC
257 select CPU_V7_HAS_VIRT
258 select ARCH_SUPPORT_PSCI
259 select SPL_ARMV7_SET_CORTEX_SMPEN
263 select SUNXI_GEN_SUN6I
265 select SYS_I2C_SUN6I_P2WI
266 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
269 bool "sun7i (Allwinner A20)"
271 select CPU_V7_HAS_NONSEC
272 select CPU_V7_HAS_VIRT
273 select ARCH_SUPPORT_PSCI
274 select SPL_ARMV7_SET_CORTEX_SMPEN
276 select SUNXI_GEN_SUN4I
278 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
279 imply SPL_SYS_I2C_LEGACY
282 config MACH_SUN8I_A23
283 bool "sun8i (Allwinner A23)"
285 select CPU_V7_HAS_NONSEC
286 select CPU_V7_HAS_VIRT
287 select ARCH_SUPPORT_PSCI
288 select DRAM_SUN8I_A23
290 select SUNXI_GEN_SUN6I
292 select SYS_I2C_SUN8I_RSB
293 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
295 config MACH_SUN8I_A33
296 bool "sun8i (Allwinner A33)"
298 select CPU_V7_HAS_NONSEC
299 select CPU_V7_HAS_VIRT
300 select ARCH_SUPPORT_PSCI
301 select DRAM_SUN8I_A33
303 select SUNXI_GEN_SUN6I
305 select SYS_I2C_SUN8I_RSB
306 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
308 config MACH_SUN8I_A83T
309 bool "sun8i (Allwinner A83T)"
311 select DRAM_SUN8I_A83T
313 select SUNXI_GEN_SUN6I
314 select MMC_SUNXI_HAS_NEW_MODE
315 select MMC_SUNXI_HAS_MODE_SWITCH
317 select SYS_I2C_SUN8I_RSB
320 bool "sun8i (Allwinner H3)"
322 select CPU_V7_HAS_NONSEC
323 select CPU_V7_HAS_VIRT
324 select ARCH_SUPPORT_PSCI
325 select MACH_SUNXI_H3_H5
326 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
328 config MACH_SUN8I_R40
329 bool "sun8i (Allwinner R40)"
331 select CPU_V7_HAS_NONSEC
332 select CPU_V7_HAS_VIRT
333 select ARCH_SUPPORT_PSCI
334 select SUNXI_GEN_SUN6I
335 select MMC_SUNXI_HAS_NEW_MODE
338 select SUNXI_DRAM_DW_32BIT
339 imply SPL_SYS_I2C_LEGACY
341 config MACH_SUN8I_V3S
342 bool "sun8i (Allwinner V3/V3s/S3/S3L)"
344 select CPU_V7_HAS_NONSEC
345 select CPU_V7_HAS_VIRT
346 select ARCH_SUPPORT_PSCI
347 select SUNXI_GEN_SUN6I
349 select SUNXI_DRAM_DW_16BIT
351 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
354 bool "sun9i (Allwinner A80)"
356 select SPL_ARMV7_SET_CORTEX_SMPEN
360 select SUNXI_GEN_SUN6I
364 bool "sun50i (Allwinner A64)"
368 select SUNXI_GEN_SUN6I
369 select MMC_SUNXI_HAS_NEW_MODE
372 select SUNXI_DRAM_DW_32BIT
375 select SUNXI_A64_TIMER_ERRATUM
377 config MACH_SUN50I_H5
378 bool "sun50i (Allwinner H5)"
380 select MACH_SUNXI_H3_H5
381 select MMC_SUNXI_HAS_NEW_MODE
385 config MACH_SUN50I_H6
386 bool "sun50i (Allwinner H6)"
388 select DRAM_SUN50I_H6
391 config MACH_SUN50I_H616
392 bool "sun50i (Allwinner H616)"
394 select DRAM_SUN50I_H616
399 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
402 select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64
404 default y if MACH_SUN8I_A23
405 default y if MACH_SUN8I_A33
406 default y if MACH_SUN8I_A83T
407 default y if MACH_SUNXI_H3_H5
408 default y if MACH_SUN8I_R40
409 default y if MACH_SUN8I_V3S
411 config RESERVE_ALLWINNER_BOOT0_HEADER
412 bool "reserve space for Allwinner boot0 header"
413 select ENABLE_ARM_SOC_BOOT0_HOOK
415 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
416 filled with magic values post build. The Allwinner provided boot0
417 blob relies on this information to load and execute U-Boot.
418 Only needed on 64-bit Allwinner boards so far when using boot0.
420 config ARM_BOOT_HOOK_RMR
424 select ENABLE_ARM_SOC_BOOT0_HOOK
426 Insert some ARM32 code at the very beginning of the U-Boot binary
427 which uses an RMR register write to bring the core into AArch64 mode.
428 The very first instruction acts as a switch, since it's carefully
429 chosen to be a NOP in one mode and a branch in the other, so the
430 code would only be executed if not already in AArch64.
431 This allows both the SPL and the U-Boot proper to be entered in
432 either mode and switch to AArch64 if needed.
434 if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616
435 config SUNXI_DRAM_DDR3
438 config SUNXI_DRAM_DDR2
441 config SUNXI_DRAM_LPDDR3
445 prompt "DRAM Type and Timing"
446 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
447 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
449 config SUNXI_DRAM_DDR3_1333
451 select SUNXI_DRAM_DDR3
453 This option is the original only supported memory type, which suits
454 many H3/H5/A64 boards available now.
456 config SUNXI_DRAM_LPDDR3_STOCK
457 bool "LPDDR3 with Allwinner stock configuration"
458 select SUNXI_DRAM_LPDDR3
460 This option is the LPDDR3 timing used by the stock boot0 by
463 config SUNXI_DRAM_H6_LPDDR3
464 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
465 select SUNXI_DRAM_LPDDR3
466 depends on DRAM_SUN50I_H6
468 This option is the LPDDR3 timing used by the stock boot0 by
471 config SUNXI_DRAM_H6_DDR3_1333
472 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
473 select SUNXI_DRAM_DDR3
474 depends on DRAM_SUN50I_H6
476 This option is the DDR3 timing used by the boot0 on H6 TV boxes
477 which use a DDR3-1333 timing.
479 config SUNXI_DRAM_H616_LPDDR3
480 bool "LPDDR3 DRAM chips on the H616 DRAM controller"
481 select SUNXI_DRAM_LPDDR3
482 depends on DRAM_SUN50I_H616
484 This option is the LPDDR3 timing used by the stock boot0 by
487 config SUNXI_DRAM_H616_DDR3_1333
488 bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
489 select SUNXI_DRAM_DDR3
490 depends on DRAM_SUN50I_H616
492 This option is the DDR3 timing used by the boot0 on H616 TV boxes
493 which use a DDR3-1333 timing.
495 config SUNXI_DRAM_DDR2_V3S
496 bool "DDR2 found in V3s chip"
497 select SUNXI_DRAM_DDR2
498 depends on MACH_SUN8I_V3S
500 This option is only for the DDR2 memory chip which is co-packaged in
507 int "sunxi dram type"
508 depends on MACH_SUN8I_A83T
511 Set the dram type, 3: DDR3, 7: LPDDR3
514 int "sunxi dram clock speed"
515 default 792 if MACH_SUN9I
516 default 648 if MACH_SUN8I_R40
517 default 312 if MACH_SUN6I || MACH_SUN8I
518 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
520 default 672 if MACH_SUN50I
521 default 744 if MACH_SUN50I_H6
522 default 720 if MACH_SUN50I_H616
524 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
525 must be a multiple of 24. For the sun9i (A80), the tested values
526 (for DDR3-1600) are 312 to 792.
528 if MACH_SUN5I || MACH_SUN7I
530 int "sunxi mbus clock speed"
533 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
538 int "sunxi dram zq value"
539 depends on !MACH_SUN50I_H616
540 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
541 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
542 default 127 if MACH_SUN7I
543 default 14779 if MACH_SUN8I_V3S
544 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
545 default 4145117 if MACH_SUN9I
546 default 3881915 if MACH_SUN50I
548 Set the dram zq value.
551 bool "sunxi dram odt enable"
552 depends on !MACH_SUN50I_H616
553 default y if MACH_SUN8I_A23
554 default y if MACH_SUNXI_H3_H5
555 default y if MACH_SUN8I_R40
556 default y if MACH_SUN50I
557 default y if MACH_SUN50I_H6
559 Select this to enable dram odt (on die termination).
561 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
563 int "sunxi dram emr1 value"
564 default 0 if MACH_SUN4I
565 default 4 if MACH_SUN5I || MACH_SUN7I
567 Set the dram controller emr1 value.
570 hex "sunxi dram tpr3 value"
573 Set the dram controller tpr3 parameter. This parameter configures
574 the delay on the command lane and also phase shifts, which are
575 applied for sampling incoming read data. The default value 0
576 means that no phase/delay adjustments are necessary. Properly
577 configuring this parameter increases reliability at high DRAM
580 config DRAM_DQS_GATING_DELAY
581 hex "sunxi dram dqs_gating_delay value"
584 Set the dram controller dqs_gating_delay parmeter. Each byte
585 encodes the DQS gating delay for each byte lane. The delay
586 granularity is 1/4 cycle. For example, the value 0x05060606
587 means that the delay is 5 quarter-cycles for one lane (1.25
588 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
589 The default value 0 means autodetection. The results of hardware
590 autodetection are not very reliable and depend on the chip
591 temperature (sometimes producing different results on cold start
592 and warm reboot). But the accuracy of hardware autodetection
593 is usually good enough, unless running at really high DRAM
594 clocks speeds (up to 600MHz). If unsure, keep as 0.
597 prompt "sunxi dram timings"
598 default DRAM_TIMINGS_VENDOR_MAGIC
600 Select the timings of the DDR3 chips.
602 config DRAM_TIMINGS_VENDOR_MAGIC
603 bool "Magic vendor timings from Android"
605 The same DRAM timings as in the Allwinner boot0 bootloader.
607 config DRAM_TIMINGS_DDR3_1066F_1333H
608 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
610 Use the timings of the standard JEDEC DDR3-1066F speed bin for
611 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
612 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
613 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
614 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
615 that down binning to DDR3-1066F is supported (because DDR3-1066F
616 uses a bit faster timings than DDR3-1333H).
618 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
619 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
621 Use the timings of the slowest possible JEDEC speed bin for the
622 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
623 DDR3-800E, DDR3-1066G or DDR3-1333J.
630 config DRAM_ODT_CORRECTION
631 int "sunxi dram odt correction value"
634 Set the dram odt correction value (range -255 - 255). In allwinner
635 fex files, this option is found in bits 8-15 of the u32 odt_en variable
636 in the [dram] section. When bit 31 of the odt_en variable is set
637 then the correction is negative. Usually the value for this is 0.
641 default 408000000 if MACH_SUNIV
642 default 1008000000 if MACH_SUN4I
643 default 1008000000 if MACH_SUN5I
644 default 1008000000 if MACH_SUN6I
645 default 912000000 if MACH_SUN7I
646 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
647 default 1008000000 if MACH_SUN8I
648 default 1008000000 if MACH_SUN9I
649 default 888000000 if MACH_SUN50I_H6
650 default 1008000000 if MACH_SUN50I_H616
652 config SYS_CONFIG_NAME
653 default "suniv" if MACH_SUNIV
654 default "sun4i" if MACH_SUN4I
655 default "sun5i" if MACH_SUN5I
656 default "sun6i" if MACH_SUN6I
657 default "sun7i" if MACH_SUN7I
658 default "sun8i" if MACH_SUN8I
659 default "sun9i" if MACH_SUN9I
660 default "sun50i" if MACH_SUN50I
661 default "sun50i" if MACH_SUN50I_H6
662 default "sun50i" if MACH_SUN50I_H616
670 config SUNXI_MINIMUM_DRAM_MB
671 int "minimum DRAM size"
672 default 32 if MACH_SUNIV
673 default 64 if MACH_SUN8I_V3S
676 Minimum DRAM size expected on the board. Traditionally we assumed
677 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM
678 we have smaller sizes, though, so that U-Boot's own load address and
679 the default payload addresses must be shifted down.
680 This is expected to be fixed by the SoC selection.
683 bool "UART0 on MicroSD breakout board"
685 Repurpose the SD card slot for getting access to the UART0 serial
686 console. Primarily useful only for low level u-boot debugging on
687 tablets, where normal UART0 is difficult to access and requires
688 device disassembly and/or soldering. As the SD card can't be used
689 at the same time, the system can be only booted in the FEL mode.
690 Only enable this if you really know what you are doing.
692 config OLD_SUNXI_KERNEL_COMPAT
693 bool "Enable workarounds for booting old kernels"
695 Set this to enable various workarounds for old kernels, this results in
696 sub-optimal settings for newer kernels, only enable if needed.
699 string "MAC power pin"
702 Set the pin used to power the MAC. This takes a string in the format
703 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
706 bool "Pins for mmc1 are on Port H"
707 depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
709 Select this option for boards where mmc1 uses the Port H pinmux.
711 config MMC_SUNXI_SLOT_EXTRA
712 int "mmc extra slot number"
715 sunxi builds always enable mmc0, some boards also have a second sdcard
716 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
720 string "Vbus enable pin for usb0 (otg)"
723 Set the Vbus enable pin for usb0 (otg). This takes a string in the
724 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
727 string "Vbus detect pin for usb0 (otg)"
730 Set the Vbus detect pin for usb0 (otg). This takes a string in the
731 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
734 string "ID detect pin for usb0 (otg)"
737 Set the ID detect pin for usb0 (otg). This takes a string in the
738 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
741 string "Vbus enable pin for usb1 (ehci0)"
742 default "PH6" if MACH_SUN4I || MACH_SUN7I
743 default "PH27" if MACH_SUN6I
745 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
746 a string in the format understood by sunxi_name_to_gpio, e.g.
747 PH1 for pin 1 of port H.
750 string "Vbus enable pin for usb2 (ehci1)"
751 default "PH3" if MACH_SUN4I || MACH_SUN7I
752 default "PH24" if MACH_SUN6I
754 See USB1_VBUS_PIN help text.
757 string "Vbus enable pin for usb3 (ehci2)"
760 See USB1_VBUS_PIN help text.
763 bool "Enable I2C/TWI controller 0"
764 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
765 default n if MACH_SUN6I || MACH_SUN8I
768 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
769 its clock and setting up the bus. This is especially useful on devices
770 with slaves connected to the bus or with pins exposed through e.g. an
771 expansion port/header.
774 bool "Enable I2C/TWI controller 1"
777 See I2C0_ENABLE help text.
779 if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
781 bool "Enable the PRCM I2C/TWI controller"
782 # This is used for the pmic on H3
783 default y if SY8106A_POWER
786 Set this to y to enable the I2C controller which is part of the PRCM.
790 bool "Enable support for gpio-s on axp PMICs"
791 depends on AXP_PMIC_BUS
793 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
795 config AXP_DISABLE_BOOT_ON_POWERON
796 bool "Disable device boot on power plug-in"
797 depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
800 Say Y here to prevent the device from booting up because of a plug-in
801 event. When set, the device will boot into the SPL briefly to
802 determine why it was powered on, and if it was determined because of
803 a plug-in event instead of a button press event it will shut back off.
806 bool "Enable graphical uboot console on HDMI, LCD or VGA"
807 depends on !MACH_SUN8I_A83T
808 depends on !MACH_SUNXI_H3_H5
809 depends on !MACH_SUN8I_R40
810 depends on !MACH_SUN8I_V3S
811 depends on !MACH_SUN9I
812 depends on !MACH_SUN50I
813 depends on !SUN50I_GEN_H6
816 imply VIDEO_DT_SIMPLEFB
819 Say Y here to add support for using a graphical console on the HDMI,
820 LCD or VGA output found on older sunxi devices. This will also provide
821 a simple_framebuffer device for Linux.
824 bool "HDMI output support"
825 depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV
828 Say Y here to add support for outputting video over HDMI.
831 bool "VGA output support"
832 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
834 Say Y here to add support for outputting video over VGA.
836 config VIDEO_VGA_VIA_LCD
837 bool "VGA via LCD controller support"
838 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
840 Say Y here to add support for external DACs connected to the parallel
841 LCD interface driving a VGA connector, such as found on the
844 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
845 bool "Force sync active high for VGA via LCD controller support"
846 depends on VIDEO_VGA_VIA_LCD
848 Say Y here if you've a board which uses opendrain drivers for the vga
849 hsync and vsync signals. Opendrain drivers cannot generate steep enough
850 positive edges for a stable video output, so on boards with opendrain
851 drivers the sync signals must always be active high.
853 config VIDEO_VGA_EXTERNAL_DAC_EN
854 string "LCD panel power enable pin"
855 depends on VIDEO_VGA_VIA_LCD
858 Set the enable pin for the external VGA DAC. This takes a string in the
859 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
861 config VIDEO_COMPOSITE
862 bool "Composite video output support"
863 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
865 Say Y here to add support for outputting composite video.
867 config VIDEO_LCD_MODE
868 string "LCD panel timing details"
869 depends on VIDEO_SUNXI
872 LCD panel timing details string, leave empty if there is no LCD panel.
873 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
874 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
875 Also see: http://linux-sunxi.org/LCD
877 config VIDEO_LCD_DCLK_PHASE
878 int "LCD panel display clock phase"
879 depends on VIDEO_SUNXI || VIDEO
883 Select LCD panel display clock phase shift
885 config VIDEO_LCD_POWER
886 string "LCD panel power enable pin"
887 depends on VIDEO_SUNXI
890 Set the power enable pin for the LCD panel. This takes a string in the
891 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
893 config VIDEO_LCD_RESET
894 string "LCD panel reset pin"
895 depends on VIDEO_SUNXI
898 Set the reset pin for the LCD panel. This takes a string in the format
899 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
901 config VIDEO_LCD_BL_EN
902 string "LCD panel backlight enable pin"
903 depends on VIDEO_SUNXI
906 Set the backlight enable pin for the LCD panel. This takes a string in the
907 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
910 config VIDEO_LCD_BL_PWM
911 string "LCD panel backlight pwm pin"
912 depends on VIDEO_SUNXI
915 Set the backlight pwm pin for the LCD panel. This takes a string in the
916 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
918 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
919 bool "LCD panel backlight pwm is inverted"
920 depends on VIDEO_SUNXI
923 Set this if the backlight pwm output is active low.
925 config VIDEO_LCD_PANEL_I2C
926 bool "LCD panel needs to be configured via i2c"
927 depends on VIDEO_SUNXI
930 Say y here if the LCD panel needs to be configured via i2c. This
931 will add a bitbang i2c controller using gpios to talk to the LCD.
933 config VIDEO_LCD_PANEL_I2C_NAME
934 string "LCD panel i2c interface node name"
935 depends on VIDEO_LCD_PANEL_I2C
938 Set the device tree node name for the LCD i2c interface.
940 # Note only one of these may be selected at a time! But hidden choices are
941 # not supported by Kconfig
942 config VIDEO_LCD_IF_PARALLEL
945 config VIDEO_LCD_IF_LVDS
952 bool "Display Engine 2 video driver"
957 imply VIDEO_DT_SIMPLEFB
960 Say y here if you want to build DE2 video driver which is present on
961 newer SoCs. Currently only HDMI output is supported.
965 prompt "LCD panel support"
966 depends on VIDEO_SUNXI
968 Select which type of LCD panel to support.
970 config VIDEO_LCD_PANEL_PARALLEL
971 bool "Generic parallel interface LCD panel"
972 select VIDEO_LCD_IF_PARALLEL
974 config VIDEO_LCD_PANEL_LVDS
975 bool "Generic lvds interface LCD panel"
976 select VIDEO_LCD_IF_LVDS
978 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
979 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
980 select VIDEO_LCD_SSD2828
981 select VIDEO_LCD_IF_PARALLEL
983 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
985 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
986 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
987 select VIDEO_LCD_ANX9804
988 select VIDEO_LCD_IF_PARALLEL
989 select VIDEO_LCD_PANEL_I2C
991 Select this for eDP LCD panels with 4 lanes running at 1.62G,
992 connected via an ANX9804 bridge chip.
994 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
995 bool "Hitachi tx18d42vm LCD panel"
996 select VIDEO_LCD_HITACHI_TX18D42VM
997 select VIDEO_LCD_IF_LVDS
999 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
1001 config VIDEO_LCD_TL059WV5C0
1002 bool "tl059wv5c0 LCD panel"
1003 select VIDEO_LCD_PANEL_I2C
1004 select VIDEO_LCD_IF_PARALLEL
1006 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
1007 Aigo M60/M608/M606 tablets.
1012 string "SATA power pin"
1015 Set the pins used to power the SATA. This takes a string in the
1016 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
1019 config GMAC_TX_DELAY
1020 int "GMAC Transmit Clock Delay Chain"
1023 Set the GMAC Transmit Clock Delay Chain value.
1025 config SPL_STACK_R_ADDR
1026 default 0x81e00000 if MACH_SUNIV
1027 default 0x4fe00000 if MACH_SUN4I
1028 default 0x4fe00000 if MACH_SUN5I
1029 default 0x4fe00000 if MACH_SUN6I
1030 default 0x4fe00000 if MACH_SUN7I
1031 default 0x4fe00000 if MACH_SUN8I
1032 default 0x2fe00000 if MACH_SUN9I
1033 default 0x4fe00000 if MACH_SUN50I
1034 default 0x4fe00000 if SUN50I_GEN_H6
1036 config SPL_SPI_SUNXI
1037 bool "Support for SPI Flash on Allwinner SoCs in SPL"
1038 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
1040 Enable support for SPI Flash. This option allows SPL to read from
1041 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1042 not need any extra configuration.
1044 config PINE64_DT_SELECTION
1045 bool "Enable Pine64 device tree selection code"
1046 depends on MACH_SUN50I
1048 The original Pine A64 and Pine A64+ are similar but different
1049 boards and can be differed by the DRAM size. Pine A64 has
1050 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1051 option, the device tree selection code specific to Pine64 which
1052 utilizes the DRAM size will be enabled.
1054 config PINEPHONE_DT_SELECTION
1055 bool "Enable PinePhone device tree selection code"
1056 depends on MACH_SUN50I
1058 Enable this option to automatically select the device tree for the
1059 correct PinePhone hardware revision during boot.
1061 config BLUETOOTH_DT_DEVICE_FIXUP
1062 string "Fixup the Bluetooth controller address"
1065 This option specifies the DT compatible name of the Bluetooth
1066 controller for which to set the "local-bd-address" property.
1067 Set this option if your device ships with the Bluetooth controller
1069 The used address is "bdaddr" if set, and "ethaddr" with the LSB
1072 source "board/sunxi/Kconfig"
1076 config CHIP_DIP_SCAN
1077 bool "Enable DIPs detection for CHIP board"
1078 select SUPPORT_EXTENSION_SCAN
1082 select W1_EEPROM_DS24XXX
1083 select CMD_EXTENSION