4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
158 select DM_SCSI if SCSI
161 select SUNXI_GEN_SUN4I
165 bool "sun5i (Allwinner A13)"
167 select ARM_CORTEX_CPU_IS_UP
171 select SUNXI_GEN_SUN4I
173 imply CONS_INDEX_2 if !DM_SERIAL
176 bool "sun6i (Allwinner A31)"
178 select CPU_V7_HAS_NONSEC
179 select CPU_V7_HAS_VIRT
180 select ARCH_SUPPORT_PSCI
186 select SUNXI_GEN_SUN6I
188 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
191 bool "sun7i (Allwinner A20)"
193 select CPU_V7_HAS_NONSEC
194 select CPU_V7_HAS_VIRT
195 select ARCH_SUPPORT_PSCI
198 select SUNXI_GEN_SUN4I
200 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
202 config MACH_SUN8I_A23
203 bool "sun8i (Allwinner A23)"
205 select CPU_V7_HAS_NONSEC
206 select CPU_V7_HAS_VIRT
207 select ARCH_SUPPORT_PSCI
209 select DRAM_SUN8I_A23
211 select SUNXI_GEN_SUN6I
213 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
214 imply CONS_INDEX_5 if !DM_SERIAL
216 config MACH_SUN8I_A33
217 bool "sun8i (Allwinner A33)"
219 select CPU_V7_HAS_NONSEC
220 select CPU_V7_HAS_VIRT
221 select ARCH_SUPPORT_PSCI
223 select DRAM_SUN8I_A33
225 select SUNXI_GEN_SUN6I
227 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
228 imply CONS_INDEX_5 if !DM_SERIAL
230 config MACH_SUN8I_A83T
231 bool "sun8i (Allwinner A83T)"
234 select DRAM_SUN8I_A83T
236 select SUNXI_GEN_SUN6I
237 select MMC_SUNXI_HAS_NEW_MODE
238 select MMC_SUNXI_HAS_MODE_SWITCH
242 bool "sun8i (Allwinner H3)"
244 select CPU_V7_HAS_NONSEC
245 select CPU_V7_HAS_VIRT
246 select ARCH_SUPPORT_PSCI
247 select MACH_SUNXI_H3_H5
248 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
251 config MACH_SUN8I_R40
252 bool "sun8i (Allwinner R40)"
254 select CPU_V7_HAS_NONSEC
255 select CPU_V7_HAS_VIRT
256 select ARCH_SUPPORT_PSCI
257 select SUNXI_GEN_SUN6I
260 select SUNXI_DRAM_DW_32BIT
262 config MACH_SUN8I_V3S
263 bool "sun8i (Allwinner V3s)"
265 select CPU_V7_HAS_NONSEC
266 select CPU_V7_HAS_VIRT
267 select ARCH_SUPPORT_PSCI
269 select SUNXI_GEN_SUN6I
271 select SUNXI_DRAM_DW_16BIT
273 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
276 bool "sun9i (Allwinner A80)"
280 select SUNXI_GEN_SUN6I
286 bool "sun50i (Allwinner A64)"
293 select SUNXI_GEN_SUN6I
294 select MMC_SUNXI_HAS_NEW_MODE
297 select SUNXI_DRAM_DW_32BIT
300 select SUNXI_A64_TIMER_ERRATUM
302 config MACH_SUN50I_H5
303 bool "sun50i (Allwinner H5)"
305 select MACH_SUNXI_H3_H5
310 config MACH_SUN50I_H6
311 bool "sun50i (Allwinner H6)"
317 select DRAM_SUN50I_H6
321 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
326 default y if MACH_SUN8I_A23
327 default y if MACH_SUN8I_A33
328 default y if MACH_SUN8I_A83T
329 default y if MACH_SUNXI_H3_H5
330 default y if MACH_SUN8I_R40
331 default y if MACH_SUN8I_V3S
333 config RESERVE_ALLWINNER_BOOT0_HEADER
334 bool "reserve space for Allwinner boot0 header"
335 select ENABLE_ARM_SOC_BOOT0_HOOK
337 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
338 filled with magic values post build. The Allwinner provided boot0
339 blob relies on this information to load and execute U-Boot.
340 Only needed on 64-bit Allwinner boards so far when using boot0.
342 config ARM_BOOT_HOOK_RMR
346 select ENABLE_ARM_SOC_BOOT0_HOOK
348 Insert some ARM32 code at the very beginning of the U-Boot binary
349 which uses an RMR register write to bring the core into AArch64 mode.
350 The very first instruction acts as a switch, since it's carefully
351 chosen to be a NOP in one mode and a branch in the other, so the
352 code would only be executed if not already in AArch64.
353 This allows both the SPL and the U-Boot proper to be entered in
354 either mode and switch to AArch64 if needed.
357 config SUNXI_DRAM_DDR3
360 config SUNXI_DRAM_DDR2
363 config SUNXI_DRAM_LPDDR3
367 prompt "DRAM Type and Timing"
368 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
369 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
371 config SUNXI_DRAM_DDR3_1333
373 select SUNXI_DRAM_DDR3
374 depends on !MACH_SUN8I_V3S
376 This option is the original only supported memory type, which suits
377 many H3/H5/A64 boards available now.
379 config SUNXI_DRAM_LPDDR3_STOCK
380 bool "LPDDR3 with Allwinner stock configuration"
381 select SUNXI_DRAM_LPDDR3
383 This option is the LPDDR3 timing used by the stock boot0 by
386 config SUNXI_DRAM_DDR2_V3S
387 bool "DDR2 found in V3s chip"
388 select SUNXI_DRAM_DDR2
389 depends on MACH_SUN8I_V3S
391 This option is only for the DDR2 memory chip which is co-packaged in
398 int "sunxi dram type"
399 depends on MACH_SUN8I_A83T
402 Set the dram type, 3: DDR3, 7: LPDDR3
405 int "sunxi dram clock speed"
406 default 792 if MACH_SUN9I
407 default 648 if MACH_SUN8I_R40
408 default 312 if MACH_SUN6I || MACH_SUN8I
409 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
411 default 672 if MACH_SUN50I
412 default 744 if MACH_SUN50I_H6
414 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
415 must be a multiple of 24. For the sun9i (A80), the tested values
416 (for DDR3-1600) are 312 to 792.
418 if MACH_SUN5I || MACH_SUN7I
420 int "sunxi mbus clock speed"
423 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
428 int "sunxi dram zq value"
429 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
430 default 127 if MACH_SUN7I
431 default 14779 if MACH_SUN8I_V3S
432 default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
433 default 4145117 if MACH_SUN9I
434 default 3881915 if MACH_SUN50I
436 Set the dram zq value.
439 bool "sunxi dram odt enable"
440 default y if MACH_SUN8I_A23
441 default y if MACH_SUN8I_R40
442 default y if MACH_SUN50I
443 default y if MACH_SUN50I_H6
445 Select this to enable dram odt (on die termination).
447 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
449 int "sunxi dram emr1 value"
450 default 0 if MACH_SUN4I
451 default 4 if MACH_SUN5I || MACH_SUN7I
453 Set the dram controller emr1 value.
456 hex "sunxi dram tpr3 value"
459 Set the dram controller tpr3 parameter. This parameter configures
460 the delay on the command lane and also phase shifts, which are
461 applied for sampling incoming read data. The default value 0
462 means that no phase/delay adjustments are necessary. Properly
463 configuring this parameter increases reliability at high DRAM
466 config DRAM_DQS_GATING_DELAY
467 hex "sunxi dram dqs_gating_delay value"
470 Set the dram controller dqs_gating_delay parmeter. Each byte
471 encodes the DQS gating delay for each byte lane. The delay
472 granularity is 1/4 cycle. For example, the value 0x05060606
473 means that the delay is 5 quarter-cycles for one lane (1.25
474 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
475 The default value 0 means autodetection. The results of hardware
476 autodetection are not very reliable and depend on the chip
477 temperature (sometimes producing different results on cold start
478 and warm reboot). But the accuracy of hardware autodetection
479 is usually good enough, unless running at really high DRAM
480 clocks speeds (up to 600MHz). If unsure, keep as 0.
483 prompt "sunxi dram timings"
484 default DRAM_TIMINGS_VENDOR_MAGIC
486 Select the timings of the DDR3 chips.
488 config DRAM_TIMINGS_VENDOR_MAGIC
489 bool "Magic vendor timings from Android"
491 The same DRAM timings as in the Allwinner boot0 bootloader.
493 config DRAM_TIMINGS_DDR3_1066F_1333H
494 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
496 Use the timings of the standard JEDEC DDR3-1066F speed bin for
497 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
498 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
499 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
500 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
501 that down binning to DDR3-1066F is supported (because DDR3-1066F
502 uses a bit faster timings than DDR3-1333H).
504 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
505 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
507 Use the timings of the slowest possible JEDEC speed bin for the
508 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
509 DDR3-800E, DDR3-1066G or DDR3-1333J.
516 config DRAM_ODT_CORRECTION
517 int "sunxi dram odt correction value"
520 Set the dram odt correction value (range -255 - 255). In allwinner
521 fex files, this option is found in bits 8-15 of the u32 odt_en variable
522 in the [dram] section. When bit 31 of the odt_en variable is set
523 then the correction is negative. Usually the value for this is 0.
527 default 1008000000 if MACH_SUN4I
528 default 1008000000 if MACH_SUN5I
529 default 1008000000 if MACH_SUN6I
530 default 912000000 if MACH_SUN7I
531 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
532 default 1008000000 if MACH_SUN8I
533 default 1008000000 if MACH_SUN9I
534 default 888000000 if MACH_SUN50I_H6
536 config SYS_CONFIG_NAME
537 default "sun4i" if MACH_SUN4I
538 default "sun5i" if MACH_SUN5I
539 default "sun6i" if MACH_SUN6I
540 default "sun7i" if MACH_SUN7I
541 default "sun8i" if MACH_SUN8I
542 default "sun9i" if MACH_SUN9I
543 default "sun50i" if MACH_SUN50I
544 default "sun50i" if MACH_SUN50I_H6
553 bool "UART0 on MicroSD breakout board"
556 Repurpose the SD card slot for getting access to the UART0 serial
557 console. Primarily useful only for low level u-boot debugging on
558 tablets, where normal UART0 is difficult to access and requires
559 device disassembly and/or soldering. As the SD card can't be used
560 at the same time, the system can be only booted in the FEL mode.
561 Only enable this if you really know what you are doing.
563 config OLD_SUNXI_KERNEL_COMPAT
564 bool "Enable workarounds for booting old kernels"
567 Set this to enable various workarounds for old kernels, this results in
568 sub-optimal settings for newer kernels, only enable if needed.
571 string "MAC power pin"
574 Set the pin used to power the MAC. This takes a string in the format
575 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
578 string "Card detect pin for mmc0"
579 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
582 Set the card detect pin for mmc0, leave empty to not use cd. This
583 takes a string in the format understood by sunxi_name_to_gpio, e.g.
584 PH1 for pin 1 of port H.
587 string "Card detect pin for mmc1"
590 See MMC0_CD_PIN help text.
593 string "Card detect pin for mmc2"
596 See MMC0_CD_PIN help text.
599 string "Card detect pin for mmc3"
602 See MMC0_CD_PIN help text.
605 string "Pins for mmc1"
608 Set the pins used for mmc1, when applicable. This takes a string in the
609 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
612 string "Pins for mmc2"
615 See MMC1_PINS help text.
618 string "Pins for mmc3"
621 See MMC1_PINS help text.
623 config MMC_SUNXI_SLOT_EXTRA
624 int "mmc extra slot number"
627 sunxi builds always enable mmc0, some boards also have a second sdcard
628 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
631 config INITIAL_USB_SCAN_DELAY
632 int "delay initial usb scan by x ms to allow builtin devices to init"
635 Some boards have on board usb devices which need longer than the
636 USB spec's 1 second to connect from board powerup. Set this config
637 option to a non 0 value to add an extra delay before the first usb
641 string "Vbus enable pin for usb0 (otg)"
644 Set the Vbus enable pin for usb0 (otg). This takes a string in the
645 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
648 string "Vbus detect pin for usb0 (otg)"
651 Set the Vbus detect pin for usb0 (otg). This takes a string in the
652 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
655 string "ID detect pin for usb0 (otg)"
658 Set the ID detect pin for usb0 (otg). This takes a string in the
659 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
662 string "Vbus enable pin for usb1 (ehci0)"
663 default "PH6" if MACH_SUN4I || MACH_SUN7I
664 default "PH27" if MACH_SUN6I
666 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
667 a string in the format understood by sunxi_name_to_gpio, e.g.
668 PH1 for pin 1 of port H.
671 string "Vbus enable pin for usb2 (ehci1)"
672 default "PH3" if MACH_SUN4I || MACH_SUN7I
673 default "PH24" if MACH_SUN6I
675 See USB1_VBUS_PIN help text.
678 string "Vbus enable pin for usb3 (ehci2)"
681 See USB1_VBUS_PIN help text.
684 bool "Enable I2C/TWI controller 0"
685 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
686 default n if MACH_SUN6I || MACH_SUN8I
689 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
690 its clock and setting up the bus. This is especially useful on devices
691 with slaves connected to the bus or with pins exposed through e.g. an
692 expansion port/header.
695 bool "Enable I2C/TWI controller 1"
699 See I2C0_ENABLE help text.
702 bool "Enable I2C/TWI controller 2"
706 See I2C0_ENABLE help text.
708 if MACH_SUN6I || MACH_SUN7I
710 bool "Enable I2C/TWI controller 3"
714 See I2C0_ENABLE help text.
719 bool "Enable the PRCM I2C/TWI controller"
720 # This is used for the pmic on H3
721 default y if SY8106A_POWER
724 Set this to y to enable the I2C controller which is part of the PRCM.
729 bool "Enable I2C/TWI controller 4"
733 See I2C0_ENABLE help text.
737 bool "Enable support for gpio-s on axp PMICs"
740 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
743 bool "Enable graphical uboot console on HDMI, LCD or VGA"
744 depends on !MACH_SUN8I_A83T
745 depends on !MACH_SUNXI_H3_H5
746 depends on !MACH_SUN8I_R40
747 depends on !MACH_SUN8I_V3S
748 depends on !MACH_SUN9I
749 depends on !MACH_SUN50I
750 depends on !MACH_SUN50I_H6
752 imply VIDEO_DT_SIMPLEFB
755 Say Y here to add support for using a cfb console on the HDMI, LCD
756 or VGA output found on most sunxi devices. See doc/README.video for
757 info on how to select the video output and mode.
760 bool "HDMI output support"
761 depends on VIDEO_SUNXI && !MACH_SUN8I
764 Say Y here to add support for outputting video over HDMI.
767 bool "VGA output support"
768 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
771 Say Y here to add support for outputting video over VGA.
773 config VIDEO_VGA_VIA_LCD
774 bool "VGA via LCD controller support"
775 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
778 Say Y here to add support for external DACs connected to the parallel
779 LCD interface driving a VGA connector, such as found on the
782 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
783 bool "Force sync active high for VGA via LCD controller support"
784 depends on VIDEO_VGA_VIA_LCD
787 Say Y here if you've a board which uses opendrain drivers for the vga
788 hsync and vsync signals. Opendrain drivers cannot generate steep enough
789 positive edges for a stable video output, so on boards with opendrain
790 drivers the sync signals must always be active high.
792 config VIDEO_VGA_EXTERNAL_DAC_EN
793 string "LCD panel power enable pin"
794 depends on VIDEO_VGA_VIA_LCD
797 Set the enable pin for the external VGA DAC. This takes a string in the
798 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
800 config VIDEO_COMPOSITE
801 bool "Composite video output support"
802 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
805 Say Y here to add support for outputting composite video.
807 config VIDEO_LCD_MODE
808 string "LCD panel timing details"
809 depends on VIDEO_SUNXI
812 LCD panel timing details string, leave empty if there is no LCD panel.
813 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
814 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
815 Also see: http://linux-sunxi.org/LCD
817 config VIDEO_LCD_DCLK_PHASE
818 int "LCD panel display clock phase"
819 depends on VIDEO_SUNXI || DM_VIDEO
822 Select LCD panel display clock phase shift, range 0-3.
824 config VIDEO_LCD_POWER
825 string "LCD panel power enable pin"
826 depends on VIDEO_SUNXI
829 Set the power enable pin for the LCD panel. This takes a string in the
830 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
832 config VIDEO_LCD_RESET
833 string "LCD panel reset pin"
834 depends on VIDEO_SUNXI
837 Set the reset pin for the LCD panel. This takes a string in the format
838 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
840 config VIDEO_LCD_BL_EN
841 string "LCD panel backlight enable pin"
842 depends on VIDEO_SUNXI
845 Set the backlight enable pin for the LCD panel. This takes a string in the
846 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
849 config VIDEO_LCD_BL_PWM
850 string "LCD panel backlight pwm pin"
851 depends on VIDEO_SUNXI
854 Set the backlight pwm pin for the LCD panel. This takes a string in the
855 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
857 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
858 bool "LCD panel backlight pwm is inverted"
859 depends on VIDEO_SUNXI
862 Set this if the backlight pwm output is active low.
864 config VIDEO_LCD_PANEL_I2C
865 bool "LCD panel needs to be configured via i2c"
866 depends on VIDEO_SUNXI
870 Say y here if the LCD panel needs to be configured via i2c. This
871 will add a bitbang i2c controller using gpios to talk to the LCD.
873 config VIDEO_LCD_PANEL_I2C_SDA
874 string "LCD panel i2c interface SDA pin"
875 depends on VIDEO_LCD_PANEL_I2C
878 Set the SDA pin for the LCD i2c interface. This takes a string in the
879 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
881 config VIDEO_LCD_PANEL_I2C_SCL
882 string "LCD panel i2c interface SCL pin"
883 depends on VIDEO_LCD_PANEL_I2C
886 Set the SCL pin for the LCD i2c interface. This takes a string in the
887 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
890 # Note only one of these may be selected at a time! But hidden choices are
891 # not supported by Kconfig
892 config VIDEO_LCD_IF_PARALLEL
895 config VIDEO_LCD_IF_LVDS
903 bool "Display Engine 2 video driver"
907 imply VIDEO_DT_SIMPLEFB
910 Say y here if you want to build DE2 video driver which is present on
911 newer SoCs. Currently only HDMI output is supported.
915 prompt "LCD panel support"
916 depends on VIDEO_SUNXI
918 Select which type of LCD panel to support.
920 config VIDEO_LCD_PANEL_PARALLEL
921 bool "Generic parallel interface LCD panel"
922 select VIDEO_LCD_IF_PARALLEL
924 config VIDEO_LCD_PANEL_LVDS
925 bool "Generic lvds interface LCD panel"
926 select VIDEO_LCD_IF_LVDS
928 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
929 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
930 select VIDEO_LCD_SSD2828
931 select VIDEO_LCD_IF_PARALLEL
933 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
935 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
936 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
937 select VIDEO_LCD_ANX9804
938 select VIDEO_LCD_IF_PARALLEL
939 select VIDEO_LCD_PANEL_I2C
941 Select this for eDP LCD panels with 4 lanes running at 1.62G,
942 connected via an ANX9804 bridge chip.
944 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
945 bool "Hitachi tx18d42vm LCD panel"
946 select VIDEO_LCD_HITACHI_TX18D42VM
947 select VIDEO_LCD_IF_LVDS
949 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
951 config VIDEO_LCD_TL059WV5C0
952 bool "tl059wv5c0 LCD panel"
953 select VIDEO_LCD_PANEL_I2C
954 select VIDEO_LCD_IF_PARALLEL
956 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
957 Aigo M60/M608/M606 tablets.
962 string "SATA power pin"
965 Set the pins used to power the SATA. This takes a string in the
966 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
970 int "GMAC Transmit Clock Delay Chain"
973 Set the GMAC Transmit Clock Delay Chain value.
975 config SPL_STACK_R_ADDR
976 default 0x4fe00000 if MACH_SUN4I
977 default 0x4fe00000 if MACH_SUN5I
978 default 0x4fe00000 if MACH_SUN6I
979 default 0x4fe00000 if MACH_SUN7I
980 default 0x4fe00000 if MACH_SUN8I
981 default 0x2fe00000 if MACH_SUN9I
982 default 0x4fe00000 if MACH_SUN50I
983 default 0x4fe00000 if MACH_SUN50I_H6
986 bool "Support for SPI Flash on Allwinner SoCs in SPL"
987 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
989 Enable support for SPI Flash. This option allows SPL to read from
990 sunxi SPI Flash. It uses the same method as the boot ROM, so does
991 not need any extra configuration.
993 config PINE64_DT_SELECTION
994 bool "Enable Pine64 device tree selection code"
995 depends on MACH_SUN50I
997 The original Pine A64 and Pine A64+ are similar but different
998 boards and can be differed by the DRAM size. Pine A64 has
999 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1000 option, the device tree selection code specific to Pine64 which
1001 utilizes the DRAM size will be enabled.