4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
155 select SUNXI_DRAM_DW_16BIT
157 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
160 bool "sun9i (Allwinner A80)"
162 select SUNXI_HIGH_SRAM
163 select SUNXI_GEN_SUN6I
167 bool "sun50i (Allwinner A64)"
171 select SUNXI_GEN_SUN6I
172 select SUNXI_HIGH_SRAM
175 select SUNXI_DRAM_DW_32BIT
179 config MACH_SUN50I_H5
180 bool "sun50i (Allwinner H5)"
182 select MACH_SUNXI_H3_H5
183 select SUNXI_HIGH_SRAM
189 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
192 default y if MACH_SUN8I_A23
193 default y if MACH_SUN8I_A33
194 default y if MACH_SUN8I_A83T
195 default y if MACH_SUNXI_H3_H5
196 default y if MACH_SUN8I_R40
197 default y if MACH_SUN8I_V3S
199 config RESERVE_ALLWINNER_BOOT0_HEADER
200 bool "reserve space for Allwinner boot0 header"
201 select ENABLE_ARM_SOC_BOOT0_HOOK
203 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
204 filled with magic values post build. The Allwinner provided boot0
205 blob relies on this information to load and execute U-Boot.
206 Only needed on 64-bit Allwinner boards so far when using boot0.
208 config ARM_BOOT_HOOK_RMR
212 select ENABLE_ARM_SOC_BOOT0_HOOK
214 Insert some ARM32 code at the very beginning of the U-Boot binary
215 which uses an RMR register write to bring the core into AArch64 mode.
216 The very first instruction acts as a switch, since it's carefully
217 chosen to be a NOP in one mode and a branch in the other, so the
218 code would only be executed if not already in AArch64.
219 This allows both the SPL and the U-Boot proper to be entered in
220 either mode and switch to AArch64 if needed.
223 config SUNXI_DRAM_DDR3
226 config SUNXI_DRAM_DDR2
230 prompt "DRAM Type and Timing"
231 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
232 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
234 config SUNXI_DRAM_DDR3_1333
236 select SUNXI_DRAM_DDR3
237 depends on !MACH_SUN8I_V3S
239 This option is the original only supported memory type, which suits
240 many H3/H5/A64 boards available now.
242 config SUNXI_DRAM_DDR2_V3S
243 bool "DDR2 found in V3s chip"
244 select SUNXI_DRAM_DDR2
245 depends on MACH_SUN8I_V3S
247 This option is only for the DDR2 memory chip which is co-packaged in
254 int "sunxi dram type"
255 depends on MACH_SUN8I_A83T
258 Set the dram type, 3: DDR3, 7: LPDDR3
261 int "sunxi dram clock speed"
262 default 792 if MACH_SUN9I
263 default 648 if MACH_SUN8I_R40
264 default 312 if MACH_SUN6I || MACH_SUN8I
265 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
267 default 672 if MACH_SUN50I
269 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
270 must be a multiple of 24. For the sun9i (A80), the tested values
271 (for DDR3-1600) are 312 to 792.
273 if MACH_SUN5I || MACH_SUN7I
275 int "sunxi mbus clock speed"
278 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
283 int "sunxi dram zq value"
284 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
285 default 127 if MACH_SUN7I
286 default 14779 if MACH_SUN8I_V3S
287 default 3881979 if MACH_SUN8I_R40
288 default 4145117 if MACH_SUN9I
289 default 3881915 if MACH_SUN50I
291 Set the dram zq value.
294 bool "sunxi dram odt enable"
295 default n if !MACH_SUN8I_A23
296 default y if MACH_SUN8I_A23
297 default y if MACH_SUN8I_R40
298 default y if MACH_SUN50I
300 Select this to enable dram odt (on die termination).
302 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
304 int "sunxi dram emr1 value"
305 default 0 if MACH_SUN4I
306 default 4 if MACH_SUN5I || MACH_SUN7I
308 Set the dram controller emr1 value.
311 hex "sunxi dram tpr3 value"
314 Set the dram controller tpr3 parameter. This parameter configures
315 the delay on the command lane and also phase shifts, which are
316 applied for sampling incoming read data. The default value 0
317 means that no phase/delay adjustments are necessary. Properly
318 configuring this parameter increases reliability at high DRAM
321 config DRAM_DQS_GATING_DELAY
322 hex "sunxi dram dqs_gating_delay value"
325 Set the dram controller dqs_gating_delay parmeter. Each byte
326 encodes the DQS gating delay for each byte lane. The delay
327 granularity is 1/4 cycle. For example, the value 0x05060606
328 means that the delay is 5 quarter-cycles for one lane (1.25
329 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
330 The default value 0 means autodetection. The results of hardware
331 autodetection are not very reliable and depend on the chip
332 temperature (sometimes producing different results on cold start
333 and warm reboot). But the accuracy of hardware autodetection
334 is usually good enough, unless running at really high DRAM
335 clocks speeds (up to 600MHz). If unsure, keep as 0.
338 prompt "sunxi dram timings"
339 default DRAM_TIMINGS_VENDOR_MAGIC
341 Select the timings of the DDR3 chips.
343 config DRAM_TIMINGS_VENDOR_MAGIC
344 bool "Magic vendor timings from Android"
346 The same DRAM timings as in the Allwinner boot0 bootloader.
348 config DRAM_TIMINGS_DDR3_1066F_1333H
349 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
351 Use the timings of the standard JEDEC DDR3-1066F speed bin for
352 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
353 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
354 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
355 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
356 that down binning to DDR3-1066F is supported (because DDR3-1066F
357 uses a bit faster timings than DDR3-1333H).
359 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
360 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
362 Use the timings of the slowest possible JEDEC speed bin for the
363 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
364 DDR3-800E, DDR3-1066G or DDR3-1333J.
371 config DRAM_ODT_CORRECTION
372 int "sunxi dram odt correction value"
375 Set the dram odt correction value (range -255 - 255). In allwinner
376 fex files, this option is found in bits 8-15 of the u32 odt_en variable
377 in the [dram] section. When bit 31 of the odt_en variable is set
378 then the correction is negative. Usually the value for this is 0.
382 default 1008000000 if MACH_SUN4I
383 default 1008000000 if MACH_SUN5I
384 default 1008000000 if MACH_SUN6I
385 default 912000000 if MACH_SUN7I
386 default 1008000000 if MACH_SUN8I
387 default 1008000000 if MACH_SUN9I
388 default 816000000 if MACH_SUN50I
390 config SYS_CONFIG_NAME
391 default "sun4i" if MACH_SUN4I
392 default "sun5i" if MACH_SUN5I
393 default "sun6i" if MACH_SUN6I
394 default "sun7i" if MACH_SUN7I
395 default "sun8i" if MACH_SUN8I
396 default "sun9i" if MACH_SUN9I
397 default "sun50i" if MACH_SUN50I
406 bool "UART0 on MicroSD breakout board"
409 Repurpose the SD card slot for getting access to the UART0 serial
410 console. Primarily useful only for low level u-boot debugging on
411 tablets, where normal UART0 is difficult to access and requires
412 device disassembly and/or soldering. As the SD card can't be used
413 at the same time, the system can be only booted in the FEL mode.
414 Only enable this if you really know what you are doing.
416 config OLD_SUNXI_KERNEL_COMPAT
417 bool "Enable workarounds for booting old kernels"
420 Set this to enable various workarounds for old kernels, this results in
421 sub-optimal settings for newer kernels, only enable if needed.
424 string "MAC power pin"
427 Set the pin used to power the MAC. This takes a string in the format
428 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
431 string "Card detect pin for mmc0"
432 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
435 Set the card detect pin for mmc0, leave empty to not use cd. This
436 takes a string in the format understood by sunxi_name_to_gpio, e.g.
437 PH1 for pin 1 of port H.
440 string "Card detect pin for mmc1"
443 See MMC0_CD_PIN help text.
446 string "Card detect pin for mmc2"
449 See MMC0_CD_PIN help text.
452 string "Card detect pin for mmc3"
455 See MMC0_CD_PIN help text.
458 string "Pins for mmc1"
461 Set the pins used for mmc1, when applicable. This takes a string in the
462 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
465 string "Pins for mmc2"
468 See MMC1_PINS help text.
471 string "Pins for mmc3"
474 See MMC1_PINS help text.
476 config MMC_SUNXI_SLOT_EXTRA
477 int "mmc extra slot number"
480 sunxi builds always enable mmc0, some boards also have a second sdcard
481 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
484 config INITIAL_USB_SCAN_DELAY
485 int "delay initial usb scan by x ms to allow builtin devices to init"
488 Some boards have on board usb devices which need longer than the
489 USB spec's 1 second to connect from board powerup. Set this config
490 option to a non 0 value to add an extra delay before the first usb
494 string "Vbus enable pin for usb0 (otg)"
497 Set the Vbus enable pin for usb0 (otg). This takes a string in the
498 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
501 string "Vbus detect pin for usb0 (otg)"
504 Set the Vbus detect pin for usb0 (otg). This takes a string in the
505 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
508 string "ID detect pin for usb0 (otg)"
511 Set the ID detect pin for usb0 (otg). This takes a string in the
512 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
515 string "Vbus enable pin for usb1 (ehci0)"
516 default "PH6" if MACH_SUN4I || MACH_SUN7I
517 default "PH27" if MACH_SUN6I
519 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
520 a string in the format understood by sunxi_name_to_gpio, e.g.
521 PH1 for pin 1 of port H.
524 string "Vbus enable pin for usb2 (ehci1)"
525 default "PH3" if MACH_SUN4I || MACH_SUN7I
526 default "PH24" if MACH_SUN6I
528 See USB1_VBUS_PIN help text.
531 string "Vbus enable pin for usb3 (ehci2)"
534 See USB1_VBUS_PIN help text.
537 bool "Enable I2C/TWI controller 0"
538 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
539 default n if MACH_SUN6I || MACH_SUN8I
542 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
543 its clock and setting up the bus. This is especially useful on devices
544 with slaves connected to the bus or with pins exposed through e.g. an
545 expansion port/header.
548 bool "Enable I2C/TWI controller 1"
552 See I2C0_ENABLE help text.
555 bool "Enable I2C/TWI controller 2"
559 See I2C0_ENABLE help text.
561 if MACH_SUN6I || MACH_SUN7I
563 bool "Enable I2C/TWI controller 3"
567 See I2C0_ENABLE help text.
572 bool "Enable the PRCM I2C/TWI controller"
573 # This is used for the pmic on H3
574 default y if SY8106A_POWER
577 Set this to y to enable the I2C controller which is part of the PRCM.
582 bool "Enable I2C/TWI controller 4"
586 See I2C0_ENABLE help text.
590 bool "Enable support for gpio-s on axp PMICs"
593 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
596 bool "Enable graphical uboot console on HDMI, LCD or VGA"
597 depends on !MACH_SUN8I_A83T
598 depends on !MACH_SUNXI_H3_H5
599 depends on !MACH_SUN8I_R40
600 depends on !MACH_SUN8I_V3S
601 depends on !MACH_SUN9I
602 depends on !MACH_SUN50I
605 Say Y here to add support for using a cfb console on the HDMI, LCD
606 or VGA output found on most sunxi devices. See doc/README.video for
607 info on how to select the video output and mode.
610 bool "HDMI output support"
611 depends on VIDEO && !MACH_SUN8I
614 Say Y here to add support for outputting video over HDMI.
617 bool "VGA output support"
618 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
621 Say Y here to add support for outputting video over VGA.
623 config VIDEO_VGA_VIA_LCD
624 bool "VGA via LCD controller support"
625 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
628 Say Y here to add support for external DACs connected to the parallel
629 LCD interface driving a VGA connector, such as found on the
632 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
633 bool "Force sync active high for VGA via LCD controller support"
634 depends on VIDEO_VGA_VIA_LCD
637 Say Y here if you've a board which uses opendrain drivers for the vga
638 hsync and vsync signals. Opendrain drivers cannot generate steep enough
639 positive edges for a stable video output, so on boards with opendrain
640 drivers the sync signals must always be active high.
642 config VIDEO_VGA_EXTERNAL_DAC_EN
643 string "LCD panel power enable pin"
644 depends on VIDEO_VGA_VIA_LCD
647 Set the enable pin for the external VGA DAC. This takes a string in the
648 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
650 config VIDEO_COMPOSITE
651 bool "Composite video output support"
652 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
655 Say Y here to add support for outputting composite video.
657 config VIDEO_LCD_MODE
658 string "LCD panel timing details"
662 LCD panel timing details string, leave empty if there is no LCD panel.
663 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
664 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
665 Also see: http://linux-sunxi.org/LCD
667 config VIDEO_LCD_DCLK_PHASE
668 int "LCD panel display clock phase"
672 Select LCD panel display clock phase shift, range 0-3.
674 config VIDEO_LCD_POWER
675 string "LCD panel power enable pin"
679 Set the power enable pin for the LCD panel. This takes a string in the
680 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
682 config VIDEO_LCD_RESET
683 string "LCD panel reset pin"
687 Set the reset pin for the LCD panel. This takes a string in the format
688 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
690 config VIDEO_LCD_BL_EN
691 string "LCD panel backlight enable pin"
695 Set the backlight enable pin for the LCD panel. This takes a string in the
696 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
699 config VIDEO_LCD_BL_PWM
700 string "LCD panel backlight pwm pin"
704 Set the backlight pwm pin for the LCD panel. This takes a string in the
705 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
707 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
708 bool "LCD panel backlight pwm is inverted"
712 Set this if the backlight pwm output is active low.
714 config VIDEO_LCD_PANEL_I2C
715 bool "LCD panel needs to be configured via i2c"
720 Say y here if the LCD panel needs to be configured via i2c. This
721 will add a bitbang i2c controller using gpios to talk to the LCD.
723 config VIDEO_LCD_PANEL_I2C_SDA
724 string "LCD panel i2c interface SDA pin"
725 depends on VIDEO_LCD_PANEL_I2C
728 Set the SDA pin for the LCD i2c interface. This takes a string in the
729 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
731 config VIDEO_LCD_PANEL_I2C_SCL
732 string "LCD panel i2c interface SCL pin"
733 depends on VIDEO_LCD_PANEL_I2C
736 Set the SCL pin for the LCD i2c interface. This takes a string in the
737 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
740 # Note only one of these may be selected at a time! But hidden choices are
741 # not supported by Kconfig
742 config VIDEO_LCD_IF_PARALLEL
745 config VIDEO_LCD_IF_LVDS
753 bool "Display Engine 2 video driver"
759 Say y here if you want to build DE2 video driver which is present on
760 newer SoCs. Currently only HDMI output is supported.
764 prompt "LCD panel support"
767 Select which type of LCD panel to support.
769 config VIDEO_LCD_PANEL_PARALLEL
770 bool "Generic parallel interface LCD panel"
771 select VIDEO_LCD_IF_PARALLEL
773 config VIDEO_LCD_PANEL_LVDS
774 bool "Generic lvds interface LCD panel"
775 select VIDEO_LCD_IF_LVDS
777 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
778 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
779 select VIDEO_LCD_SSD2828
780 select VIDEO_LCD_IF_PARALLEL
782 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
784 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
785 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
786 select VIDEO_LCD_ANX9804
787 select VIDEO_LCD_IF_PARALLEL
788 select VIDEO_LCD_PANEL_I2C
790 Select this for eDP LCD panels with 4 lanes running at 1.62G,
791 connected via an ANX9804 bridge chip.
793 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
794 bool "Hitachi tx18d42vm LCD panel"
795 select VIDEO_LCD_HITACHI_TX18D42VM
796 select VIDEO_LCD_IF_LVDS
798 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
800 config VIDEO_LCD_TL059WV5C0
801 bool "tl059wv5c0 LCD panel"
802 select VIDEO_LCD_PANEL_I2C
803 select VIDEO_LCD_IF_PARALLEL
805 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
806 Aigo M60/M608/M606 tablets.
811 string "SATA power pin"
814 Set the pins used to power the SATA. This takes a string in the
815 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
819 int "GMAC Transmit Clock Delay Chain"
822 Set the GMAC Transmit Clock Delay Chain value.
824 config SPL_STACK_R_ADDR
825 default 0x4fe00000 if MACH_SUN4I
826 default 0x4fe00000 if MACH_SUN5I
827 default 0x4fe00000 if MACH_SUN6I
828 default 0x4fe00000 if MACH_SUN7I
829 default 0x4fe00000 if MACH_SUN8I
830 default 0x2fe00000 if MACH_SUN9I
831 default 0x4fe00000 if MACH_SUN50I