4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
144 prompt "Sunxi SoC Variant"
148 bool "sun4i (Allwinner A10)"
150 select ARM_CORTEX_CPU_IS_UP
152 select DM_SCSI if SCSI
155 select SUNXI_GEN_SUN4I
159 bool "sun5i (Allwinner A13)"
161 select ARM_CORTEX_CPU_IS_UP
164 select SUNXI_GEN_SUN4I
166 imply CONS_INDEX_2 if !DM_SERIAL
169 bool "sun6i (Allwinner A31)"
171 select CPU_V7_HAS_NONSEC
172 select CPU_V7_HAS_VIRT
173 select ARCH_SUPPORT_PSCI
178 select SUNXI_GEN_SUN6I
180 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
183 bool "sun7i (Allwinner A20)"
185 select CPU_V7_HAS_NONSEC
186 select CPU_V7_HAS_VIRT
187 select ARCH_SUPPORT_PSCI
190 select SUNXI_GEN_SUN4I
192 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
194 config MACH_SUN8I_A23
195 bool "sun8i (Allwinner A23)"
197 select CPU_V7_HAS_NONSEC
198 select CPU_V7_HAS_VIRT
199 select ARCH_SUPPORT_PSCI
200 select DRAM_SUN8I_A23
202 select SUNXI_GEN_SUN6I
204 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
205 imply CONS_INDEX_5 if !DM_SERIAL
207 config MACH_SUN8I_A33
208 bool "sun8i (Allwinner A33)"
210 select CPU_V7_HAS_NONSEC
211 select CPU_V7_HAS_VIRT
212 select ARCH_SUPPORT_PSCI
213 select DRAM_SUN8I_A33
215 select SUNXI_GEN_SUN6I
217 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
218 imply CONS_INDEX_5 if !DM_SERIAL
220 config MACH_SUN8I_A83T
221 bool "sun8i (Allwinner A83T)"
223 select DRAM_SUN8I_A83T
225 select SUNXI_GEN_SUN6I
226 select MMC_SUNXI_HAS_NEW_MODE
230 bool "sun8i (Allwinner H3)"
232 select CPU_V7_HAS_NONSEC
233 select CPU_V7_HAS_VIRT
234 select ARCH_SUPPORT_PSCI
235 select MACH_SUNXI_H3_H5
236 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
238 config MACH_SUN8I_R40
239 bool "sun8i (Allwinner R40)"
241 select CPU_V7_HAS_NONSEC
242 select CPU_V7_HAS_VIRT
243 select ARCH_SUPPORT_PSCI
244 select SUNXI_GEN_SUN6I
247 select SUNXI_DRAM_DW_32BIT
249 config MACH_SUN8I_V3S
250 bool "sun8i (Allwinner V3s)"
252 select CPU_V7_HAS_NONSEC
253 select CPU_V7_HAS_VIRT
254 select ARCH_SUPPORT_PSCI
255 select SUNXI_GEN_SUN6I
257 select SUNXI_DRAM_DW_16BIT
259 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
262 bool "sun9i (Allwinner A80)"
266 select SUNXI_GEN_SUN6I
271 bool "sun50i (Allwinner A64)"
276 select SUNXI_GEN_SUN6I
279 select SUNXI_DRAM_DW_32BIT
282 select SUNXI_A64_TIMER_ERRATUM
284 config MACH_SUN50I_H5
285 bool "sun50i (Allwinner H5)"
287 select MACH_SUNXI_H3_H5
291 config MACH_SUN50I_H6
292 bool "sun50i (Allwinner H6)"
297 select DRAM_SUN50I_H6
301 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
306 default y if MACH_SUN8I_A23
307 default y if MACH_SUN8I_A33
308 default y if MACH_SUN8I_A83T
309 default y if MACH_SUNXI_H3_H5
310 default y if MACH_SUN8I_R40
311 default y if MACH_SUN8I_V3S
313 config RESERVE_ALLWINNER_BOOT0_HEADER
314 bool "reserve space for Allwinner boot0 header"
315 select ENABLE_ARM_SOC_BOOT0_HOOK
317 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
318 filled with magic values post build. The Allwinner provided boot0
319 blob relies on this information to load and execute U-Boot.
320 Only needed on 64-bit Allwinner boards so far when using boot0.
322 config ARM_BOOT_HOOK_RMR
326 select ENABLE_ARM_SOC_BOOT0_HOOK
328 Insert some ARM32 code at the very beginning of the U-Boot binary
329 which uses an RMR register write to bring the core into AArch64 mode.
330 The very first instruction acts as a switch, since it's carefully
331 chosen to be a NOP in one mode and a branch in the other, so the
332 code would only be executed if not already in AArch64.
333 This allows both the SPL and the U-Boot proper to be entered in
334 either mode and switch to AArch64 if needed.
337 config SUNXI_DRAM_DDR3
340 config SUNXI_DRAM_DDR2
343 config SUNXI_DRAM_LPDDR3
347 prompt "DRAM Type and Timing"
348 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
349 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
351 config SUNXI_DRAM_DDR3_1333
353 select SUNXI_DRAM_DDR3
354 depends on !MACH_SUN8I_V3S
356 This option is the original only supported memory type, which suits
357 many H3/H5/A64 boards available now.
359 config SUNXI_DRAM_LPDDR3_STOCK
360 bool "LPDDR3 with Allwinner stock configuration"
361 select SUNXI_DRAM_LPDDR3
363 This option is the LPDDR3 timing used by the stock boot0 by
366 config SUNXI_DRAM_DDR2_V3S
367 bool "DDR2 found in V3s chip"
368 select SUNXI_DRAM_DDR2
369 depends on MACH_SUN8I_V3S
371 This option is only for the DDR2 memory chip which is co-packaged in
378 int "sunxi dram type"
379 depends on MACH_SUN8I_A83T
382 Set the dram type, 3: DDR3, 7: LPDDR3
385 int "sunxi dram clock speed"
386 default 792 if MACH_SUN9I
387 default 648 if MACH_SUN8I_R40
388 default 312 if MACH_SUN6I || MACH_SUN8I
389 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
391 default 672 if MACH_SUN50I
392 default 744 if MACH_SUN50I_H6
394 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
395 must be a multiple of 24. For the sun9i (A80), the tested values
396 (for DDR3-1600) are 312 to 792.
398 if MACH_SUN5I || MACH_SUN7I
400 int "sunxi mbus clock speed"
403 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
408 int "sunxi dram zq value"
409 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
410 default 127 if MACH_SUN7I
411 default 14779 if MACH_SUN8I_V3S
412 default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
413 default 4145117 if MACH_SUN9I
414 default 3881915 if MACH_SUN50I
416 Set the dram zq value.
419 bool "sunxi dram odt enable"
420 default n if !MACH_SUN8I_A23
421 default y if MACH_SUN8I_A23
422 default y if MACH_SUN8I_R40
423 default y if MACH_SUN50I
424 default y if MACH_SUN50I_H6
426 Select this to enable dram odt (on die termination).
428 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
430 int "sunxi dram emr1 value"
431 default 0 if MACH_SUN4I
432 default 4 if MACH_SUN5I || MACH_SUN7I
434 Set the dram controller emr1 value.
437 hex "sunxi dram tpr3 value"
440 Set the dram controller tpr3 parameter. This parameter configures
441 the delay on the command lane and also phase shifts, which are
442 applied for sampling incoming read data. The default value 0
443 means that no phase/delay adjustments are necessary. Properly
444 configuring this parameter increases reliability at high DRAM
447 config DRAM_DQS_GATING_DELAY
448 hex "sunxi dram dqs_gating_delay value"
451 Set the dram controller dqs_gating_delay parmeter. Each byte
452 encodes the DQS gating delay for each byte lane. The delay
453 granularity is 1/4 cycle. For example, the value 0x05060606
454 means that the delay is 5 quarter-cycles for one lane (1.25
455 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
456 The default value 0 means autodetection. The results of hardware
457 autodetection are not very reliable and depend on the chip
458 temperature (sometimes producing different results on cold start
459 and warm reboot). But the accuracy of hardware autodetection
460 is usually good enough, unless running at really high DRAM
461 clocks speeds (up to 600MHz). If unsure, keep as 0.
464 prompt "sunxi dram timings"
465 default DRAM_TIMINGS_VENDOR_MAGIC
467 Select the timings of the DDR3 chips.
469 config DRAM_TIMINGS_VENDOR_MAGIC
470 bool "Magic vendor timings from Android"
472 The same DRAM timings as in the Allwinner boot0 bootloader.
474 config DRAM_TIMINGS_DDR3_1066F_1333H
475 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
477 Use the timings of the standard JEDEC DDR3-1066F speed bin for
478 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
479 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
480 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
481 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
482 that down binning to DDR3-1066F is supported (because DDR3-1066F
483 uses a bit faster timings than DDR3-1333H).
485 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
486 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
488 Use the timings of the slowest possible JEDEC speed bin for the
489 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
490 DDR3-800E, DDR3-1066G or DDR3-1333J.
497 config DRAM_ODT_CORRECTION
498 int "sunxi dram odt correction value"
501 Set the dram odt correction value (range -255 - 255). In allwinner
502 fex files, this option is found in bits 8-15 of the u32 odt_en variable
503 in the [dram] section. When bit 31 of the odt_en variable is set
504 then the correction is negative. Usually the value for this is 0.
508 default 1008000000 if MACH_SUN4I
509 default 1008000000 if MACH_SUN5I
510 default 1008000000 if MACH_SUN6I
511 default 912000000 if MACH_SUN7I
512 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
513 default 1008000000 if MACH_SUN8I
514 default 1008000000 if MACH_SUN9I
515 default 888000000 if MACH_SUN50I_H6
517 config SYS_CONFIG_NAME
518 default "sun4i" if MACH_SUN4I
519 default "sun5i" if MACH_SUN5I
520 default "sun6i" if MACH_SUN6I
521 default "sun7i" if MACH_SUN7I
522 default "sun8i" if MACH_SUN8I
523 default "sun9i" if MACH_SUN9I
524 default "sun50i" if MACH_SUN50I
525 default "sun50i" if MACH_SUN50I_H6
534 bool "UART0 on MicroSD breakout board"
537 Repurpose the SD card slot for getting access to the UART0 serial
538 console. Primarily useful only for low level u-boot debugging on
539 tablets, where normal UART0 is difficult to access and requires
540 device disassembly and/or soldering. As the SD card can't be used
541 at the same time, the system can be only booted in the FEL mode.
542 Only enable this if you really know what you are doing.
544 config OLD_SUNXI_KERNEL_COMPAT
545 bool "Enable workarounds for booting old kernels"
548 Set this to enable various workarounds for old kernels, this results in
549 sub-optimal settings for newer kernels, only enable if needed.
552 string "MAC power pin"
555 Set the pin used to power the MAC. This takes a string in the format
556 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
559 string "Card detect pin for mmc0"
560 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
563 Set the card detect pin for mmc0, leave empty to not use cd. This
564 takes a string in the format understood by sunxi_name_to_gpio, e.g.
565 PH1 for pin 1 of port H.
568 string "Card detect pin for mmc1"
571 See MMC0_CD_PIN help text.
574 string "Card detect pin for mmc2"
577 See MMC0_CD_PIN help text.
580 string "Card detect pin for mmc3"
583 See MMC0_CD_PIN help text.
586 string "Pins for mmc1"
589 Set the pins used for mmc1, when applicable. This takes a string in the
590 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
593 string "Pins for mmc2"
596 See MMC1_PINS help text.
599 string "Pins for mmc3"
602 See MMC1_PINS help text.
604 config MMC_SUNXI_SLOT_EXTRA
605 int "mmc extra slot number"
608 sunxi builds always enable mmc0, some boards also have a second sdcard
609 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
612 config INITIAL_USB_SCAN_DELAY
613 int "delay initial usb scan by x ms to allow builtin devices to init"
616 Some boards have on board usb devices which need longer than the
617 USB spec's 1 second to connect from board powerup. Set this config
618 option to a non 0 value to add an extra delay before the first usb
622 string "Vbus enable pin for usb0 (otg)"
625 Set the Vbus enable pin for usb0 (otg). This takes a string in the
626 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
629 string "Vbus detect pin for usb0 (otg)"
632 Set the Vbus detect pin for usb0 (otg). This takes a string in the
633 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
636 string "ID detect pin for usb0 (otg)"
639 Set the ID detect pin for usb0 (otg). This takes a string in the
640 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
643 string "Vbus enable pin for usb1 (ehci0)"
644 default "PH6" if MACH_SUN4I || MACH_SUN7I
645 default "PH27" if MACH_SUN6I
647 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
648 a string in the format understood by sunxi_name_to_gpio, e.g.
649 PH1 for pin 1 of port H.
652 string "Vbus enable pin for usb2 (ehci1)"
653 default "PH3" if MACH_SUN4I || MACH_SUN7I
654 default "PH24" if MACH_SUN6I
656 See USB1_VBUS_PIN help text.
659 string "Vbus enable pin for usb3 (ehci2)"
662 See USB1_VBUS_PIN help text.
665 bool "Enable I2C/TWI controller 0"
666 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
667 default n if MACH_SUN6I || MACH_SUN8I
670 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
671 its clock and setting up the bus. This is especially useful on devices
672 with slaves connected to the bus or with pins exposed through e.g. an
673 expansion port/header.
676 bool "Enable I2C/TWI controller 1"
680 See I2C0_ENABLE help text.
683 bool "Enable I2C/TWI controller 2"
687 See I2C0_ENABLE help text.
689 if MACH_SUN6I || MACH_SUN7I
691 bool "Enable I2C/TWI controller 3"
695 See I2C0_ENABLE help text.
700 bool "Enable the PRCM I2C/TWI controller"
701 # This is used for the pmic on H3
702 default y if SY8106A_POWER
705 Set this to y to enable the I2C controller which is part of the PRCM.
710 bool "Enable I2C/TWI controller 4"
714 See I2C0_ENABLE help text.
718 bool "Enable support for gpio-s on axp PMICs"
721 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
724 bool "Enable graphical uboot console on HDMI, LCD or VGA"
725 depends on !MACH_SUN8I_A83T
726 depends on !MACH_SUNXI_H3_H5
727 depends on !MACH_SUN8I_R40
728 depends on !MACH_SUN8I_V3S
729 depends on !MACH_SUN9I
730 depends on !MACH_SUN50I
731 depends on !MACH_SUN50I_H6
733 imply VIDEO_DT_SIMPLEFB
736 Say Y here to add support for using a cfb console on the HDMI, LCD
737 or VGA output found on most sunxi devices. See doc/README.video for
738 info on how to select the video output and mode.
741 bool "HDMI output support"
742 depends on VIDEO_SUNXI && !MACH_SUN8I
745 Say Y here to add support for outputting video over HDMI.
748 bool "VGA output support"
749 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
752 Say Y here to add support for outputting video over VGA.
754 config VIDEO_VGA_VIA_LCD
755 bool "VGA via LCD controller support"
756 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
759 Say Y here to add support for external DACs connected to the parallel
760 LCD interface driving a VGA connector, such as found on the
763 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
764 bool "Force sync active high for VGA via LCD controller support"
765 depends on VIDEO_VGA_VIA_LCD
768 Say Y here if you've a board which uses opendrain drivers for the vga
769 hsync and vsync signals. Opendrain drivers cannot generate steep enough
770 positive edges for a stable video output, so on boards with opendrain
771 drivers the sync signals must always be active high.
773 config VIDEO_VGA_EXTERNAL_DAC_EN
774 string "LCD panel power enable pin"
775 depends on VIDEO_VGA_VIA_LCD
778 Set the enable pin for the external VGA DAC. This takes a string in the
779 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
781 config VIDEO_COMPOSITE
782 bool "Composite video output support"
783 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
786 Say Y here to add support for outputting composite video.
788 config VIDEO_LCD_MODE
789 string "LCD panel timing details"
790 depends on VIDEO_SUNXI
793 LCD panel timing details string, leave empty if there is no LCD panel.
794 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
795 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
796 Also see: http://linux-sunxi.org/LCD
798 config VIDEO_LCD_DCLK_PHASE
799 int "LCD panel display clock phase"
800 depends on VIDEO_SUNXI || DM_VIDEO
803 Select LCD panel display clock phase shift, range 0-3.
805 config VIDEO_LCD_POWER
806 string "LCD panel power enable pin"
807 depends on VIDEO_SUNXI
810 Set the power enable pin for the LCD panel. This takes a string in the
811 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
813 config VIDEO_LCD_RESET
814 string "LCD panel reset pin"
815 depends on VIDEO_SUNXI
818 Set the reset pin for the LCD panel. This takes a string in the format
819 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
821 config VIDEO_LCD_BL_EN
822 string "LCD panel backlight enable pin"
823 depends on VIDEO_SUNXI
826 Set the backlight enable pin for the LCD panel. This takes a string in the
827 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
830 config VIDEO_LCD_BL_PWM
831 string "LCD panel backlight pwm pin"
832 depends on VIDEO_SUNXI
835 Set the backlight pwm pin for the LCD panel. This takes a string in the
836 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
838 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
839 bool "LCD panel backlight pwm is inverted"
840 depends on VIDEO_SUNXI
843 Set this if the backlight pwm output is active low.
845 config VIDEO_LCD_PANEL_I2C
846 bool "LCD panel needs to be configured via i2c"
847 depends on VIDEO_SUNXI
851 Say y here if the LCD panel needs to be configured via i2c. This
852 will add a bitbang i2c controller using gpios to talk to the LCD.
854 config VIDEO_LCD_PANEL_I2C_SDA
855 string "LCD panel i2c interface SDA pin"
856 depends on VIDEO_LCD_PANEL_I2C
859 Set the SDA pin for the LCD i2c interface. This takes a string in the
860 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
862 config VIDEO_LCD_PANEL_I2C_SCL
863 string "LCD panel i2c interface SCL pin"
864 depends on VIDEO_LCD_PANEL_I2C
867 Set the SCL pin for the LCD i2c interface. This takes a string in the
868 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
871 # Note only one of these may be selected at a time! But hidden choices are
872 # not supported by Kconfig
873 config VIDEO_LCD_IF_PARALLEL
876 config VIDEO_LCD_IF_LVDS
884 bool "Display Engine 2 video driver"
888 imply VIDEO_DT_SIMPLEFB
891 Say y here if you want to build DE2 video driver which is present on
892 newer SoCs. Currently only HDMI output is supported.
896 prompt "LCD panel support"
897 depends on VIDEO_SUNXI
899 Select which type of LCD panel to support.
901 config VIDEO_LCD_PANEL_PARALLEL
902 bool "Generic parallel interface LCD panel"
903 select VIDEO_LCD_IF_PARALLEL
905 config VIDEO_LCD_PANEL_LVDS
906 bool "Generic lvds interface LCD panel"
907 select VIDEO_LCD_IF_LVDS
909 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
910 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
911 select VIDEO_LCD_SSD2828
912 select VIDEO_LCD_IF_PARALLEL
914 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
916 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
917 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
918 select VIDEO_LCD_ANX9804
919 select VIDEO_LCD_IF_PARALLEL
920 select VIDEO_LCD_PANEL_I2C
922 Select this for eDP LCD panels with 4 lanes running at 1.62G,
923 connected via an ANX9804 bridge chip.
925 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
926 bool "Hitachi tx18d42vm LCD panel"
927 select VIDEO_LCD_HITACHI_TX18D42VM
928 select VIDEO_LCD_IF_LVDS
930 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
932 config VIDEO_LCD_TL059WV5C0
933 bool "tl059wv5c0 LCD panel"
934 select VIDEO_LCD_PANEL_I2C
935 select VIDEO_LCD_IF_PARALLEL
937 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
938 Aigo M60/M608/M606 tablets.
943 string "SATA power pin"
946 Set the pins used to power the SATA. This takes a string in the
947 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
951 int "GMAC Transmit Clock Delay Chain"
954 Set the GMAC Transmit Clock Delay Chain value.
956 config SPL_STACK_R_ADDR
957 default 0x4fe00000 if MACH_SUN4I
958 default 0x4fe00000 if MACH_SUN5I
959 default 0x4fe00000 if MACH_SUN6I
960 default 0x4fe00000 if MACH_SUN7I
961 default 0x4fe00000 if MACH_SUN8I
962 default 0x2fe00000 if MACH_SUN9I
963 default 0x4fe00000 if MACH_SUN50I
964 default 0x4fe00000 if MACH_SUN50I_H6
967 bool "Support for SPI Flash on Allwinner SoCs in SPL"
968 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
970 Enable support for SPI Flash. This option allows SPL to read from
971 sunxi SPI Flash. It uses the same method as the boot ROM, so does
972 not need any extra configuration.