4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
159 select SUNXI_GEN_SUN4I
163 bool "sun5i (Allwinner A13)"
165 select ARM_CORTEX_CPU_IS_UP
168 select SUNXI_GEN_SUN4I
170 imply CONS_INDEX_2 if !DM_SERIAL
173 bool "sun6i (Allwinner A31)"
175 select CPU_V7_HAS_NONSEC
176 select CPU_V7_HAS_VIRT
177 select ARCH_SUPPORT_PSCI
182 select SUNXI_GEN_SUN6I
184 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187 bool "sun7i (Allwinner A20)"
189 select CPU_V7_HAS_NONSEC
190 select CPU_V7_HAS_VIRT
191 select ARCH_SUPPORT_PSCI
194 select SUNXI_GEN_SUN4I
196 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
198 config MACH_SUN8I_A23
199 bool "sun8i (Allwinner A23)"
201 select CPU_V7_HAS_NONSEC
202 select CPU_V7_HAS_VIRT
203 select ARCH_SUPPORT_PSCI
204 select DRAM_SUN8I_A23
206 select SUNXI_GEN_SUN6I
208 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
209 imply CONS_INDEX_5 if !DM_SERIAL
211 config MACH_SUN8I_A33
212 bool "sun8i (Allwinner A33)"
214 select CPU_V7_HAS_NONSEC
215 select CPU_V7_HAS_VIRT
216 select ARCH_SUPPORT_PSCI
217 select DRAM_SUN8I_A33
219 select SUNXI_GEN_SUN6I
221 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
222 imply CONS_INDEX_5 if !DM_SERIAL
224 config MACH_SUN8I_A83T
225 bool "sun8i (Allwinner A83T)"
227 select DRAM_SUN8I_A83T
229 select SUNXI_GEN_SUN6I
230 select MMC_SUNXI_HAS_NEW_MODE
231 select MMC_SUNXI_HAS_MODE_SWITCH
235 bool "sun8i (Allwinner H3)"
237 select CPU_V7_HAS_NONSEC
238 select CPU_V7_HAS_VIRT
239 select ARCH_SUPPORT_PSCI
240 select MACH_SUNXI_H3_H5
241 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
243 config MACH_SUN8I_R40
244 bool "sun8i (Allwinner R40)"
246 select CPU_V7_HAS_NONSEC
247 select CPU_V7_HAS_VIRT
248 select ARCH_SUPPORT_PSCI
249 select SUNXI_GEN_SUN6I
252 select SUNXI_DRAM_DW_32BIT
255 config MACH_SUN8I_V3S
256 bool "sun8i (Allwinner V3s)"
258 select CPU_V7_HAS_NONSEC
259 select CPU_V7_HAS_VIRT
260 select ARCH_SUPPORT_PSCI
261 select SUNXI_GEN_SUN6I
263 select SUNXI_DRAM_DW_16BIT
265 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
268 bool "sun9i (Allwinner A80)"
272 select SUNXI_GEN_SUN6I
277 bool "sun50i (Allwinner A64)"
286 select SUNXI_GEN_SUN6I
287 select MMC_SUNXI_HAS_NEW_MODE
290 select SUNXI_DRAM_DW_32BIT
293 select SUNXI_A64_TIMER_ERRATUM
295 config MACH_SUN50I_H5
296 bool "sun50i (Allwinner H5)"
298 select MACH_SUNXI_H3_H5
302 config MACH_SUN50I_H6
303 bool "sun50i (Allwinner H6)"
309 select DRAM_SUN50I_H6
313 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
318 default y if MACH_SUN8I_A23
319 default y if MACH_SUN8I_A33
320 default y if MACH_SUN8I_A83T
321 default y if MACH_SUNXI_H3_H5
322 default y if MACH_SUN8I_R40
323 default y if MACH_SUN8I_V3S
325 config RESERVE_ALLWINNER_BOOT0_HEADER
326 bool "reserve space for Allwinner boot0 header"
327 select ENABLE_ARM_SOC_BOOT0_HOOK
329 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
330 filled with magic values post build. The Allwinner provided boot0
331 blob relies on this information to load and execute U-Boot.
332 Only needed on 64-bit Allwinner boards so far when using boot0.
334 config ARM_BOOT_HOOK_RMR
338 select ENABLE_ARM_SOC_BOOT0_HOOK
340 Insert some ARM32 code at the very beginning of the U-Boot binary
341 which uses an RMR register write to bring the core into AArch64 mode.
342 The very first instruction acts as a switch, since it's carefully
343 chosen to be a NOP in one mode and a branch in the other, so the
344 code would only be executed if not already in AArch64.
345 This allows both the SPL and the U-Boot proper to be entered in
346 either mode and switch to AArch64 if needed.
348 if SUNXI_DRAM_DW || DRAM_SUN50I_H6
349 config SUNXI_DRAM_DDR3
352 config SUNXI_DRAM_DDR2
355 config SUNXI_DRAM_LPDDR3
359 prompt "DRAM Type and Timing"
360 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
361 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
363 config SUNXI_DRAM_DDR3_1333
365 select SUNXI_DRAM_DDR3
366 depends on !MACH_SUN8I_V3S
368 This option is the original only supported memory type, which suits
369 many H3/H5/A64 boards available now.
371 config SUNXI_DRAM_LPDDR3_STOCK
372 bool "LPDDR3 with Allwinner stock configuration"
373 select SUNXI_DRAM_LPDDR3
375 This option is the LPDDR3 timing used by the stock boot0 by
378 config SUNXI_DRAM_H6_LPDDR3
379 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
380 select SUNXI_DRAM_LPDDR3
381 depends on DRAM_SUN50I_H6
383 This option is the LPDDR3 timing used by the stock boot0 by
386 config SUNXI_DRAM_H6_DDR3_1333
387 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
388 select SUNXI_DRAM_DDR3
389 depends on DRAM_SUN50I_H6
391 This option is the DDR3 timing used by the boot0 on H6 TV boxes
392 which use a DDR3-1333 timing.
394 config SUNXI_DRAM_DDR2_V3S
395 bool "DDR2 found in V3s chip"
396 select SUNXI_DRAM_DDR2
397 depends on MACH_SUN8I_V3S
399 This option is only for the DDR2 memory chip which is co-packaged in
406 int "sunxi dram type"
407 depends on MACH_SUN8I_A83T
410 Set the dram type, 3: DDR3, 7: LPDDR3
413 int "sunxi dram clock speed"
414 default 792 if MACH_SUN9I
415 default 648 if MACH_SUN8I_R40
416 default 312 if MACH_SUN6I || MACH_SUN8I
417 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
419 default 672 if MACH_SUN50I
420 default 744 if MACH_SUN50I_H6
422 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
423 must be a multiple of 24. For the sun9i (A80), the tested values
424 (for DDR3-1600) are 312 to 792.
426 if MACH_SUN5I || MACH_SUN7I
428 int "sunxi mbus clock speed"
431 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
436 int "sunxi dram zq value"
437 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
438 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
439 default 127 if MACH_SUN7I
440 default 14779 if MACH_SUN8I_V3S
441 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
442 default 4145117 if MACH_SUN9I
443 default 3881915 if MACH_SUN50I
445 Set the dram zq value.
448 bool "sunxi dram odt enable"
449 default y if MACH_SUN8I_A23
450 default y if MACH_SUNXI_H3_H5
451 default y if MACH_SUN8I_R40
452 default y if MACH_SUN50I
453 default y if MACH_SUN50I_H6
455 Select this to enable dram odt (on die termination).
457 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
459 int "sunxi dram emr1 value"
460 default 0 if MACH_SUN4I
461 default 4 if MACH_SUN5I || MACH_SUN7I
463 Set the dram controller emr1 value.
466 hex "sunxi dram tpr3 value"
469 Set the dram controller tpr3 parameter. This parameter configures
470 the delay on the command lane and also phase shifts, which are
471 applied for sampling incoming read data. The default value 0
472 means that no phase/delay adjustments are necessary. Properly
473 configuring this parameter increases reliability at high DRAM
476 config DRAM_DQS_GATING_DELAY
477 hex "sunxi dram dqs_gating_delay value"
480 Set the dram controller dqs_gating_delay parmeter. Each byte
481 encodes the DQS gating delay for each byte lane. The delay
482 granularity is 1/4 cycle. For example, the value 0x05060606
483 means that the delay is 5 quarter-cycles for one lane (1.25
484 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
485 The default value 0 means autodetection. The results of hardware
486 autodetection are not very reliable and depend on the chip
487 temperature (sometimes producing different results on cold start
488 and warm reboot). But the accuracy of hardware autodetection
489 is usually good enough, unless running at really high DRAM
490 clocks speeds (up to 600MHz). If unsure, keep as 0.
493 prompt "sunxi dram timings"
494 default DRAM_TIMINGS_VENDOR_MAGIC
496 Select the timings of the DDR3 chips.
498 config DRAM_TIMINGS_VENDOR_MAGIC
499 bool "Magic vendor timings from Android"
501 The same DRAM timings as in the Allwinner boot0 bootloader.
503 config DRAM_TIMINGS_DDR3_1066F_1333H
504 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
506 Use the timings of the standard JEDEC DDR3-1066F speed bin for
507 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
508 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
509 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
510 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
511 that down binning to DDR3-1066F is supported (because DDR3-1066F
512 uses a bit faster timings than DDR3-1333H).
514 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
515 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
517 Use the timings of the slowest possible JEDEC speed bin for the
518 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
519 DDR3-800E, DDR3-1066G or DDR3-1333J.
526 config DRAM_ODT_CORRECTION
527 int "sunxi dram odt correction value"
530 Set the dram odt correction value (range -255 - 255). In allwinner
531 fex files, this option is found in bits 8-15 of the u32 odt_en variable
532 in the [dram] section. When bit 31 of the odt_en variable is set
533 then the correction is negative. Usually the value for this is 0.
537 default 1008000000 if MACH_SUN4I
538 default 1008000000 if MACH_SUN5I
539 default 1008000000 if MACH_SUN6I
540 default 912000000 if MACH_SUN7I
541 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
542 default 1008000000 if MACH_SUN8I
543 default 1008000000 if MACH_SUN9I
544 default 888000000 if MACH_SUN50I_H6
546 config SYS_CONFIG_NAME
547 default "sun4i" if MACH_SUN4I
548 default "sun5i" if MACH_SUN5I
549 default "sun6i" if MACH_SUN6I
550 default "sun7i" if MACH_SUN7I
551 default "sun8i" if MACH_SUN8I
552 default "sun9i" if MACH_SUN9I
553 default "sun50i" if MACH_SUN50I
554 default "sun50i" if MACH_SUN50I_H6
563 bool "UART0 on MicroSD breakout board"
566 Repurpose the SD card slot for getting access to the UART0 serial
567 console. Primarily useful only for low level u-boot debugging on
568 tablets, where normal UART0 is difficult to access and requires
569 device disassembly and/or soldering. As the SD card can't be used
570 at the same time, the system can be only booted in the FEL mode.
571 Only enable this if you really know what you are doing.
573 config OLD_SUNXI_KERNEL_COMPAT
574 bool "Enable workarounds for booting old kernels"
577 Set this to enable various workarounds for old kernels, this results in
578 sub-optimal settings for newer kernels, only enable if needed.
581 string "MAC power pin"
584 Set the pin used to power the MAC. This takes a string in the format
585 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
588 string "Card detect pin for mmc0"
589 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
592 Set the card detect pin for mmc0, leave empty to not use cd. This
593 takes a string in the format understood by sunxi_name_to_gpio, e.g.
594 PH1 for pin 1 of port H.
597 string "Card detect pin for mmc1"
600 See MMC0_CD_PIN help text.
603 string "Card detect pin for mmc2"
606 See MMC0_CD_PIN help text.
609 string "Card detect pin for mmc3"
612 See MMC0_CD_PIN help text.
615 string "Pins for mmc1"
618 Set the pins used for mmc1, when applicable. This takes a string in the
619 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
622 string "Pins for mmc2"
625 See MMC1_PINS help text.
628 string "Pins for mmc3"
631 See MMC1_PINS help text.
633 config MMC_SUNXI_SLOT_EXTRA
634 int "mmc extra slot number"
637 sunxi builds always enable mmc0, some boards also have a second sdcard
638 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
641 config INITIAL_USB_SCAN_DELAY
642 int "delay initial usb scan by x ms to allow builtin devices to init"
645 Some boards have on board usb devices which need longer than the
646 USB spec's 1 second to connect from board powerup. Set this config
647 option to a non 0 value to add an extra delay before the first usb
651 string "Vbus enable pin for usb0 (otg)"
654 Set the Vbus enable pin for usb0 (otg). This takes a string in the
655 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
658 string "Vbus detect pin for usb0 (otg)"
661 Set the Vbus detect pin for usb0 (otg). This takes a string in the
662 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
665 string "ID detect pin for usb0 (otg)"
668 Set the ID detect pin for usb0 (otg). This takes a string in the
669 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
672 string "Vbus enable pin for usb1 (ehci0)"
673 default "PH6" if MACH_SUN4I || MACH_SUN7I
674 default "PH27" if MACH_SUN6I
676 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
677 a string in the format understood by sunxi_name_to_gpio, e.g.
678 PH1 for pin 1 of port H.
681 string "Vbus enable pin for usb2 (ehci1)"
682 default "PH3" if MACH_SUN4I || MACH_SUN7I
683 default "PH24" if MACH_SUN6I
685 See USB1_VBUS_PIN help text.
688 string "Vbus enable pin for usb3 (ehci2)"
691 See USB1_VBUS_PIN help text.
694 bool "Enable I2C/TWI controller 0"
695 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
696 default n if MACH_SUN6I || MACH_SUN8I
699 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
700 its clock and setting up the bus. This is especially useful on devices
701 with slaves connected to the bus or with pins exposed through e.g. an
702 expansion port/header.
705 bool "Enable I2C/TWI controller 1"
709 See I2C0_ENABLE help text.
712 bool "Enable I2C/TWI controller 2"
716 See I2C0_ENABLE help text.
718 if MACH_SUN6I || MACH_SUN7I
720 bool "Enable I2C/TWI controller 3"
724 See I2C0_ENABLE help text.
729 bool "Enable the PRCM I2C/TWI controller"
730 # This is used for the pmic on H3
731 default y if SY8106A_POWER
734 Set this to y to enable the I2C controller which is part of the PRCM.
739 bool "Enable I2C/TWI controller 4"
743 See I2C0_ENABLE help text.
747 bool "Enable support for gpio-s on axp PMICs"
750 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
753 bool "Enable graphical uboot console on HDMI, LCD or VGA"
754 depends on !MACH_SUN8I_A83T
755 depends on !MACH_SUNXI_H3_H5
756 depends on !MACH_SUN8I_R40
757 depends on !MACH_SUN8I_V3S
758 depends on !MACH_SUN9I
759 depends on !MACH_SUN50I
760 depends on !MACH_SUN50I_H6
762 imply VIDEO_DT_SIMPLEFB
765 Say Y here to add support for using a cfb console on the HDMI, LCD
766 or VGA output found on most sunxi devices. See doc/README.video for
767 info on how to select the video output and mode.
770 bool "HDMI output support"
771 depends on VIDEO_SUNXI && !MACH_SUN8I
774 Say Y here to add support for outputting video over HDMI.
777 bool "VGA output support"
778 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
781 Say Y here to add support for outputting video over VGA.
783 config VIDEO_VGA_VIA_LCD
784 bool "VGA via LCD controller support"
785 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
788 Say Y here to add support for external DACs connected to the parallel
789 LCD interface driving a VGA connector, such as found on the
792 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
793 bool "Force sync active high for VGA via LCD controller support"
794 depends on VIDEO_VGA_VIA_LCD
797 Say Y here if you've a board which uses opendrain drivers for the vga
798 hsync and vsync signals. Opendrain drivers cannot generate steep enough
799 positive edges for a stable video output, so on boards with opendrain
800 drivers the sync signals must always be active high.
802 config VIDEO_VGA_EXTERNAL_DAC_EN
803 string "LCD panel power enable pin"
804 depends on VIDEO_VGA_VIA_LCD
807 Set the enable pin for the external VGA DAC. This takes a string in the
808 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
810 config VIDEO_COMPOSITE
811 bool "Composite video output support"
812 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
815 Say Y here to add support for outputting composite video.
817 config VIDEO_LCD_MODE
818 string "LCD panel timing details"
819 depends on VIDEO_SUNXI
822 LCD panel timing details string, leave empty if there is no LCD panel.
823 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
824 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
825 Also see: http://linux-sunxi.org/LCD
827 config VIDEO_LCD_DCLK_PHASE
828 int "LCD panel display clock phase"
829 depends on VIDEO_SUNXI || DM_VIDEO
832 Select LCD panel display clock phase shift, range 0-3.
834 config VIDEO_LCD_POWER
835 string "LCD panel power enable pin"
836 depends on VIDEO_SUNXI
839 Set the power enable pin for the LCD panel. This takes a string in the
840 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
842 config VIDEO_LCD_RESET
843 string "LCD panel reset pin"
844 depends on VIDEO_SUNXI
847 Set the reset pin for the LCD panel. This takes a string in the format
848 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
850 config VIDEO_LCD_BL_EN
851 string "LCD panel backlight enable pin"
852 depends on VIDEO_SUNXI
855 Set the backlight enable pin for the LCD panel. This takes a string in the
856 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
859 config VIDEO_LCD_BL_PWM
860 string "LCD panel backlight pwm pin"
861 depends on VIDEO_SUNXI
864 Set the backlight pwm pin for the LCD panel. This takes a string in the
865 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
867 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
868 bool "LCD panel backlight pwm is inverted"
869 depends on VIDEO_SUNXI
872 Set this if the backlight pwm output is active low.
874 config VIDEO_LCD_PANEL_I2C
875 bool "LCD panel needs to be configured via i2c"
876 depends on VIDEO_SUNXI
880 Say y here if the LCD panel needs to be configured via i2c. This
881 will add a bitbang i2c controller using gpios to talk to the LCD.
883 config VIDEO_LCD_PANEL_I2C_SDA
884 string "LCD panel i2c interface SDA pin"
885 depends on VIDEO_LCD_PANEL_I2C
888 Set the SDA pin for the LCD i2c interface. This takes a string in the
889 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
891 config VIDEO_LCD_PANEL_I2C_SCL
892 string "LCD panel i2c interface SCL pin"
893 depends on VIDEO_LCD_PANEL_I2C
896 Set the SCL pin for the LCD i2c interface. This takes a string in the
897 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
900 # Note only one of these may be selected at a time! But hidden choices are
901 # not supported by Kconfig
902 config VIDEO_LCD_IF_PARALLEL
905 config VIDEO_LCD_IF_LVDS
913 bool "Display Engine 2 video driver"
917 imply VIDEO_DT_SIMPLEFB
920 Say y here if you want to build DE2 video driver which is present on
921 newer SoCs. Currently only HDMI output is supported.
925 prompt "LCD panel support"
926 depends on VIDEO_SUNXI
928 Select which type of LCD panel to support.
930 config VIDEO_LCD_PANEL_PARALLEL
931 bool "Generic parallel interface LCD panel"
932 select VIDEO_LCD_IF_PARALLEL
934 config VIDEO_LCD_PANEL_LVDS
935 bool "Generic lvds interface LCD panel"
936 select VIDEO_LCD_IF_LVDS
938 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
939 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
940 select VIDEO_LCD_SSD2828
941 select VIDEO_LCD_IF_PARALLEL
943 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
945 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
946 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
947 select VIDEO_LCD_ANX9804
948 select VIDEO_LCD_IF_PARALLEL
949 select VIDEO_LCD_PANEL_I2C
951 Select this for eDP LCD panels with 4 lanes running at 1.62G,
952 connected via an ANX9804 bridge chip.
954 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
955 bool "Hitachi tx18d42vm LCD panel"
956 select VIDEO_LCD_HITACHI_TX18D42VM
957 select VIDEO_LCD_IF_LVDS
959 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
961 config VIDEO_LCD_TL059WV5C0
962 bool "tl059wv5c0 LCD panel"
963 select VIDEO_LCD_PANEL_I2C
964 select VIDEO_LCD_IF_PARALLEL
966 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
967 Aigo M60/M608/M606 tablets.
972 string "SATA power pin"
975 Set the pins used to power the SATA. This takes a string in the
976 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
980 int "GMAC Transmit Clock Delay Chain"
983 Set the GMAC Transmit Clock Delay Chain value.
985 config SPL_STACK_R_ADDR
986 default 0x4fe00000 if MACH_SUN4I
987 default 0x4fe00000 if MACH_SUN5I
988 default 0x4fe00000 if MACH_SUN6I
989 default 0x4fe00000 if MACH_SUN7I
990 default 0x4fe00000 if MACH_SUN8I
991 default 0x2fe00000 if MACH_SUN9I
992 default 0x4fe00000 if MACH_SUN50I
993 default 0x4fe00000 if MACH_SUN50I_H6
996 bool "Support for SPI Flash on Allwinner SoCs in SPL"
997 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
999 Enable support for SPI Flash. This option allows SPL to read from
1000 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1001 not need any extra configuration.
1003 config PINE64_DT_SELECTION
1004 bool "Enable Pine64 device tree selection code"
1005 depends on MACH_SUN50I
1007 The original Pine A64 and Pine A64+ are similar but different
1008 boards and can be differed by the DRAM size. Pine A64 has
1009 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1010 option, the device tree selection code specific to Pine64 which
1011 utilizes the DRAM size will be enabled.