4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Support for the PRCM (Power/Reset/Clock Management) unit available
15 config SUNXI_HIGH_SRAM
19 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
20 with the first SRAM region being located at address 0.
21 Some newer SoCs map the boot ROM at address 0 instead and move the
22 SRAM to 64KB, just behind the mask ROM.
23 Chips using the latter setup are supposed to select this option to
24 adjust the addresses accordingly.
26 # Note only one of these may be selected at a time! But hidden choices are
27 # not supported by Kconfig
28 config SUNXI_GEN_SUN4I
31 Select this for sunxi SoCs which have resets and clocks set up
32 as the original A10 (mach-sun4i).
34 config SUNXI_GEN_SUN6I
37 Select this for sunxi SoCs which have sun6i like periphery, like
38 separate ahb reset control registers, custom pmic bus, new style
44 Select this for sunxi SoCs which uses a DRAM controller like the
45 DesignWare controller used in H3, mainly SoCs after H3, which do
46 not have official open-source DRAM initialization code, but can
47 use modified H3 DRAM initialization code.
50 config SUNXI_DRAM_DW_16BIT
53 Select this for sunxi SoCs with DesignWare DRAM controller and
54 have only 16-bit memory buswidth.
56 config SUNXI_DRAM_DW_32BIT
59 Select this for sunxi SoCs with DesignWare DRAM controller with
60 32-bit memory buswidth.
63 config MACH_SUNXI_H3_H5
68 select SUNXI_DRAM_DW_32BIT
69 select SUNXI_GEN_SUN6I
73 prompt "Sunxi SoC Variant"
77 bool "sun4i (Allwinner A10)"
79 select ARM_CORTEX_CPU_IS_UP
80 select SUNXI_GEN_SUN4I
84 bool "sun5i (Allwinner A13)"
86 select ARM_CORTEX_CPU_IS_UP
87 select SUNXI_GEN_SUN4I
89 imply CONS_INDEX_2 if !DM_SERIAL
92 bool "sun6i (Allwinner A31)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN6I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
103 bool "sun7i (Allwinner A20)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
108 select SUNXI_GEN_SUN4I
110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
112 config MACH_SUN8I_A23
113 bool "sun8i (Allwinner A23)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 imply CONS_INDEX_5 if !DM_SERIAL
123 config MACH_SUN8I_A33
124 bool "sun8i (Allwinner A33)"
126 select CPU_V7_HAS_NONSEC
127 select CPU_V7_HAS_VIRT
128 select ARCH_SUPPORT_PSCI
129 select SUNXI_GEN_SUN6I
131 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
132 imply CONS_INDEX_5 if !DM_SERIAL
134 config MACH_SUN8I_A83T
135 bool "sun8i (Allwinner A83T)"
137 select SUNXI_GEN_SUN6I
138 select MMC_SUNXI_HAS_NEW_MODE
142 bool "sun8i (Allwinner H3)"
144 select CPU_V7_HAS_NONSEC
145 select CPU_V7_HAS_VIRT
146 select ARCH_SUPPORT_PSCI
147 select MACH_SUNXI_H3_H5
148 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
150 config MACH_SUN8I_R40
151 bool "sun8i (Allwinner R40)"
153 select CPU_V7_HAS_NONSEC
154 select CPU_V7_HAS_VIRT
155 select ARCH_SUPPORT_PSCI
156 select SUNXI_GEN_SUN6I
159 select SUNXI_DRAM_DW_32BIT
161 config MACH_SUN8I_V3S
162 bool "sun8i (Allwinner V3s)"
164 select CPU_V7_HAS_NONSEC
165 select CPU_V7_HAS_VIRT
166 select ARCH_SUPPORT_PSCI
167 select SUNXI_GEN_SUN6I
169 select SUNXI_DRAM_DW_16BIT
171 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
174 bool "sun9i (Allwinner A80)"
176 select SUNXI_HIGH_SRAM
177 select SUNXI_GEN_SUN6I
181 bool "sun50i (Allwinner A64)"
185 select SUNXI_GEN_SUN6I
186 select SUNXI_HIGH_SRAM
189 select SUNXI_DRAM_DW_32BIT
193 config MACH_SUN50I_H5
194 bool "sun50i (Allwinner H5)"
196 select MACH_SUNXI_H3_H5
197 select SUNXI_HIGH_SRAM
203 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
206 default y if MACH_SUN8I_A23
207 default y if MACH_SUN8I_A33
208 default y if MACH_SUN8I_A83T
209 default y if MACH_SUNXI_H3_H5
210 default y if MACH_SUN8I_R40
211 default y if MACH_SUN8I_V3S
213 config RESERVE_ALLWINNER_BOOT0_HEADER
214 bool "reserve space for Allwinner boot0 header"
215 select ENABLE_ARM_SOC_BOOT0_HOOK
217 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
218 filled with magic values post build. The Allwinner provided boot0
219 blob relies on this information to load and execute U-Boot.
220 Only needed on 64-bit Allwinner boards so far when using boot0.
222 config ARM_BOOT_HOOK_RMR
226 select ENABLE_ARM_SOC_BOOT0_HOOK
228 Insert some ARM32 code at the very beginning of the U-Boot binary
229 which uses an RMR register write to bring the core into AArch64 mode.
230 The very first instruction acts as a switch, since it's carefully
231 chosen to be a NOP in one mode and a branch in the other, so the
232 code would only be executed if not already in AArch64.
233 This allows both the SPL and the U-Boot proper to be entered in
234 either mode and switch to AArch64 if needed.
237 config SUNXI_DRAM_DDR3
240 config SUNXI_DRAM_DDR2
243 config SUNXI_DRAM_LPDDR3
247 prompt "DRAM Type and Timing"
248 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
249 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
251 config SUNXI_DRAM_DDR3_1333
253 select SUNXI_DRAM_DDR3
254 depends on !MACH_SUN8I_V3S
256 This option is the original only supported memory type, which suits
257 many H3/H5/A64 boards available now.
259 config SUNXI_DRAM_LPDDR3_STOCK
260 bool "LPDDR3 with Allwinner stock configuration"
261 select SUNXI_DRAM_LPDDR3
263 This option is the LPDDR3 timing used by the stock boot0 by
266 config SUNXI_DRAM_DDR2_V3S
267 bool "DDR2 found in V3s chip"
268 select SUNXI_DRAM_DDR2
269 depends on MACH_SUN8I_V3S
271 This option is only for the DDR2 memory chip which is co-packaged in
278 int "sunxi dram type"
279 depends on MACH_SUN8I_A83T
282 Set the dram type, 3: DDR3, 7: LPDDR3
285 int "sunxi dram clock speed"
286 default 792 if MACH_SUN9I
287 default 648 if MACH_SUN8I_R40
288 default 312 if MACH_SUN6I || MACH_SUN8I
289 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
291 default 672 if MACH_SUN50I
293 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
294 must be a multiple of 24. For the sun9i (A80), the tested values
295 (for DDR3-1600) are 312 to 792.
297 if MACH_SUN5I || MACH_SUN7I
299 int "sunxi mbus clock speed"
302 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
307 int "sunxi dram zq value"
308 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
309 default 127 if MACH_SUN7I
310 default 14779 if MACH_SUN8I_V3S
311 default 3881979 if MACH_SUN8I_R40
312 default 4145117 if MACH_SUN9I
313 default 3881915 if MACH_SUN50I
315 Set the dram zq value.
318 bool "sunxi dram odt enable"
319 default n if !MACH_SUN8I_A23
320 default y if MACH_SUN8I_A23
321 default y if MACH_SUN8I_R40
322 default y if MACH_SUN50I
324 Select this to enable dram odt (on die termination).
326 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
328 int "sunxi dram emr1 value"
329 default 0 if MACH_SUN4I
330 default 4 if MACH_SUN5I || MACH_SUN7I
332 Set the dram controller emr1 value.
335 hex "sunxi dram tpr3 value"
338 Set the dram controller tpr3 parameter. This parameter configures
339 the delay on the command lane and also phase shifts, which are
340 applied for sampling incoming read data. The default value 0
341 means that no phase/delay adjustments are necessary. Properly
342 configuring this parameter increases reliability at high DRAM
345 config DRAM_DQS_GATING_DELAY
346 hex "sunxi dram dqs_gating_delay value"
349 Set the dram controller dqs_gating_delay parmeter. Each byte
350 encodes the DQS gating delay for each byte lane. The delay
351 granularity is 1/4 cycle. For example, the value 0x05060606
352 means that the delay is 5 quarter-cycles for one lane (1.25
353 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
354 The default value 0 means autodetection. The results of hardware
355 autodetection are not very reliable and depend on the chip
356 temperature (sometimes producing different results on cold start
357 and warm reboot). But the accuracy of hardware autodetection
358 is usually good enough, unless running at really high DRAM
359 clocks speeds (up to 600MHz). If unsure, keep as 0.
362 prompt "sunxi dram timings"
363 default DRAM_TIMINGS_VENDOR_MAGIC
365 Select the timings of the DDR3 chips.
367 config DRAM_TIMINGS_VENDOR_MAGIC
368 bool "Magic vendor timings from Android"
370 The same DRAM timings as in the Allwinner boot0 bootloader.
372 config DRAM_TIMINGS_DDR3_1066F_1333H
373 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
375 Use the timings of the standard JEDEC DDR3-1066F speed bin for
376 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
377 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
378 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
379 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
380 that down binning to DDR3-1066F is supported (because DDR3-1066F
381 uses a bit faster timings than DDR3-1333H).
383 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
384 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
386 Use the timings of the slowest possible JEDEC speed bin for the
387 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
388 DDR3-800E, DDR3-1066G or DDR3-1333J.
395 config DRAM_ODT_CORRECTION
396 int "sunxi dram odt correction value"
399 Set the dram odt correction value (range -255 - 255). In allwinner
400 fex files, this option is found in bits 8-15 of the u32 odt_en variable
401 in the [dram] section. When bit 31 of the odt_en variable is set
402 then the correction is negative. Usually the value for this is 0.
406 default 1008000000 if MACH_SUN4I
407 default 1008000000 if MACH_SUN5I
408 default 1008000000 if MACH_SUN6I
409 default 912000000 if MACH_SUN7I
410 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
411 default 1008000000 if MACH_SUN8I
412 default 1008000000 if MACH_SUN9I
414 config SYS_CONFIG_NAME
415 default "sun4i" if MACH_SUN4I
416 default "sun5i" if MACH_SUN5I
417 default "sun6i" if MACH_SUN6I
418 default "sun7i" if MACH_SUN7I
419 default "sun8i" if MACH_SUN8I
420 default "sun9i" if MACH_SUN9I
421 default "sun50i" if MACH_SUN50I
430 bool "UART0 on MicroSD breakout board"
433 Repurpose the SD card slot for getting access to the UART0 serial
434 console. Primarily useful only for low level u-boot debugging on
435 tablets, where normal UART0 is difficult to access and requires
436 device disassembly and/or soldering. As the SD card can't be used
437 at the same time, the system can be only booted in the FEL mode.
438 Only enable this if you really know what you are doing.
440 config OLD_SUNXI_KERNEL_COMPAT
441 bool "Enable workarounds for booting old kernels"
444 Set this to enable various workarounds for old kernels, this results in
445 sub-optimal settings for newer kernels, only enable if needed.
448 string "MAC power pin"
451 Set the pin used to power the MAC. This takes a string in the format
452 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
455 string "Card detect pin for mmc0"
456 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
459 Set the card detect pin for mmc0, leave empty to not use cd. This
460 takes a string in the format understood by sunxi_name_to_gpio, e.g.
461 PH1 for pin 1 of port H.
464 string "Card detect pin for mmc1"
467 See MMC0_CD_PIN help text.
470 string "Card detect pin for mmc2"
473 See MMC0_CD_PIN help text.
476 string "Card detect pin for mmc3"
479 See MMC0_CD_PIN help text.
482 string "Pins for mmc1"
485 Set the pins used for mmc1, when applicable. This takes a string in the
486 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
489 string "Pins for mmc2"
492 See MMC1_PINS help text.
495 string "Pins for mmc3"
498 See MMC1_PINS help text.
500 config MMC_SUNXI_SLOT_EXTRA
501 int "mmc extra slot number"
504 sunxi builds always enable mmc0, some boards also have a second sdcard
505 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
508 config INITIAL_USB_SCAN_DELAY
509 int "delay initial usb scan by x ms to allow builtin devices to init"
512 Some boards have on board usb devices which need longer than the
513 USB spec's 1 second to connect from board powerup. Set this config
514 option to a non 0 value to add an extra delay before the first usb
518 string "Vbus enable pin for usb0 (otg)"
521 Set the Vbus enable pin for usb0 (otg). This takes a string in the
522 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
525 string "Vbus detect pin for usb0 (otg)"
528 Set the Vbus detect pin for usb0 (otg). This takes a string in the
529 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
532 string "ID detect pin for usb0 (otg)"
535 Set the ID detect pin for usb0 (otg). This takes a string in the
536 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
539 string "Vbus enable pin for usb1 (ehci0)"
540 default "PH6" if MACH_SUN4I || MACH_SUN7I
541 default "PH27" if MACH_SUN6I
543 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
544 a string in the format understood by sunxi_name_to_gpio, e.g.
545 PH1 for pin 1 of port H.
548 string "Vbus enable pin for usb2 (ehci1)"
549 default "PH3" if MACH_SUN4I || MACH_SUN7I
550 default "PH24" if MACH_SUN6I
552 See USB1_VBUS_PIN help text.
555 string "Vbus enable pin for usb3 (ehci2)"
558 See USB1_VBUS_PIN help text.
561 bool "Enable I2C/TWI controller 0"
562 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
563 default n if MACH_SUN6I || MACH_SUN8I
566 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
567 its clock and setting up the bus. This is especially useful on devices
568 with slaves connected to the bus or with pins exposed through e.g. an
569 expansion port/header.
572 bool "Enable I2C/TWI controller 1"
576 See I2C0_ENABLE help text.
579 bool "Enable I2C/TWI controller 2"
583 See I2C0_ENABLE help text.
585 if MACH_SUN6I || MACH_SUN7I
587 bool "Enable I2C/TWI controller 3"
591 See I2C0_ENABLE help text.
596 bool "Enable the PRCM I2C/TWI controller"
597 # This is used for the pmic on H3
598 default y if SY8106A_POWER
601 Set this to y to enable the I2C controller which is part of the PRCM.
606 bool "Enable I2C/TWI controller 4"
610 See I2C0_ENABLE help text.
614 bool "Enable support for gpio-s on axp PMICs"
617 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
620 bool "Enable graphical uboot console on HDMI, LCD or VGA"
621 depends on !MACH_SUN8I_A83T
622 depends on !MACH_SUNXI_H3_H5
623 depends on !MACH_SUN8I_R40
624 depends on !MACH_SUN8I_V3S
625 depends on !MACH_SUN9I
626 depends on !MACH_SUN50I
628 imply VIDEO_DT_SIMPLEFB
631 Say Y here to add support for using a cfb console on the HDMI, LCD
632 or VGA output found on most sunxi devices. See doc/README.video for
633 info on how to select the video output and mode.
636 bool "HDMI output support"
637 depends on VIDEO_SUNXI && !MACH_SUN8I
640 Say Y here to add support for outputting video over HDMI.
643 bool "VGA output support"
644 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
647 Say Y here to add support for outputting video over VGA.
649 config VIDEO_VGA_VIA_LCD
650 bool "VGA via LCD controller support"
651 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
654 Say Y here to add support for external DACs connected to the parallel
655 LCD interface driving a VGA connector, such as found on the
658 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
659 bool "Force sync active high for VGA via LCD controller support"
660 depends on VIDEO_VGA_VIA_LCD
663 Say Y here if you've a board which uses opendrain drivers for the vga
664 hsync and vsync signals. Opendrain drivers cannot generate steep enough
665 positive edges for a stable video output, so on boards with opendrain
666 drivers the sync signals must always be active high.
668 config VIDEO_VGA_EXTERNAL_DAC_EN
669 string "LCD panel power enable pin"
670 depends on VIDEO_VGA_VIA_LCD
673 Set the enable pin for the external VGA DAC. This takes a string in the
674 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
676 config VIDEO_COMPOSITE
677 bool "Composite video output support"
678 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
681 Say Y here to add support for outputting composite video.
683 config VIDEO_LCD_MODE
684 string "LCD panel timing details"
685 depends on VIDEO_SUNXI
688 LCD panel timing details string, leave empty if there is no LCD panel.
689 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
690 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
691 Also see: http://linux-sunxi.org/LCD
693 config VIDEO_LCD_DCLK_PHASE
694 int "LCD panel display clock phase"
695 depends on VIDEO_SUNXI || DM_VIDEO
698 Select LCD panel display clock phase shift, range 0-3.
700 config VIDEO_LCD_POWER
701 string "LCD panel power enable pin"
702 depends on VIDEO_SUNXI
705 Set the power enable pin for the LCD panel. This takes a string in the
706 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
708 config VIDEO_LCD_RESET
709 string "LCD panel reset pin"
710 depends on VIDEO_SUNXI
713 Set the reset pin for the LCD panel. This takes a string in the format
714 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
716 config VIDEO_LCD_BL_EN
717 string "LCD panel backlight enable pin"
718 depends on VIDEO_SUNXI
721 Set the backlight enable pin for the LCD panel. This takes a string in the
722 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
725 config VIDEO_LCD_BL_PWM
726 string "LCD panel backlight pwm pin"
727 depends on VIDEO_SUNXI
730 Set the backlight pwm pin for the LCD panel. This takes a string in the
731 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
733 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
734 bool "LCD panel backlight pwm is inverted"
735 depends on VIDEO_SUNXI
738 Set this if the backlight pwm output is active low.
740 config VIDEO_LCD_PANEL_I2C
741 bool "LCD panel needs to be configured via i2c"
742 depends on VIDEO_SUNXI
746 Say y here if the LCD panel needs to be configured via i2c. This
747 will add a bitbang i2c controller using gpios to talk to the LCD.
749 config VIDEO_LCD_PANEL_I2C_SDA
750 string "LCD panel i2c interface SDA pin"
751 depends on VIDEO_LCD_PANEL_I2C
754 Set the SDA pin for the LCD i2c interface. This takes a string in the
755 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
757 config VIDEO_LCD_PANEL_I2C_SCL
758 string "LCD panel i2c interface SCL pin"
759 depends on VIDEO_LCD_PANEL_I2C
762 Set the SCL pin for the LCD i2c interface. This takes a string in the
763 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
766 # Note only one of these may be selected at a time! But hidden choices are
767 # not supported by Kconfig
768 config VIDEO_LCD_IF_PARALLEL
771 config VIDEO_LCD_IF_LVDS
779 bool "Display Engine 2 video driver"
783 imply VIDEO_DT_SIMPLEFB
786 Say y here if you want to build DE2 video driver which is present on
787 newer SoCs. Currently only HDMI output is supported.
791 prompt "LCD panel support"
792 depends on VIDEO_SUNXI
794 Select which type of LCD panel to support.
796 config VIDEO_LCD_PANEL_PARALLEL
797 bool "Generic parallel interface LCD panel"
798 select VIDEO_LCD_IF_PARALLEL
800 config VIDEO_LCD_PANEL_LVDS
801 bool "Generic lvds interface LCD panel"
802 select VIDEO_LCD_IF_LVDS
804 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
805 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
806 select VIDEO_LCD_SSD2828
807 select VIDEO_LCD_IF_PARALLEL
809 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
811 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
812 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
813 select VIDEO_LCD_ANX9804
814 select VIDEO_LCD_IF_PARALLEL
815 select VIDEO_LCD_PANEL_I2C
817 Select this for eDP LCD panels with 4 lanes running at 1.62G,
818 connected via an ANX9804 bridge chip.
820 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
821 bool "Hitachi tx18d42vm LCD panel"
822 select VIDEO_LCD_HITACHI_TX18D42VM
823 select VIDEO_LCD_IF_LVDS
825 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
827 config VIDEO_LCD_TL059WV5C0
828 bool "tl059wv5c0 LCD panel"
829 select VIDEO_LCD_PANEL_I2C
830 select VIDEO_LCD_IF_PARALLEL
832 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
833 Aigo M60/M608/M606 tablets.
838 string "SATA power pin"
841 Set the pins used to power the SATA. This takes a string in the
842 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
846 int "GMAC Transmit Clock Delay Chain"
849 Set the GMAC Transmit Clock Delay Chain value.
851 config SPL_STACK_R_ADDR
852 default 0x4fe00000 if MACH_SUN4I
853 default 0x4fe00000 if MACH_SUN5I
854 default 0x4fe00000 if MACH_SUN6I
855 default 0x4fe00000 if MACH_SUN7I
856 default 0x4fe00000 if MACH_SUN8I
857 default 0x2fe00000 if MACH_SUN9I
858 default 0x4fe00000 if MACH_SUN50I
861 bool "Support for SPI Flash on Allwinner SoCs in SPL"
862 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
864 Enable support for SPI Flash. This option allows SPL to read from
865 sunxi SPI Flash. It uses the same method as the boot ROM, so does
866 not need any extra configuration.