4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
159 select SUNXI_GEN_SUN4I
163 bool "sun5i (Allwinner A13)"
165 select ARM_CORTEX_CPU_IS_UP
168 select SUNXI_GEN_SUN4I
170 imply CONS_INDEX_2 if !DM_SERIAL
173 bool "sun6i (Allwinner A31)"
175 select CPU_V7_HAS_NONSEC
176 select CPU_V7_HAS_VIRT
177 select ARCH_SUPPORT_PSCI
182 select SUNXI_GEN_SUN6I
184 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187 bool "sun7i (Allwinner A20)"
189 select CPU_V7_HAS_NONSEC
190 select CPU_V7_HAS_VIRT
191 select ARCH_SUPPORT_PSCI
194 select SUNXI_GEN_SUN4I
196 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
198 config MACH_SUN8I_A23
199 bool "sun8i (Allwinner A23)"
201 select CPU_V7_HAS_NONSEC
202 select CPU_V7_HAS_VIRT
203 select ARCH_SUPPORT_PSCI
204 select DRAM_SUN8I_A23
206 select SUNXI_GEN_SUN6I
208 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
209 imply CONS_INDEX_5 if !DM_SERIAL
211 config MACH_SUN8I_A33
212 bool "sun8i (Allwinner A33)"
214 select CPU_V7_HAS_NONSEC
215 select CPU_V7_HAS_VIRT
216 select ARCH_SUPPORT_PSCI
217 select DRAM_SUN8I_A33
219 select SUNXI_GEN_SUN6I
221 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
222 imply CONS_INDEX_5 if !DM_SERIAL
224 config MACH_SUN8I_A83T
225 bool "sun8i (Allwinner A83T)"
227 select DRAM_SUN8I_A83T
229 select SUNXI_GEN_SUN6I
230 select MMC_SUNXI_HAS_NEW_MODE
231 select MMC_SUNXI_HAS_MODE_SWITCH
235 bool "sun8i (Allwinner H3)"
237 select CPU_V7_HAS_NONSEC
238 select CPU_V7_HAS_VIRT
239 select ARCH_SUPPORT_PSCI
240 select MACH_SUNXI_H3_H5
241 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
243 config MACH_SUN8I_R40
244 bool "sun8i (Allwinner R40)"
246 select CPU_V7_HAS_NONSEC
247 select CPU_V7_HAS_VIRT
248 select ARCH_SUPPORT_PSCI
249 select SUNXI_GEN_SUN6I
252 select SUNXI_DRAM_DW_32BIT
254 config MACH_SUN8I_V3S
255 bool "sun8i (Allwinner V3s)"
257 select CPU_V7_HAS_NONSEC
258 select CPU_V7_HAS_VIRT
259 select ARCH_SUPPORT_PSCI
260 select SUNXI_GEN_SUN6I
262 select SUNXI_DRAM_DW_16BIT
264 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
267 bool "sun9i (Allwinner A80)"
271 select SUNXI_GEN_SUN6I
276 bool "sun50i (Allwinner A64)"
282 select SUNXI_GEN_SUN6I
283 select MMC_SUNXI_HAS_NEW_MODE
286 select SUNXI_DRAM_DW_32BIT
289 select SUNXI_A64_TIMER_ERRATUM
291 config MACH_SUN50I_H5
292 bool "sun50i (Allwinner H5)"
294 select MACH_SUNXI_H3_H5
298 config MACH_SUN50I_H6
299 bool "sun50i (Allwinner H6)"
305 select DRAM_SUN50I_H6
309 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
314 default y if MACH_SUN8I_A23
315 default y if MACH_SUN8I_A33
316 default y if MACH_SUN8I_A83T
317 default y if MACH_SUNXI_H3_H5
318 default y if MACH_SUN8I_R40
319 default y if MACH_SUN8I_V3S
321 config RESERVE_ALLWINNER_BOOT0_HEADER
322 bool "reserve space for Allwinner boot0 header"
323 select ENABLE_ARM_SOC_BOOT0_HOOK
325 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
326 filled with magic values post build. The Allwinner provided boot0
327 blob relies on this information to load and execute U-Boot.
328 Only needed on 64-bit Allwinner boards so far when using boot0.
330 config ARM_BOOT_HOOK_RMR
334 select ENABLE_ARM_SOC_BOOT0_HOOK
336 Insert some ARM32 code at the very beginning of the U-Boot binary
337 which uses an RMR register write to bring the core into AArch64 mode.
338 The very first instruction acts as a switch, since it's carefully
339 chosen to be a NOP in one mode and a branch in the other, so the
340 code would only be executed if not already in AArch64.
341 This allows both the SPL and the U-Boot proper to be entered in
342 either mode and switch to AArch64 if needed.
344 if SUNXI_DRAM_DW || DRAM_SUN50I_H6
345 config SUNXI_DRAM_DDR3
348 config SUNXI_DRAM_DDR2
351 config SUNXI_DRAM_LPDDR3
355 prompt "DRAM Type and Timing"
356 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
357 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
359 config SUNXI_DRAM_DDR3_1333
361 select SUNXI_DRAM_DDR3
362 depends on !MACH_SUN8I_V3S
364 This option is the original only supported memory type, which suits
365 many H3/H5/A64 boards available now.
367 config SUNXI_DRAM_LPDDR3_STOCK
368 bool "LPDDR3 with Allwinner stock configuration"
369 select SUNXI_DRAM_LPDDR3
371 This option is the LPDDR3 timing used by the stock boot0 by
374 config SUNXI_DRAM_H6_LPDDR3
375 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
376 select SUNXI_DRAM_LPDDR3
377 depends on DRAM_SUN50I_H6
379 This option is the LPDDR3 timing used by the stock boot0 by
382 config SUNXI_DRAM_H6_DDR3_1333
383 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
384 select SUNXI_DRAM_DDR3
385 depends on DRAM_SUN50I_H6
387 This option is the DDR3 timing used by the boot0 on H6 TV boxes
388 which use a DDR3-1333 timing.
390 config SUNXI_DRAM_DDR2_V3S
391 bool "DDR2 found in V3s chip"
392 select SUNXI_DRAM_DDR2
393 depends on MACH_SUN8I_V3S
395 This option is only for the DDR2 memory chip which is co-packaged in
402 int "sunxi dram type"
403 depends on MACH_SUN8I_A83T
406 Set the dram type, 3: DDR3, 7: LPDDR3
409 int "sunxi dram clock speed"
410 default 792 if MACH_SUN9I
411 default 648 if MACH_SUN8I_R40
412 default 312 if MACH_SUN6I || MACH_SUN8I
413 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
415 default 672 if MACH_SUN50I
416 default 744 if MACH_SUN50I_H6
418 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
419 must be a multiple of 24. For the sun9i (A80), the tested values
420 (for DDR3-1600) are 312 to 792.
422 if MACH_SUN5I || MACH_SUN7I
424 int "sunxi mbus clock speed"
427 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
432 int "sunxi dram zq value"
433 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
434 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
435 default 127 if MACH_SUN7I
436 default 14779 if MACH_SUN8I_V3S
437 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
438 default 4145117 if MACH_SUN9I
439 default 3881915 if MACH_SUN50I
441 Set the dram zq value.
444 bool "sunxi dram odt enable"
445 default y if MACH_SUN8I_A23
446 default y if MACH_SUNXI_H3_H5
447 default y if MACH_SUN8I_R40
448 default y if MACH_SUN50I
449 default y if MACH_SUN50I_H6
451 Select this to enable dram odt (on die termination).
453 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
455 int "sunxi dram emr1 value"
456 default 0 if MACH_SUN4I
457 default 4 if MACH_SUN5I || MACH_SUN7I
459 Set the dram controller emr1 value.
462 hex "sunxi dram tpr3 value"
465 Set the dram controller tpr3 parameter. This parameter configures
466 the delay on the command lane and also phase shifts, which are
467 applied for sampling incoming read data. The default value 0
468 means that no phase/delay adjustments are necessary. Properly
469 configuring this parameter increases reliability at high DRAM
472 config DRAM_DQS_GATING_DELAY
473 hex "sunxi dram dqs_gating_delay value"
476 Set the dram controller dqs_gating_delay parmeter. Each byte
477 encodes the DQS gating delay for each byte lane. The delay
478 granularity is 1/4 cycle. For example, the value 0x05060606
479 means that the delay is 5 quarter-cycles for one lane (1.25
480 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
481 The default value 0 means autodetection. The results of hardware
482 autodetection are not very reliable and depend on the chip
483 temperature (sometimes producing different results on cold start
484 and warm reboot). But the accuracy of hardware autodetection
485 is usually good enough, unless running at really high DRAM
486 clocks speeds (up to 600MHz). If unsure, keep as 0.
489 prompt "sunxi dram timings"
490 default DRAM_TIMINGS_VENDOR_MAGIC
492 Select the timings of the DDR3 chips.
494 config DRAM_TIMINGS_VENDOR_MAGIC
495 bool "Magic vendor timings from Android"
497 The same DRAM timings as in the Allwinner boot0 bootloader.
499 config DRAM_TIMINGS_DDR3_1066F_1333H
500 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
502 Use the timings of the standard JEDEC DDR3-1066F speed bin for
503 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
504 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
505 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
506 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
507 that down binning to DDR3-1066F is supported (because DDR3-1066F
508 uses a bit faster timings than DDR3-1333H).
510 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
511 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
513 Use the timings of the slowest possible JEDEC speed bin for the
514 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
515 DDR3-800E, DDR3-1066G or DDR3-1333J.
522 config DRAM_ODT_CORRECTION
523 int "sunxi dram odt correction value"
526 Set the dram odt correction value (range -255 - 255). In allwinner
527 fex files, this option is found in bits 8-15 of the u32 odt_en variable
528 in the [dram] section. When bit 31 of the odt_en variable is set
529 then the correction is negative. Usually the value for this is 0.
533 default 1008000000 if MACH_SUN4I
534 default 1008000000 if MACH_SUN5I
535 default 1008000000 if MACH_SUN6I
536 default 912000000 if MACH_SUN7I
537 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
538 default 1008000000 if MACH_SUN8I
539 default 1008000000 if MACH_SUN9I
540 default 888000000 if MACH_SUN50I_H6
542 config SYS_CONFIG_NAME
543 default "sun4i" if MACH_SUN4I
544 default "sun5i" if MACH_SUN5I
545 default "sun6i" if MACH_SUN6I
546 default "sun7i" if MACH_SUN7I
547 default "sun8i" if MACH_SUN8I
548 default "sun9i" if MACH_SUN9I
549 default "sun50i" if MACH_SUN50I
550 default "sun50i" if MACH_SUN50I_H6
559 bool "UART0 on MicroSD breakout board"
562 Repurpose the SD card slot for getting access to the UART0 serial
563 console. Primarily useful only for low level u-boot debugging on
564 tablets, where normal UART0 is difficult to access and requires
565 device disassembly and/or soldering. As the SD card can't be used
566 at the same time, the system can be only booted in the FEL mode.
567 Only enable this if you really know what you are doing.
569 config OLD_SUNXI_KERNEL_COMPAT
570 bool "Enable workarounds for booting old kernels"
573 Set this to enable various workarounds for old kernels, this results in
574 sub-optimal settings for newer kernels, only enable if needed.
577 string "MAC power pin"
580 Set the pin used to power the MAC. This takes a string in the format
581 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
584 string "Card detect pin for mmc0"
585 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
588 Set the card detect pin for mmc0, leave empty to not use cd. This
589 takes a string in the format understood by sunxi_name_to_gpio, e.g.
590 PH1 for pin 1 of port H.
593 string "Card detect pin for mmc1"
596 See MMC0_CD_PIN help text.
599 string "Card detect pin for mmc2"
602 See MMC0_CD_PIN help text.
605 string "Card detect pin for mmc3"
608 See MMC0_CD_PIN help text.
611 string "Pins for mmc1"
614 Set the pins used for mmc1, when applicable. This takes a string in the
615 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
618 string "Pins for mmc2"
621 See MMC1_PINS help text.
624 string "Pins for mmc3"
627 See MMC1_PINS help text.
629 config MMC_SUNXI_SLOT_EXTRA
630 int "mmc extra slot number"
633 sunxi builds always enable mmc0, some boards also have a second sdcard
634 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
637 config INITIAL_USB_SCAN_DELAY
638 int "delay initial usb scan by x ms to allow builtin devices to init"
641 Some boards have on board usb devices which need longer than the
642 USB spec's 1 second to connect from board powerup. Set this config
643 option to a non 0 value to add an extra delay before the first usb
647 string "Vbus enable pin for usb0 (otg)"
650 Set the Vbus enable pin for usb0 (otg). This takes a string in the
651 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
654 string "Vbus detect pin for usb0 (otg)"
657 Set the Vbus detect pin for usb0 (otg). This takes a string in the
658 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
661 string "ID detect pin for usb0 (otg)"
664 Set the ID detect pin for usb0 (otg). This takes a string in the
665 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
668 string "Vbus enable pin for usb1 (ehci0)"
669 default "PH6" if MACH_SUN4I || MACH_SUN7I
670 default "PH27" if MACH_SUN6I
672 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
673 a string in the format understood by sunxi_name_to_gpio, e.g.
674 PH1 for pin 1 of port H.
677 string "Vbus enable pin for usb2 (ehci1)"
678 default "PH3" if MACH_SUN4I || MACH_SUN7I
679 default "PH24" if MACH_SUN6I
681 See USB1_VBUS_PIN help text.
684 string "Vbus enable pin for usb3 (ehci2)"
687 See USB1_VBUS_PIN help text.
690 bool "Enable I2C/TWI controller 0"
691 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
692 default n if MACH_SUN6I || MACH_SUN8I
695 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
696 its clock and setting up the bus. This is especially useful on devices
697 with slaves connected to the bus or with pins exposed through e.g. an
698 expansion port/header.
701 bool "Enable I2C/TWI controller 1"
705 See I2C0_ENABLE help text.
708 bool "Enable I2C/TWI controller 2"
712 See I2C0_ENABLE help text.
714 if MACH_SUN6I || MACH_SUN7I
716 bool "Enable I2C/TWI controller 3"
720 See I2C0_ENABLE help text.
725 bool "Enable the PRCM I2C/TWI controller"
726 # This is used for the pmic on H3
727 default y if SY8106A_POWER
730 Set this to y to enable the I2C controller which is part of the PRCM.
735 bool "Enable I2C/TWI controller 4"
739 See I2C0_ENABLE help text.
743 bool "Enable support for gpio-s on axp PMICs"
746 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
749 bool "Enable graphical uboot console on HDMI, LCD or VGA"
750 depends on !MACH_SUN8I_A83T
751 depends on !MACH_SUNXI_H3_H5
752 depends on !MACH_SUN8I_R40
753 depends on !MACH_SUN8I_V3S
754 depends on !MACH_SUN9I
755 depends on !MACH_SUN50I
756 depends on !MACH_SUN50I_H6
758 imply VIDEO_DT_SIMPLEFB
761 Say Y here to add support for using a cfb console on the HDMI, LCD
762 or VGA output found on most sunxi devices. See doc/README.video for
763 info on how to select the video output and mode.
766 bool "HDMI output support"
767 depends on VIDEO_SUNXI && !MACH_SUN8I
770 Say Y here to add support for outputting video over HDMI.
773 bool "VGA output support"
774 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
777 Say Y here to add support for outputting video over VGA.
779 config VIDEO_VGA_VIA_LCD
780 bool "VGA via LCD controller support"
781 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
784 Say Y here to add support for external DACs connected to the parallel
785 LCD interface driving a VGA connector, such as found on the
788 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
789 bool "Force sync active high for VGA via LCD controller support"
790 depends on VIDEO_VGA_VIA_LCD
793 Say Y here if you've a board which uses opendrain drivers for the vga
794 hsync and vsync signals. Opendrain drivers cannot generate steep enough
795 positive edges for a stable video output, so on boards with opendrain
796 drivers the sync signals must always be active high.
798 config VIDEO_VGA_EXTERNAL_DAC_EN
799 string "LCD panel power enable pin"
800 depends on VIDEO_VGA_VIA_LCD
803 Set the enable pin for the external VGA DAC. This takes a string in the
804 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
806 config VIDEO_COMPOSITE
807 bool "Composite video output support"
808 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
811 Say Y here to add support for outputting composite video.
813 config VIDEO_LCD_MODE
814 string "LCD panel timing details"
815 depends on VIDEO_SUNXI
818 LCD panel timing details string, leave empty if there is no LCD panel.
819 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
820 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
821 Also see: http://linux-sunxi.org/LCD
823 config VIDEO_LCD_DCLK_PHASE
824 int "LCD panel display clock phase"
825 depends on VIDEO_SUNXI || DM_VIDEO
828 Select LCD panel display clock phase shift, range 0-3.
830 config VIDEO_LCD_POWER
831 string "LCD panel power enable pin"
832 depends on VIDEO_SUNXI
835 Set the power enable pin for the LCD panel. This takes a string in the
836 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
838 config VIDEO_LCD_RESET
839 string "LCD panel reset pin"
840 depends on VIDEO_SUNXI
843 Set the reset pin for the LCD panel. This takes a string in the format
844 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
846 config VIDEO_LCD_BL_EN
847 string "LCD panel backlight enable pin"
848 depends on VIDEO_SUNXI
851 Set the backlight enable pin for the LCD panel. This takes a string in the
852 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
855 config VIDEO_LCD_BL_PWM
856 string "LCD panel backlight pwm pin"
857 depends on VIDEO_SUNXI
860 Set the backlight pwm pin for the LCD panel. This takes a string in the
861 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
863 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
864 bool "LCD panel backlight pwm is inverted"
865 depends on VIDEO_SUNXI
868 Set this if the backlight pwm output is active low.
870 config VIDEO_LCD_PANEL_I2C
871 bool "LCD panel needs to be configured via i2c"
872 depends on VIDEO_SUNXI
876 Say y here if the LCD panel needs to be configured via i2c. This
877 will add a bitbang i2c controller using gpios to talk to the LCD.
879 config VIDEO_LCD_PANEL_I2C_SDA
880 string "LCD panel i2c interface SDA pin"
881 depends on VIDEO_LCD_PANEL_I2C
884 Set the SDA pin for the LCD i2c interface. This takes a string in the
885 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
887 config VIDEO_LCD_PANEL_I2C_SCL
888 string "LCD panel i2c interface SCL pin"
889 depends on VIDEO_LCD_PANEL_I2C
892 Set the SCL pin for the LCD i2c interface. This takes a string in the
893 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
896 # Note only one of these may be selected at a time! But hidden choices are
897 # not supported by Kconfig
898 config VIDEO_LCD_IF_PARALLEL
901 config VIDEO_LCD_IF_LVDS
909 bool "Display Engine 2 video driver"
913 imply VIDEO_DT_SIMPLEFB
916 Say y here if you want to build DE2 video driver which is present on
917 newer SoCs. Currently only HDMI output is supported.
921 prompt "LCD panel support"
922 depends on VIDEO_SUNXI
924 Select which type of LCD panel to support.
926 config VIDEO_LCD_PANEL_PARALLEL
927 bool "Generic parallel interface LCD panel"
928 select VIDEO_LCD_IF_PARALLEL
930 config VIDEO_LCD_PANEL_LVDS
931 bool "Generic lvds interface LCD panel"
932 select VIDEO_LCD_IF_LVDS
934 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
935 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
936 select VIDEO_LCD_SSD2828
937 select VIDEO_LCD_IF_PARALLEL
939 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
941 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
942 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
943 select VIDEO_LCD_ANX9804
944 select VIDEO_LCD_IF_PARALLEL
945 select VIDEO_LCD_PANEL_I2C
947 Select this for eDP LCD panels with 4 lanes running at 1.62G,
948 connected via an ANX9804 bridge chip.
950 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
951 bool "Hitachi tx18d42vm LCD panel"
952 select VIDEO_LCD_HITACHI_TX18D42VM
953 select VIDEO_LCD_IF_LVDS
955 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
957 config VIDEO_LCD_TL059WV5C0
958 bool "tl059wv5c0 LCD panel"
959 select VIDEO_LCD_PANEL_I2C
960 select VIDEO_LCD_IF_PARALLEL
962 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
963 Aigo M60/M608/M606 tablets.
968 string "SATA power pin"
971 Set the pins used to power the SATA. This takes a string in the
972 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
976 int "GMAC Transmit Clock Delay Chain"
979 Set the GMAC Transmit Clock Delay Chain value.
981 config SPL_STACK_R_ADDR
982 default 0x4fe00000 if MACH_SUN4I
983 default 0x4fe00000 if MACH_SUN5I
984 default 0x4fe00000 if MACH_SUN6I
985 default 0x4fe00000 if MACH_SUN7I
986 default 0x4fe00000 if MACH_SUN8I
987 default 0x2fe00000 if MACH_SUN9I
988 default 0x4fe00000 if MACH_SUN50I
989 default 0x4fe00000 if MACH_SUN50I_H6
992 bool "Support for SPI Flash on Allwinner SoCs in SPL"
993 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
995 Enable support for SPI Flash. This option allows SPL to read from
996 sunxi SPI Flash. It uses the same method as the boot ROM, so does
997 not need any extra configuration.
999 config PINE64_DT_SELECTION
1000 bool "Enable Pine64 device tree selection code"
1001 depends on MACH_SUN50I
1003 The original Pine A64 and Pine A64+ are similar but different
1004 boards and can be differed by the DRAM size. Pine A64 has
1005 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1006 option, the device tree selection code specific to Pine64 which
1007 utilizes the DRAM size will be enabled.