4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
51 config DRAM_SUN50I_H616
54 Select this dram controller driver for some sun50i platforms,
58 config DRAM_SUN50I_H616_WRITE_LEVELING
59 bool "H616 DRAM write leveling"
61 Select this when DRAM on your H616 board needs write leveling.
63 config DRAM_SUN50I_H616_READ_CALIBRATION
64 bool "H616 DRAM read calibration"
66 Select this when DRAM on your H616 board needs read calibration.
68 config DRAM_SUN50I_H616_READ_TRAINING
69 bool "H616 DRAM read training"
71 Select this when DRAM on your H616 board needs read training.
73 config DRAM_SUN50I_H616_WRITE_TRAINING
74 bool "H616 DRAM write training"
76 Select this when DRAM on your H616 board needs write training.
78 config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
79 bool "H616 DRAM bit delay compensation"
81 Select this when DRAM on your H616 board needs bit delay
84 config DRAM_SUN50I_H616_UNKNOWN_FEATURE
85 bool "H616 DRAM unknown feature"
87 Select this when DRAM on your H616 board needs this unknown
94 Support for the PRCM (Power/Reset/Clock Management) unit available
100 Select this PMIC bus access helpers for Sunxi platform PRCM or other
101 AXP family PMIC devices.
104 bool "Allwinner sunXi Reduced Serial Bus Driver"
106 Say y here to enable support for Allwinner's Reduced Serial Bus
107 (RSB) support. This controller is responsible for communicating
108 with various RSB based devices, such as AXP223, AXP8XX PMICs,
111 config SUNXI_SRAM_ADDRESS
113 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
114 default 0x20000 if SUN50I_GEN_H6
117 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
118 with the first SRAM region being located at address 0.
119 Some newer SoCs map the boot ROM at address 0 instead and move the
120 SRAM to a different address.
122 config SUNXI_A64_TIMER_ERRATUM
125 # Note only one of these may be selected at a time! But hidden choices are
126 # not supported by Kconfig
127 config SUNXI_GEN_SUN4I
130 Select this for sunxi SoCs which have resets and clocks set up
131 as the original A10 (mach-sun4i).
133 config SUNXI_GEN_SUN6I
136 Select this for sunxi SoCs which have sun6i like periphery, like
137 separate ahb reset control registers, custom pmic bus, new style
144 select MMC_SUNXI_HAS_NEW_MODE
147 Select this for sunxi SoCs which have H6 like peripherals, clocks
153 Select this for sunxi SoCs which uses a DRAM controller like the
154 DesignWare controller used in H3, mainly SoCs after H3, which do
155 not have official open-source DRAM initialization code, but can
156 use modified H3 DRAM initialization code.
159 config SUNXI_DRAM_DW_16BIT
162 Select this for sunxi SoCs with DesignWare DRAM controller and
163 have only 16-bit memory buswidth.
165 config SUNXI_DRAM_DW_32BIT
168 Select this for sunxi SoCs with DesignWare DRAM controller with
169 32-bit memory buswidth.
172 config MACH_SUNXI_H3_H5
178 select SUNXI_DRAM_DW_32BIT
179 select SUNXI_GEN_SUN6I
182 # TODO: try out A80's 8GiB DRAM space
183 config SUNXI_DRAM_MAX_SIZE
185 default 0x100000000 if MACH_SUN50I_H616
186 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
190 prompt "Sunxi SoC Variant"
194 bool "sun4i (Allwinner A10)"
196 select ARM_CORTEX_CPU_IS_UP
199 select SUNXI_GEN_SUN4I
201 imply SPL_SYS_I2C_LEGACY
205 bool "sun5i (Allwinner A13)"
207 select ARM_CORTEX_CPU_IS_UP
210 select SUNXI_GEN_SUN4I
212 imply CONS_INDEX_2 if !DM_SERIAL
213 imply SPL_SYS_I2C_LEGACY
217 bool "sun6i (Allwinner A31)"
219 select CPU_V7_HAS_NONSEC
220 select CPU_V7_HAS_VIRT
221 select ARCH_SUPPORT_PSCI
226 select SUNXI_GEN_SUN6I
228 select SYS_I2C_SUN6I_P2WI
229 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
232 bool "sun7i (Allwinner A20)"
234 select CPU_V7_HAS_NONSEC
235 select CPU_V7_HAS_VIRT
236 select ARCH_SUPPORT_PSCI
239 select SUNXI_GEN_SUN4I
241 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
242 imply SPL_SYS_I2C_LEGACY
245 config MACH_SUN8I_A23
246 bool "sun8i (Allwinner A23)"
248 select CPU_V7_HAS_NONSEC
249 select CPU_V7_HAS_VIRT
250 select ARCH_SUPPORT_PSCI
251 select DRAM_SUN8I_A23
254 select SUNXI_GEN_SUN6I
256 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
257 imply CONS_INDEX_5 if !DM_SERIAL
259 config MACH_SUN8I_A33
260 bool "sun8i (Allwinner A33)"
262 select CPU_V7_HAS_NONSEC
263 select CPU_V7_HAS_VIRT
264 select ARCH_SUPPORT_PSCI
265 select DRAM_SUN8I_A33
268 select SUNXI_GEN_SUN6I
270 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
271 imply CONS_INDEX_5 if !DM_SERIAL
273 config MACH_SUN8I_A83T
274 bool "sun8i (Allwinner A83T)"
276 select DRAM_SUN8I_A83T
279 select SUNXI_GEN_SUN6I
280 select MMC_SUNXI_HAS_NEW_MODE
281 select MMC_SUNXI_HAS_MODE_SWITCH
285 bool "sun8i (Allwinner H3)"
287 select CPU_V7_HAS_NONSEC
288 select CPU_V7_HAS_VIRT
289 select ARCH_SUPPORT_PSCI
290 select MACH_SUNXI_H3_H5
291 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
293 config MACH_SUN8I_R40
294 bool "sun8i (Allwinner R40)"
296 select CPU_V7_HAS_NONSEC
297 select CPU_V7_HAS_VIRT
298 select ARCH_SUPPORT_PSCI
299 select SUNXI_GEN_SUN6I
300 select MMC_SUNXI_HAS_NEW_MODE
303 select SUNXI_DRAM_DW_32BIT
305 imply SPL_SYS_I2C_LEGACY
307 config MACH_SUN8I_V3S
308 bool "sun8i (Allwinner V3/V3s/S3/S3L)"
310 select CPU_V7_HAS_NONSEC
311 select CPU_V7_HAS_VIRT
312 select ARCH_SUPPORT_PSCI
313 select SUNXI_GEN_SUN6I
315 select SUNXI_DRAM_DW_16BIT
317 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
320 bool "sun9i (Allwinner A80)"
324 select SUNXI_GEN_SUN6I
328 bool "sun50i (Allwinner A64)"
337 select SUNXI_GEN_SUN6I
338 select MMC_SUNXI_HAS_NEW_MODE
341 select SUNXI_DRAM_DW_32BIT
344 select SUNXI_A64_TIMER_ERRATUM
346 config MACH_SUN50I_H5
347 bool "sun50i (Allwinner H5)"
349 select MACH_SUNXI_H3_H5
350 select MMC_SUNXI_HAS_NEW_MODE
354 config MACH_SUN50I_H6
355 bool "sun50i (Allwinner H6)"
358 select DRAM_SUN50I_H6
361 config MACH_SUN50I_H616
362 bool "sun50i (Allwinner H616)"
364 select DRAM_SUN50I_H616
369 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
373 default y if MACH_SUN8I_A23
374 default y if MACH_SUN8I_A33
375 default y if MACH_SUN8I_A83T
376 default y if MACH_SUNXI_H3_H5
377 default y if MACH_SUN8I_R40
378 default y if MACH_SUN8I_V3S
380 config RESERVE_ALLWINNER_BOOT0_HEADER
381 bool "reserve space for Allwinner boot0 header"
382 select ENABLE_ARM_SOC_BOOT0_HOOK
384 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
385 filled with magic values post build. The Allwinner provided boot0
386 blob relies on this information to load and execute U-Boot.
387 Only needed on 64-bit Allwinner boards so far when using boot0.
389 config ARM_BOOT_HOOK_RMR
393 select ENABLE_ARM_SOC_BOOT0_HOOK
395 Insert some ARM32 code at the very beginning of the U-Boot binary
396 which uses an RMR register write to bring the core into AArch64 mode.
397 The very first instruction acts as a switch, since it's carefully
398 chosen to be a NOP in one mode and a branch in the other, so the
399 code would only be executed if not already in AArch64.
400 This allows both the SPL and the U-Boot proper to be entered in
401 either mode and switch to AArch64 if needed.
403 if SUNXI_DRAM_DW || DRAM_SUN50I_H6
404 config SUNXI_DRAM_DDR3
407 config SUNXI_DRAM_DDR2
410 config SUNXI_DRAM_LPDDR3
414 prompt "DRAM Type and Timing"
415 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
416 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
418 config SUNXI_DRAM_DDR3_1333
420 select SUNXI_DRAM_DDR3
422 This option is the original only supported memory type, which suits
423 many H3/H5/A64 boards available now.
425 config SUNXI_DRAM_LPDDR3_STOCK
426 bool "LPDDR3 with Allwinner stock configuration"
427 select SUNXI_DRAM_LPDDR3
429 This option is the LPDDR3 timing used by the stock boot0 by
432 config SUNXI_DRAM_H6_LPDDR3
433 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
434 select SUNXI_DRAM_LPDDR3
435 depends on DRAM_SUN50I_H6
437 This option is the LPDDR3 timing used by the stock boot0 by
440 config SUNXI_DRAM_H6_DDR3_1333
441 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
442 select SUNXI_DRAM_DDR3
443 depends on DRAM_SUN50I_H6
445 This option is the DDR3 timing used by the boot0 on H6 TV boxes
446 which use a DDR3-1333 timing.
448 config SUNXI_DRAM_DDR2_V3S
449 bool "DDR2 found in V3s chip"
450 select SUNXI_DRAM_DDR2
451 depends on MACH_SUN8I_V3S
453 This option is only for the DDR2 memory chip which is co-packaged in
460 int "sunxi dram type"
461 depends on MACH_SUN8I_A83T
464 Set the dram type, 3: DDR3, 7: LPDDR3
467 int "sunxi dram clock speed"
468 default 792 if MACH_SUN9I
469 default 648 if MACH_SUN8I_R40
470 default 312 if MACH_SUN6I || MACH_SUN8I
471 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
473 default 672 if MACH_SUN50I
474 default 744 if MACH_SUN50I_H6
475 default 720 if MACH_SUN50I_H616
477 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
478 must be a multiple of 24. For the sun9i (A80), the tested values
479 (for DDR3-1600) are 312 to 792.
481 if MACH_SUN5I || MACH_SUN7I
483 int "sunxi mbus clock speed"
486 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
491 int "sunxi dram zq value"
492 depends on !MACH_SUN50I_H616
493 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
494 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
495 default 127 if MACH_SUN7I
496 default 14779 if MACH_SUN8I_V3S
497 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
498 default 4145117 if MACH_SUN9I
499 default 3881915 if MACH_SUN50I
501 Set the dram zq value.
504 bool "sunxi dram odt enable"
505 default y if MACH_SUN8I_A23
506 default y if MACH_SUNXI_H3_H5
507 default y if MACH_SUN8I_R40
508 default y if MACH_SUN50I
509 default y if MACH_SUN50I_H6
510 default y if MACH_SUN50I_H616
512 Select this to enable dram odt (on die termination).
514 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
516 int "sunxi dram emr1 value"
517 default 0 if MACH_SUN4I
518 default 4 if MACH_SUN5I || MACH_SUN7I
520 Set the dram controller emr1 value.
523 hex "sunxi dram tpr3 value"
526 Set the dram controller tpr3 parameter. This parameter configures
527 the delay on the command lane and also phase shifts, which are
528 applied for sampling incoming read data. The default value 0
529 means that no phase/delay adjustments are necessary. Properly
530 configuring this parameter increases reliability at high DRAM
533 config DRAM_DQS_GATING_DELAY
534 hex "sunxi dram dqs_gating_delay value"
537 Set the dram controller dqs_gating_delay parmeter. Each byte
538 encodes the DQS gating delay for each byte lane. The delay
539 granularity is 1/4 cycle. For example, the value 0x05060606
540 means that the delay is 5 quarter-cycles for one lane (1.25
541 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
542 The default value 0 means autodetection. The results of hardware
543 autodetection are not very reliable and depend on the chip
544 temperature (sometimes producing different results on cold start
545 and warm reboot). But the accuracy of hardware autodetection
546 is usually good enough, unless running at really high DRAM
547 clocks speeds (up to 600MHz). If unsure, keep as 0.
550 prompt "sunxi dram timings"
551 default DRAM_TIMINGS_VENDOR_MAGIC
553 Select the timings of the DDR3 chips.
555 config DRAM_TIMINGS_VENDOR_MAGIC
556 bool "Magic vendor timings from Android"
558 The same DRAM timings as in the Allwinner boot0 bootloader.
560 config DRAM_TIMINGS_DDR3_1066F_1333H
561 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
563 Use the timings of the standard JEDEC DDR3-1066F speed bin for
564 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
565 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
566 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
567 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
568 that down binning to DDR3-1066F is supported (because DDR3-1066F
569 uses a bit faster timings than DDR3-1333H).
571 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
572 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
574 Use the timings of the slowest possible JEDEC speed bin for the
575 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
576 DDR3-800E, DDR3-1066G or DDR3-1333J.
583 config DRAM_ODT_CORRECTION
584 int "sunxi dram odt correction value"
587 Set the dram odt correction value (range -255 - 255). In allwinner
588 fex files, this option is found in bits 8-15 of the u32 odt_en variable
589 in the [dram] section. When bit 31 of the odt_en variable is set
590 then the correction is negative. Usually the value for this is 0.
594 default 1008000000 if MACH_SUN4I
595 default 1008000000 if MACH_SUN5I
596 default 1008000000 if MACH_SUN6I
597 default 912000000 if MACH_SUN7I
598 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
599 default 1008000000 if MACH_SUN8I
600 default 1008000000 if MACH_SUN9I
601 default 888000000 if MACH_SUN50I_H6
602 default 1008000000 if MACH_SUN50I_H616
604 config SYS_CONFIG_NAME
605 default "sun4i" if MACH_SUN4I
606 default "sun5i" if MACH_SUN5I
607 default "sun6i" if MACH_SUN6I
608 default "sun7i" if MACH_SUN7I
609 default "sun8i" if MACH_SUN8I
610 default "sun9i" if MACH_SUN9I
611 default "sun50i" if MACH_SUN50I
612 default "sun50i" if MACH_SUN50I_H6
613 default "sun50i" if MACH_SUN50I_H616
622 bool "UART0 on MicroSD breakout board"
624 Repurpose the SD card slot for getting access to the UART0 serial
625 console. Primarily useful only for low level u-boot debugging on
626 tablets, where normal UART0 is difficult to access and requires
627 device disassembly and/or soldering. As the SD card can't be used
628 at the same time, the system can be only booted in the FEL mode.
629 Only enable this if you really know what you are doing.
631 config OLD_SUNXI_KERNEL_COMPAT
632 bool "Enable workarounds for booting old kernels"
634 Set this to enable various workarounds for old kernels, this results in
635 sub-optimal settings for newer kernels, only enable if needed.
638 string "MAC power pin"
641 Set the pin used to power the MAC. This takes a string in the format
642 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
645 string "Card detect pin for mmc0"
646 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
649 Set the card detect pin for mmc0, leave empty to not use cd. This
650 takes a string in the format understood by sunxi_name_to_gpio, e.g.
651 PH1 for pin 1 of port H.
654 string "Card detect pin for mmc1"
657 See MMC0_CD_PIN help text.
660 string "Card detect pin for mmc2"
663 See MMC0_CD_PIN help text.
666 string "Card detect pin for mmc3"
669 See MMC0_CD_PIN help text.
672 bool "Pins for mmc1 are on Port H"
673 depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
675 Select this option for boards where mmc1 uses the Port H pinmux.
677 config MMC_SUNXI_SLOT_EXTRA
678 int "mmc extra slot number"
681 sunxi builds always enable mmc0, some boards also have a second sdcard
682 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
685 config INITIAL_USB_SCAN_DELAY
686 int "delay initial usb scan by x ms to allow builtin devices to init"
689 Some boards have on board usb devices which need longer than the
690 USB spec's 1 second to connect from board powerup. Set this config
691 option to a non 0 value to add an extra delay before the first usb
695 string "Vbus enable pin for usb0 (otg)"
698 Set the Vbus enable pin for usb0 (otg). This takes a string in the
699 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
702 string "Vbus detect pin for usb0 (otg)"
705 Set the Vbus detect pin for usb0 (otg). This takes a string in the
706 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
709 string "ID detect pin for usb0 (otg)"
712 Set the ID detect pin for usb0 (otg). This takes a string in the
713 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
716 string "Vbus enable pin for usb1 (ehci0)"
717 default "PH6" if MACH_SUN4I || MACH_SUN7I
718 default "PH27" if MACH_SUN6I
720 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
721 a string in the format understood by sunxi_name_to_gpio, e.g.
722 PH1 for pin 1 of port H.
725 string "Vbus enable pin for usb2 (ehci1)"
726 default "PH3" if MACH_SUN4I || MACH_SUN7I
727 default "PH24" if MACH_SUN6I
729 See USB1_VBUS_PIN help text.
732 string "Vbus enable pin for usb3 (ehci2)"
735 See USB1_VBUS_PIN help text.
738 bool "Enable I2C/TWI controller 0"
739 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
740 default n if MACH_SUN6I || MACH_SUN8I
743 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
744 its clock and setting up the bus. This is especially useful on devices
745 with slaves connected to the bus or with pins exposed through e.g. an
746 expansion port/header.
749 bool "Enable I2C/TWI controller 1"
752 See I2C0_ENABLE help text.
755 bool "Enable I2C/TWI controller 2"
758 See I2C0_ENABLE help text.
760 if MACH_SUN6I || MACH_SUN7I
762 bool "Enable I2C/TWI controller 3"
765 See I2C0_ENABLE help text.
768 if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
770 bool "Enable the PRCM I2C/TWI controller"
771 # This is used for the pmic on H3
772 default y if SY8106A_POWER
775 Set this to y to enable the I2C controller which is part of the PRCM.
780 bool "Enable I2C/TWI controller 4"
783 See I2C0_ENABLE help text.
787 bool "Enable support for gpio-s on axp PMICs"
788 depends on AXP_PMIC_BUS
790 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
793 bool "Enable graphical uboot console on HDMI, LCD or VGA"
794 depends on !MACH_SUN8I_A83T
795 depends on !MACH_SUNXI_H3_H5
796 depends on !MACH_SUN8I_R40
797 depends on !MACH_SUN8I_V3S
798 depends on !MACH_SUN9I
799 depends on !MACH_SUN50I
800 depends on !SUN50I_GEN_H6
803 imply VIDEO_DT_SIMPLEFB
806 Say Y here to add support for using a graphical console on the HDMI,
807 LCD or VGA output found on older sunxi devices. This will also provide
808 a simple_framebuffer device for Linux.
811 bool "HDMI output support"
812 depends on VIDEO_SUNXI && !MACH_SUN8I
815 Say Y here to add support for outputting video over HDMI.
818 bool "VGA output support"
819 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
821 Say Y here to add support for outputting video over VGA.
823 config VIDEO_VGA_VIA_LCD
824 bool "VGA via LCD controller support"
825 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
827 Say Y here to add support for external DACs connected to the parallel
828 LCD interface driving a VGA connector, such as found on the
831 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
832 bool "Force sync active high for VGA via LCD controller support"
833 depends on VIDEO_VGA_VIA_LCD
835 Say Y here if you've a board which uses opendrain drivers for the vga
836 hsync and vsync signals. Opendrain drivers cannot generate steep enough
837 positive edges for a stable video output, so on boards with opendrain
838 drivers the sync signals must always be active high.
840 config VIDEO_VGA_EXTERNAL_DAC_EN
841 string "LCD panel power enable pin"
842 depends on VIDEO_VGA_VIA_LCD
845 Set the enable pin for the external VGA DAC. This takes a string in the
846 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
848 config VIDEO_COMPOSITE
849 bool "Composite video output support"
850 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
852 Say Y here to add support for outputting composite video.
854 config VIDEO_LCD_MODE
855 string "LCD panel timing details"
856 depends on VIDEO_SUNXI
859 LCD panel timing details string, leave empty if there is no LCD panel.
860 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
861 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
862 Also see: http://linux-sunxi.org/LCD
864 config VIDEO_LCD_DCLK_PHASE
865 int "LCD panel display clock phase"
866 depends on VIDEO_SUNXI || DM_VIDEO
869 Select LCD panel display clock phase shift, range 0-3.
871 config VIDEO_LCD_POWER
872 string "LCD panel power enable pin"
873 depends on VIDEO_SUNXI
876 Set the power enable pin for the LCD panel. This takes a string in the
877 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
879 config VIDEO_LCD_RESET
880 string "LCD panel reset pin"
881 depends on VIDEO_SUNXI
884 Set the reset pin for the LCD panel. This takes a string in the format
885 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
887 config VIDEO_LCD_BL_EN
888 string "LCD panel backlight enable pin"
889 depends on VIDEO_SUNXI
892 Set the backlight enable pin for the LCD panel. This takes a string in the
893 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
896 config VIDEO_LCD_BL_PWM
897 string "LCD panel backlight pwm pin"
898 depends on VIDEO_SUNXI
901 Set the backlight pwm pin for the LCD panel. This takes a string in the
902 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
904 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
905 bool "LCD panel backlight pwm is inverted"
906 depends on VIDEO_SUNXI
909 Set this if the backlight pwm output is active low.
911 config VIDEO_LCD_PANEL_I2C
912 bool "LCD panel needs to be configured via i2c"
913 depends on VIDEO_SUNXI
916 Say y here if the LCD panel needs to be configured via i2c. This
917 will add a bitbang i2c controller using gpios to talk to the LCD.
919 config VIDEO_LCD_PANEL_I2C_SDA
920 string "LCD panel i2c interface SDA pin"
921 depends on VIDEO_LCD_PANEL_I2C
924 Set the SDA pin for the LCD i2c interface. This takes a string in the
925 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
927 config VIDEO_LCD_PANEL_I2C_SCL
928 string "LCD panel i2c interface SCL pin"
929 depends on VIDEO_LCD_PANEL_I2C
932 Set the SCL pin for the LCD i2c interface. This takes a string in the
933 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
936 # Note only one of these may be selected at a time! But hidden choices are
937 # not supported by Kconfig
938 config VIDEO_LCD_IF_PARALLEL
941 config VIDEO_LCD_IF_LVDS
948 bool "Display Engine 2 video driver"
953 imply VIDEO_DT_SIMPLEFB
956 Say y here if you want to build DE2 video driver which is present on
957 newer SoCs. Currently only HDMI output is supported.
961 prompt "LCD panel support"
962 depends on VIDEO_SUNXI
964 Select which type of LCD panel to support.
966 config VIDEO_LCD_PANEL_PARALLEL
967 bool "Generic parallel interface LCD panel"
968 select VIDEO_LCD_IF_PARALLEL
970 config VIDEO_LCD_PANEL_LVDS
971 bool "Generic lvds interface LCD panel"
972 select VIDEO_LCD_IF_LVDS
974 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
975 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
976 select VIDEO_LCD_SSD2828
977 select VIDEO_LCD_IF_PARALLEL
979 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
981 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
982 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
983 select VIDEO_LCD_ANX9804
984 select VIDEO_LCD_IF_PARALLEL
985 select VIDEO_LCD_PANEL_I2C
987 Select this for eDP LCD panels with 4 lanes running at 1.62G,
988 connected via an ANX9804 bridge chip.
990 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
991 bool "Hitachi tx18d42vm LCD panel"
992 select VIDEO_LCD_HITACHI_TX18D42VM
993 select VIDEO_LCD_IF_LVDS
995 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
997 config VIDEO_LCD_TL059WV5C0
998 bool "tl059wv5c0 LCD panel"
999 select VIDEO_LCD_PANEL_I2C
1000 select VIDEO_LCD_IF_PARALLEL
1002 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
1003 Aigo M60/M608/M606 tablets.
1008 string "SATA power pin"
1011 Set the pins used to power the SATA. This takes a string in the
1012 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
1015 config GMAC_TX_DELAY
1016 int "GMAC Transmit Clock Delay Chain"
1019 Set the GMAC Transmit Clock Delay Chain value.
1021 config SPL_STACK_R_ADDR
1022 default 0x4fe00000 if MACH_SUN4I
1023 default 0x4fe00000 if MACH_SUN5I
1024 default 0x4fe00000 if MACH_SUN6I
1025 default 0x4fe00000 if MACH_SUN7I
1026 default 0x4fe00000 if MACH_SUN8I
1027 default 0x2fe00000 if MACH_SUN9I
1028 default 0x4fe00000 if MACH_SUN50I
1029 default 0x4fe00000 if SUN50I_GEN_H6
1031 config SPL_SPI_SUNXI
1032 bool "Support for SPI Flash on Allwinner SoCs in SPL"
1033 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
1035 Enable support for SPI Flash. This option allows SPL to read from
1036 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1037 not need any extra configuration.
1039 config PINE64_DT_SELECTION
1040 bool "Enable Pine64 device tree selection code"
1041 depends on MACH_SUN50I
1043 The original Pine A64 and Pine A64+ are similar but different
1044 boards and can be differed by the DRAM size. Pine A64 has
1045 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1046 option, the device tree selection code specific to Pine64 which
1047 utilizes the DRAM size will be enabled.
1049 config PINEPHONE_DT_SELECTION
1050 bool "Enable PinePhone device tree selection code"
1051 depends on MACH_SUN50I
1053 Enable this option to automatically select the device tree for the
1054 correct PinePhone hardware revision during boot.
1056 config BLUETOOTH_DT_DEVICE_FIXUP
1057 string "Fixup the Bluetooth controller address"
1060 This option specifies the DT compatible name of the Bluetooth
1061 controller for which to set the "local-bd-address" property.
1062 Set this option if your device ships with the Bluetooth controller
1064 The used address is "bdaddr" if set, and "ethaddr" with the LSB
1069 config CHIP_DIP_SCAN
1070 bool "Enable DIPs detection for CHIP board"
1071 select SUPPORT_EXTENSION_SCAN
1075 select W1_EEPROM_DS24XXX
1076 select CMD_EXTENSION