4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
51 config DRAM_SUN50I_H616
54 Select this dram controller driver for some sun50i platforms,
58 config DRAM_SUN50I_H616_WRITE_LEVELING
59 bool "H616 DRAM write leveling"
61 Select this when DRAM on your H616 board needs write leveling.
63 config DRAM_SUN50I_H616_READ_CALIBRATION
64 bool "H616 DRAM read calibration"
66 Select this when DRAM on your H616 board needs read calibration.
68 config DRAM_SUN50I_H616_READ_TRAINING
69 bool "H616 DRAM read training"
71 Select this when DRAM on your H616 board needs read training.
73 config DRAM_SUN50I_H616_WRITE_TRAINING
74 bool "H616 DRAM write training"
76 Select this when DRAM on your H616 board needs write training.
78 config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
79 bool "H616 DRAM bit delay compensation"
81 Select this when DRAM on your H616 board needs bit delay
84 config DRAM_SUN50I_H616_UNKNOWN_FEATURE
85 bool "H616 DRAM unknown feature"
87 Select this when DRAM on your H616 board needs this unknown
92 bool "Allwinner sun6i internal P2WI controller"
94 If you say yes to this option, support will be included for the
95 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
97 The P2WI looks like an SMBus controller (which supports only byte
98 accesses), except that it only supports one slave device.
99 This interface is used to connect to specific PMIC devices (like the
105 Support for the PRCM (Power/Reset/Clock Management) unit available
111 Select this PMIC bus access helpers for Sunxi platform PRCM or other
112 AXP family PMIC devices.
115 bool "Allwinner sunXi Reduced Serial Bus Driver"
117 Say y here to enable support for Allwinner's Reduced Serial Bus
118 (RSB) support. This controller is responsible for communicating
119 with various RSB based devices, such as AXP223, AXP8XX PMICs,
122 config SUNXI_SRAM_ADDRESS
124 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
125 default 0x20000 if SUN50I_GEN_H6
128 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
129 with the first SRAM region being located at address 0.
130 Some newer SoCs map the boot ROM at address 0 instead and move the
131 SRAM to a different address.
133 config SUNXI_A64_TIMER_ERRATUM
136 # Note only one of these may be selected at a time! But hidden choices are
137 # not supported by Kconfig
138 config SUNXI_GEN_SUN4I
141 Select this for sunxi SoCs which have resets and clocks set up
142 as the original A10 (mach-sun4i).
144 config SUNXI_GEN_SUN6I
147 Select this for sunxi SoCs which have sun6i like periphery, like
148 separate ahb reset control registers, custom pmic bus, new style
155 select MMC_SUNXI_HAS_NEW_MODE
158 Select this for sunxi SoCs which have H6 like peripherals, clocks
164 Select this for sunxi SoCs which uses a DRAM controller like the
165 DesignWare controller used in H3, mainly SoCs after H3, which do
166 not have official open-source DRAM initialization code, but can
167 use modified H3 DRAM initialization code.
170 config SUNXI_DRAM_DW_16BIT
173 Select this for sunxi SoCs with DesignWare DRAM controller and
174 have only 16-bit memory buswidth.
176 config SUNXI_DRAM_DW_32BIT
179 Select this for sunxi SoCs with DesignWare DRAM controller with
180 32-bit memory buswidth.
183 config MACH_SUNXI_H3_H5
189 select SUNXI_DRAM_DW_32BIT
190 select SUNXI_GEN_SUN6I
193 # TODO: try out A80's 8GiB DRAM space
194 config SUNXI_DRAM_MAX_SIZE
196 default 0x100000000 if MACH_SUN50I_H616
197 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
201 prompt "Sunxi SoC Variant"
205 bool "sun4i (Allwinner A10)"
207 select ARM_CORTEX_CPU_IS_UP
210 select SUNXI_GEN_SUN4I
212 imply SPL_SYS_I2C_LEGACY
216 bool "sun5i (Allwinner A13)"
218 select ARM_CORTEX_CPU_IS_UP
221 select SUNXI_GEN_SUN4I
223 imply CONS_INDEX_2 if !DM_SERIAL
224 imply SPL_SYS_I2C_LEGACY
228 bool "sun6i (Allwinner A31)"
230 select CPU_V7_HAS_NONSEC
231 select CPU_V7_HAS_VIRT
232 select ARCH_SUPPORT_PSCI
237 select SUNXI_GEN_SUN6I
239 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
242 bool "sun7i (Allwinner A20)"
244 select CPU_V7_HAS_NONSEC
245 select CPU_V7_HAS_VIRT
246 select ARCH_SUPPORT_PSCI
249 select SUNXI_GEN_SUN4I
251 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
252 imply SPL_SYS_I2C_LEGACY
255 config MACH_SUN8I_A23
256 bool "sun8i (Allwinner A23)"
258 select CPU_V7_HAS_NONSEC
259 select CPU_V7_HAS_VIRT
260 select ARCH_SUPPORT_PSCI
261 select DRAM_SUN8I_A23
264 select SUNXI_GEN_SUN6I
266 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
267 imply CONS_INDEX_5 if !DM_SERIAL
269 config MACH_SUN8I_A33
270 bool "sun8i (Allwinner A33)"
272 select CPU_V7_HAS_NONSEC
273 select CPU_V7_HAS_VIRT
274 select ARCH_SUPPORT_PSCI
275 select DRAM_SUN8I_A33
278 select SUNXI_GEN_SUN6I
280 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
281 imply CONS_INDEX_5 if !DM_SERIAL
283 config MACH_SUN8I_A83T
284 bool "sun8i (Allwinner A83T)"
286 select DRAM_SUN8I_A83T
289 select SUNXI_GEN_SUN6I
290 select MMC_SUNXI_HAS_NEW_MODE
291 select MMC_SUNXI_HAS_MODE_SWITCH
295 bool "sun8i (Allwinner H3)"
297 select CPU_V7_HAS_NONSEC
298 select CPU_V7_HAS_VIRT
299 select ARCH_SUPPORT_PSCI
300 select MACH_SUNXI_H3_H5
301 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
303 config MACH_SUN8I_R40
304 bool "sun8i (Allwinner R40)"
306 select CPU_V7_HAS_NONSEC
307 select CPU_V7_HAS_VIRT
308 select ARCH_SUPPORT_PSCI
309 select SUNXI_GEN_SUN6I
310 select MMC_SUNXI_HAS_NEW_MODE
313 select SUNXI_DRAM_DW_32BIT
315 imply SPL_SYS_I2C_LEGACY
317 config MACH_SUN8I_V3S
318 bool "sun8i (Allwinner V3/V3s/S3/S3L)"
320 select CPU_V7_HAS_NONSEC
321 select CPU_V7_HAS_VIRT
322 select ARCH_SUPPORT_PSCI
323 select SUNXI_GEN_SUN6I
325 select SUNXI_DRAM_DW_16BIT
327 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
330 bool "sun9i (Allwinner A80)"
334 select SUNXI_GEN_SUN6I
338 bool "sun50i (Allwinner A64)"
347 select SUNXI_GEN_SUN6I
348 select MMC_SUNXI_HAS_NEW_MODE
351 select SUNXI_DRAM_DW_32BIT
354 select SUNXI_A64_TIMER_ERRATUM
356 config MACH_SUN50I_H5
357 bool "sun50i (Allwinner H5)"
359 select MACH_SUNXI_H3_H5
360 select MMC_SUNXI_HAS_NEW_MODE
364 config MACH_SUN50I_H6
365 bool "sun50i (Allwinner H6)"
368 select DRAM_SUN50I_H6
371 config MACH_SUN50I_H616
372 bool "sun50i (Allwinner H616)"
374 select DRAM_SUN50I_H616
379 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
383 default y if MACH_SUN8I_A23
384 default y if MACH_SUN8I_A33
385 default y if MACH_SUN8I_A83T
386 default y if MACH_SUNXI_H3_H5
387 default y if MACH_SUN8I_R40
388 default y if MACH_SUN8I_V3S
390 config RESERVE_ALLWINNER_BOOT0_HEADER
391 bool "reserve space for Allwinner boot0 header"
392 select ENABLE_ARM_SOC_BOOT0_HOOK
394 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
395 filled with magic values post build. The Allwinner provided boot0
396 blob relies on this information to load and execute U-Boot.
397 Only needed on 64-bit Allwinner boards so far when using boot0.
399 config ARM_BOOT_HOOK_RMR
403 select ENABLE_ARM_SOC_BOOT0_HOOK
405 Insert some ARM32 code at the very beginning of the U-Boot binary
406 which uses an RMR register write to bring the core into AArch64 mode.
407 The very first instruction acts as a switch, since it's carefully
408 chosen to be a NOP in one mode and a branch in the other, so the
409 code would only be executed if not already in AArch64.
410 This allows both the SPL and the U-Boot proper to be entered in
411 either mode and switch to AArch64 if needed.
413 if SUNXI_DRAM_DW || DRAM_SUN50I_H6
414 config SUNXI_DRAM_DDR3
417 config SUNXI_DRAM_DDR2
420 config SUNXI_DRAM_LPDDR3
424 prompt "DRAM Type and Timing"
425 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
426 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
428 config SUNXI_DRAM_DDR3_1333
430 select SUNXI_DRAM_DDR3
432 This option is the original only supported memory type, which suits
433 many H3/H5/A64 boards available now.
435 config SUNXI_DRAM_LPDDR3_STOCK
436 bool "LPDDR3 with Allwinner stock configuration"
437 select SUNXI_DRAM_LPDDR3
439 This option is the LPDDR3 timing used by the stock boot0 by
442 config SUNXI_DRAM_H6_LPDDR3
443 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
444 select SUNXI_DRAM_LPDDR3
445 depends on DRAM_SUN50I_H6
447 This option is the LPDDR3 timing used by the stock boot0 by
450 config SUNXI_DRAM_H6_DDR3_1333
451 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
452 select SUNXI_DRAM_DDR3
453 depends on DRAM_SUN50I_H6
455 This option is the DDR3 timing used by the boot0 on H6 TV boxes
456 which use a DDR3-1333 timing.
458 config SUNXI_DRAM_DDR2_V3S
459 bool "DDR2 found in V3s chip"
460 select SUNXI_DRAM_DDR2
461 depends on MACH_SUN8I_V3S
463 This option is only for the DDR2 memory chip which is co-packaged in
470 int "sunxi dram type"
471 depends on MACH_SUN8I_A83T
474 Set the dram type, 3: DDR3, 7: LPDDR3
477 int "sunxi dram clock speed"
478 default 792 if MACH_SUN9I
479 default 648 if MACH_SUN8I_R40
480 default 312 if MACH_SUN6I || MACH_SUN8I
481 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
483 default 672 if MACH_SUN50I
484 default 744 if MACH_SUN50I_H6
485 default 720 if MACH_SUN50I_H616
487 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
488 must be a multiple of 24. For the sun9i (A80), the tested values
489 (for DDR3-1600) are 312 to 792.
491 if MACH_SUN5I || MACH_SUN7I
493 int "sunxi mbus clock speed"
496 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
501 int "sunxi dram zq value"
502 depends on !MACH_SUN50I_H616
503 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
504 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
505 default 127 if MACH_SUN7I
506 default 14779 if MACH_SUN8I_V3S
507 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
508 default 4145117 if MACH_SUN9I
509 default 3881915 if MACH_SUN50I
511 Set the dram zq value.
514 bool "sunxi dram odt enable"
515 default y if MACH_SUN8I_A23
516 default y if MACH_SUNXI_H3_H5
517 default y if MACH_SUN8I_R40
518 default y if MACH_SUN50I
519 default y if MACH_SUN50I_H6
520 default y if MACH_SUN50I_H616
522 Select this to enable dram odt (on die termination).
524 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
526 int "sunxi dram emr1 value"
527 default 0 if MACH_SUN4I
528 default 4 if MACH_SUN5I || MACH_SUN7I
530 Set the dram controller emr1 value.
533 hex "sunxi dram tpr3 value"
536 Set the dram controller tpr3 parameter. This parameter configures
537 the delay on the command lane and also phase shifts, which are
538 applied for sampling incoming read data. The default value 0
539 means that no phase/delay adjustments are necessary. Properly
540 configuring this parameter increases reliability at high DRAM
543 config DRAM_DQS_GATING_DELAY
544 hex "sunxi dram dqs_gating_delay value"
547 Set the dram controller dqs_gating_delay parmeter. Each byte
548 encodes the DQS gating delay for each byte lane. The delay
549 granularity is 1/4 cycle. For example, the value 0x05060606
550 means that the delay is 5 quarter-cycles for one lane (1.25
551 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
552 The default value 0 means autodetection. The results of hardware
553 autodetection are not very reliable and depend on the chip
554 temperature (sometimes producing different results on cold start
555 and warm reboot). But the accuracy of hardware autodetection
556 is usually good enough, unless running at really high DRAM
557 clocks speeds (up to 600MHz). If unsure, keep as 0.
560 prompt "sunxi dram timings"
561 default DRAM_TIMINGS_VENDOR_MAGIC
563 Select the timings of the DDR3 chips.
565 config DRAM_TIMINGS_VENDOR_MAGIC
566 bool "Magic vendor timings from Android"
568 The same DRAM timings as in the Allwinner boot0 bootloader.
570 config DRAM_TIMINGS_DDR3_1066F_1333H
571 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
573 Use the timings of the standard JEDEC DDR3-1066F speed bin for
574 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
575 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
576 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
577 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
578 that down binning to DDR3-1066F is supported (because DDR3-1066F
579 uses a bit faster timings than DDR3-1333H).
581 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
582 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
584 Use the timings of the slowest possible JEDEC speed bin for the
585 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
586 DDR3-800E, DDR3-1066G or DDR3-1333J.
593 config DRAM_ODT_CORRECTION
594 int "sunxi dram odt correction value"
597 Set the dram odt correction value (range -255 - 255). In allwinner
598 fex files, this option is found in bits 8-15 of the u32 odt_en variable
599 in the [dram] section. When bit 31 of the odt_en variable is set
600 then the correction is negative. Usually the value for this is 0.
604 default 1008000000 if MACH_SUN4I
605 default 1008000000 if MACH_SUN5I
606 default 1008000000 if MACH_SUN6I
607 default 912000000 if MACH_SUN7I
608 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
609 default 1008000000 if MACH_SUN8I
610 default 1008000000 if MACH_SUN9I
611 default 888000000 if MACH_SUN50I_H6
612 default 1008000000 if MACH_SUN50I_H616
614 config SYS_CONFIG_NAME
615 default "sun4i" if MACH_SUN4I
616 default "sun5i" if MACH_SUN5I
617 default "sun6i" if MACH_SUN6I
618 default "sun7i" if MACH_SUN7I
619 default "sun8i" if MACH_SUN8I
620 default "sun9i" if MACH_SUN9I
621 default "sun50i" if MACH_SUN50I
622 default "sun50i" if MACH_SUN50I_H6
623 default "sun50i" if MACH_SUN50I_H616
632 bool "UART0 on MicroSD breakout board"
634 Repurpose the SD card slot for getting access to the UART0 serial
635 console. Primarily useful only for low level u-boot debugging on
636 tablets, where normal UART0 is difficult to access and requires
637 device disassembly and/or soldering. As the SD card can't be used
638 at the same time, the system can be only booted in the FEL mode.
639 Only enable this if you really know what you are doing.
641 config OLD_SUNXI_KERNEL_COMPAT
642 bool "Enable workarounds for booting old kernels"
644 Set this to enable various workarounds for old kernels, this results in
645 sub-optimal settings for newer kernels, only enable if needed.
648 string "MAC power pin"
651 Set the pin used to power the MAC. This takes a string in the format
652 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
655 string "Card detect pin for mmc0"
656 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
659 Set the card detect pin for mmc0, leave empty to not use cd. This
660 takes a string in the format understood by sunxi_name_to_gpio, e.g.
661 PH1 for pin 1 of port H.
664 string "Card detect pin for mmc1"
667 See MMC0_CD_PIN help text.
670 string "Card detect pin for mmc2"
673 See MMC0_CD_PIN help text.
676 string "Card detect pin for mmc3"
679 See MMC0_CD_PIN help text.
682 bool "Pins for mmc1 are on Port H"
683 depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
685 Select this option for boards where mmc1 uses the Port H pinmux.
687 config MMC_SUNXI_SLOT_EXTRA
688 int "mmc extra slot number"
691 sunxi builds always enable mmc0, some boards also have a second sdcard
692 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
695 config INITIAL_USB_SCAN_DELAY
696 int "delay initial usb scan by x ms to allow builtin devices to init"
699 Some boards have on board usb devices which need longer than the
700 USB spec's 1 second to connect from board powerup. Set this config
701 option to a non 0 value to add an extra delay before the first usb
705 string "Vbus enable pin for usb0 (otg)"
708 Set the Vbus enable pin for usb0 (otg). This takes a string in the
709 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
712 string "Vbus detect pin for usb0 (otg)"
715 Set the Vbus detect pin for usb0 (otg). This takes a string in the
716 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
719 string "ID detect pin for usb0 (otg)"
722 Set the ID detect pin for usb0 (otg). This takes a string in the
723 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
726 string "Vbus enable pin for usb1 (ehci0)"
727 default "PH6" if MACH_SUN4I || MACH_SUN7I
728 default "PH27" if MACH_SUN6I
730 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
731 a string in the format understood by sunxi_name_to_gpio, e.g.
732 PH1 for pin 1 of port H.
735 string "Vbus enable pin for usb2 (ehci1)"
736 default "PH3" if MACH_SUN4I || MACH_SUN7I
737 default "PH24" if MACH_SUN6I
739 See USB1_VBUS_PIN help text.
742 string "Vbus enable pin for usb3 (ehci2)"
745 See USB1_VBUS_PIN help text.
748 bool "Enable I2C/TWI controller 0"
749 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
750 default n if MACH_SUN6I || MACH_SUN8I
753 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
754 its clock and setting up the bus. This is especially useful on devices
755 with slaves connected to the bus or with pins exposed through e.g. an
756 expansion port/header.
759 bool "Enable I2C/TWI controller 1"
762 See I2C0_ENABLE help text.
765 bool "Enable I2C/TWI controller 2"
768 See I2C0_ENABLE help text.
770 if MACH_SUN6I || MACH_SUN7I
772 bool "Enable I2C/TWI controller 3"
775 See I2C0_ENABLE help text.
778 if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
780 bool "Enable the PRCM I2C/TWI controller"
781 # This is used for the pmic on H3
782 default y if SY8106A_POWER
785 Set this to y to enable the I2C controller which is part of the PRCM.
790 bool "Enable I2C/TWI controller 4"
793 See I2C0_ENABLE help text.
797 bool "Enable support for gpio-s on axp PMICs"
798 depends on AXP_PMIC_BUS
800 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
803 bool "Enable graphical uboot console on HDMI, LCD or VGA"
804 depends on !MACH_SUN8I_A83T
805 depends on !MACH_SUNXI_H3_H5
806 depends on !MACH_SUN8I_R40
807 depends on !MACH_SUN8I_V3S
808 depends on !MACH_SUN9I
809 depends on !MACH_SUN50I
810 depends on !SUN50I_GEN_H6
813 imply VIDEO_DT_SIMPLEFB
816 Say Y here to add support for using a graphical console on the HDMI,
817 LCD or VGA output found on older sunxi devices. This will also provide
818 a simple_framebuffer device for Linux.
821 bool "HDMI output support"
822 depends on VIDEO_SUNXI && !MACH_SUN8I
825 Say Y here to add support for outputting video over HDMI.
828 bool "VGA output support"
829 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
831 Say Y here to add support for outputting video over VGA.
833 config VIDEO_VGA_VIA_LCD
834 bool "VGA via LCD controller support"
835 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
837 Say Y here to add support for external DACs connected to the parallel
838 LCD interface driving a VGA connector, such as found on the
841 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
842 bool "Force sync active high for VGA via LCD controller support"
843 depends on VIDEO_VGA_VIA_LCD
845 Say Y here if you've a board which uses opendrain drivers for the vga
846 hsync and vsync signals. Opendrain drivers cannot generate steep enough
847 positive edges for a stable video output, so on boards with opendrain
848 drivers the sync signals must always be active high.
850 config VIDEO_VGA_EXTERNAL_DAC_EN
851 string "LCD panel power enable pin"
852 depends on VIDEO_VGA_VIA_LCD
855 Set the enable pin for the external VGA DAC. This takes a string in the
856 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
858 config VIDEO_COMPOSITE
859 bool "Composite video output support"
860 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
862 Say Y here to add support for outputting composite video.
864 config VIDEO_LCD_MODE
865 string "LCD panel timing details"
866 depends on VIDEO_SUNXI
869 LCD panel timing details string, leave empty if there is no LCD panel.
870 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
871 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
872 Also see: http://linux-sunxi.org/LCD
874 config VIDEO_LCD_DCLK_PHASE
875 int "LCD panel display clock phase"
876 depends on VIDEO_SUNXI || DM_VIDEO
879 Select LCD panel display clock phase shift, range 0-3.
881 config VIDEO_LCD_POWER
882 string "LCD panel power enable pin"
883 depends on VIDEO_SUNXI
886 Set the power enable pin for the LCD panel. This takes a string in the
887 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
889 config VIDEO_LCD_RESET
890 string "LCD panel reset pin"
891 depends on VIDEO_SUNXI
894 Set the reset pin for the LCD panel. This takes a string in the format
895 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
897 config VIDEO_LCD_BL_EN
898 string "LCD panel backlight enable pin"
899 depends on VIDEO_SUNXI
902 Set the backlight enable pin for the LCD panel. This takes a string in the
903 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
906 config VIDEO_LCD_BL_PWM
907 string "LCD panel backlight pwm pin"
908 depends on VIDEO_SUNXI
911 Set the backlight pwm pin for the LCD panel. This takes a string in the
912 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
914 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
915 bool "LCD panel backlight pwm is inverted"
916 depends on VIDEO_SUNXI
919 Set this if the backlight pwm output is active low.
921 config VIDEO_LCD_PANEL_I2C
922 bool "LCD panel needs to be configured via i2c"
923 depends on VIDEO_SUNXI
926 Say y here if the LCD panel needs to be configured via i2c. This
927 will add a bitbang i2c controller using gpios to talk to the LCD.
929 config VIDEO_LCD_PANEL_I2C_SDA
930 string "LCD panel i2c interface SDA pin"
931 depends on VIDEO_LCD_PANEL_I2C
934 Set the SDA pin for the LCD i2c interface. This takes a string in the
935 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
937 config VIDEO_LCD_PANEL_I2C_SCL
938 string "LCD panel i2c interface SCL pin"
939 depends on VIDEO_LCD_PANEL_I2C
942 Set the SCL pin for the LCD i2c interface. This takes a string in the
943 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
946 # Note only one of these may be selected at a time! But hidden choices are
947 # not supported by Kconfig
948 config VIDEO_LCD_IF_PARALLEL
951 config VIDEO_LCD_IF_LVDS
958 bool "Display Engine 2 video driver"
963 imply VIDEO_DT_SIMPLEFB
966 Say y here if you want to build DE2 video driver which is present on
967 newer SoCs. Currently only HDMI output is supported.
971 prompt "LCD panel support"
972 depends on VIDEO_SUNXI
974 Select which type of LCD panel to support.
976 config VIDEO_LCD_PANEL_PARALLEL
977 bool "Generic parallel interface LCD panel"
978 select VIDEO_LCD_IF_PARALLEL
980 config VIDEO_LCD_PANEL_LVDS
981 bool "Generic lvds interface LCD panel"
982 select VIDEO_LCD_IF_LVDS
984 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
985 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
986 select VIDEO_LCD_SSD2828
987 select VIDEO_LCD_IF_PARALLEL
989 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
991 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
992 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
993 select VIDEO_LCD_ANX9804
994 select VIDEO_LCD_IF_PARALLEL
995 select VIDEO_LCD_PANEL_I2C
997 Select this for eDP LCD panels with 4 lanes running at 1.62G,
998 connected via an ANX9804 bridge chip.
1000 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
1001 bool "Hitachi tx18d42vm LCD panel"
1002 select VIDEO_LCD_HITACHI_TX18D42VM
1003 select VIDEO_LCD_IF_LVDS
1005 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
1007 config VIDEO_LCD_TL059WV5C0
1008 bool "tl059wv5c0 LCD panel"
1009 select VIDEO_LCD_PANEL_I2C
1010 select VIDEO_LCD_IF_PARALLEL
1012 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
1013 Aigo M60/M608/M606 tablets.
1018 string "SATA power pin"
1021 Set the pins used to power the SATA. This takes a string in the
1022 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
1025 config GMAC_TX_DELAY
1026 int "GMAC Transmit Clock Delay Chain"
1029 Set the GMAC Transmit Clock Delay Chain value.
1031 config SPL_STACK_R_ADDR
1032 default 0x4fe00000 if MACH_SUN4I
1033 default 0x4fe00000 if MACH_SUN5I
1034 default 0x4fe00000 if MACH_SUN6I
1035 default 0x4fe00000 if MACH_SUN7I
1036 default 0x4fe00000 if MACH_SUN8I
1037 default 0x2fe00000 if MACH_SUN9I
1038 default 0x4fe00000 if MACH_SUN50I
1039 default 0x4fe00000 if SUN50I_GEN_H6
1041 config SPL_SPI_SUNXI
1042 bool "Support for SPI Flash on Allwinner SoCs in SPL"
1043 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
1045 Enable support for SPI Flash. This option allows SPL to read from
1046 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1047 not need any extra configuration.
1049 config PINE64_DT_SELECTION
1050 bool "Enable Pine64 device tree selection code"
1051 depends on MACH_SUN50I
1053 The original Pine A64 and Pine A64+ are similar but different
1054 boards and can be differed by the DRAM size. Pine A64 has
1055 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1056 option, the device tree selection code specific to Pine64 which
1057 utilizes the DRAM size will be enabled.
1059 config PINEPHONE_DT_SELECTION
1060 bool "Enable PinePhone device tree selection code"
1061 depends on MACH_SUN50I
1063 Enable this option to automatically select the device tree for the
1064 correct PinePhone hardware revision during boot.
1066 config BLUETOOTH_DT_DEVICE_FIXUP
1067 string "Fixup the Bluetooth controller address"
1070 This option specifies the DT compatible name of the Bluetooth
1071 controller for which to set the "local-bd-address" property.
1072 Set this option if your device ships with the Bluetooth controller
1074 The used address is "bdaddr" if set, and "ethaddr" with the LSB
1079 config CHIP_DIP_SCAN
1080 bool "Enable DIPs detection for CHIP board"
1081 select SUPPORT_EXTENSION_SCAN
1085 select W1_EEPROM_DS24XXX
1086 select CMD_EXTENSION