4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
46 bool "Allwinner sun6i internal P2WI controller"
48 If you say yes to this option, support will be included for the
49 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
51 The P2WI looks like an SMBus controller (which supports only byte
52 accesses), except that it only supports one slave device.
53 This interface is used to connect to specific PMIC devices (like the
59 Support for the PRCM (Power/Reset/Clock Management) unit available
63 bool "Sunxi AXP PMIC bus access helpers"
65 Select this PMIC bus access helpers for Sunxi platform PRCM or other
66 AXP family PMIC devices.
69 bool "Allwinner sunXi Reduced Serial Bus Driver"
71 Say y here to enable support for Allwinner's Reduced Serial Bus
72 (RSB) support. This controller is responsible for communicating
73 with various RSB based devices, such as AXP223, AXP8XX PMICs,
76 config SUNXI_SRAM_ADDRESS
78 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
81 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
82 with the first SRAM region being located at address 0.
83 Some newer SoCs map the boot ROM at address 0 instead and move the
84 SRAM to a different address.
86 config SUNXI_A64_TIMER_ERRATUM
89 # Note only one of these may be selected at a time! But hidden choices are
90 # not supported by Kconfig
91 config SUNXI_GEN_SUN4I
94 Select this for sunxi SoCs which have resets and clocks set up
95 as the original A10 (mach-sun4i).
97 config SUNXI_GEN_SUN6I
100 Select this for sunxi SoCs which have sun6i like periphery, like
101 separate ahb reset control registers, custom pmic bus, new style
107 Select this for sunxi SoCs which uses a DRAM controller like the
108 DesignWare controller used in H3, mainly SoCs after H3, which do
109 not have official open-source DRAM initialization code, but can
110 use modified H3 DRAM initialization code.
113 config SUNXI_DRAM_DW_16BIT
116 Select this for sunxi SoCs with DesignWare DRAM controller and
117 have only 16-bit memory buswidth.
119 config SUNXI_DRAM_DW_32BIT
122 Select this for sunxi SoCs with DesignWare DRAM controller with
123 32-bit memory buswidth.
126 config MACH_SUNXI_H3_H5
132 select SUNXI_DRAM_DW_32BIT
133 select SUNXI_GEN_SUN6I
137 prompt "Sunxi SoC Variant"
141 bool "sun4i (Allwinner A10)"
143 select ARM_CORTEX_CPU_IS_UP
145 select DM_SCSI if SCSI
148 select SUNXI_GEN_SUN4I
152 bool "sun5i (Allwinner A13)"
154 select ARM_CORTEX_CPU_IS_UP
157 select SUNXI_GEN_SUN4I
159 imply CONS_INDEX_2 if !DM_SERIAL
162 bool "sun6i (Allwinner A31)"
164 select CPU_V7_HAS_NONSEC
165 select CPU_V7_HAS_VIRT
166 select ARCH_SUPPORT_PSCI
171 select SUNXI_GEN_SUN6I
173 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
176 bool "sun7i (Allwinner A20)"
178 select CPU_V7_HAS_NONSEC
179 select CPU_V7_HAS_VIRT
180 select ARCH_SUPPORT_PSCI
183 select SUNXI_GEN_SUN4I
185 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
187 config MACH_SUN8I_A23
188 bool "sun8i (Allwinner A23)"
190 select CPU_V7_HAS_NONSEC
191 select CPU_V7_HAS_VIRT
192 select ARCH_SUPPORT_PSCI
193 select DRAM_SUN8I_A23
195 select SUNXI_GEN_SUN6I
197 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
198 imply CONS_INDEX_5 if !DM_SERIAL
200 config MACH_SUN8I_A33
201 bool "sun8i (Allwinner A33)"
203 select CPU_V7_HAS_NONSEC
204 select CPU_V7_HAS_VIRT
205 select ARCH_SUPPORT_PSCI
206 select DRAM_SUN8I_A33
208 select SUNXI_GEN_SUN6I
210 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
211 imply CONS_INDEX_5 if !DM_SERIAL
213 config MACH_SUN8I_A83T
214 bool "sun8i (Allwinner A83T)"
216 select DRAM_SUN8I_A83T
218 select SUNXI_GEN_SUN6I
219 select MMC_SUNXI_HAS_NEW_MODE
223 bool "sun8i (Allwinner H3)"
225 select CPU_V7_HAS_NONSEC
226 select CPU_V7_HAS_VIRT
227 select ARCH_SUPPORT_PSCI
228 select MACH_SUNXI_H3_H5
229 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
231 config MACH_SUN8I_R40
232 bool "sun8i (Allwinner R40)"
234 select CPU_V7_HAS_NONSEC
235 select CPU_V7_HAS_VIRT
236 select ARCH_SUPPORT_PSCI
237 select SUNXI_GEN_SUN6I
240 select SUNXI_DRAM_DW_32BIT
242 config MACH_SUN8I_V3S
243 bool "sun8i (Allwinner V3s)"
245 select CPU_V7_HAS_NONSEC
246 select CPU_V7_HAS_VIRT
247 select ARCH_SUPPORT_PSCI
248 select SUNXI_GEN_SUN6I
250 select SUNXI_DRAM_DW_16BIT
252 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
255 bool "sun9i (Allwinner A80)"
259 select SUNXI_GEN_SUN6I
264 bool "sun50i (Allwinner A64)"
269 select SUNXI_GEN_SUN6I
272 select SUNXI_DRAM_DW_32BIT
275 select SUNXI_A64_TIMER_ERRATUM
277 config MACH_SUN50I_H5
278 bool "sun50i (Allwinner H5)"
280 select MACH_SUNXI_H3_H5
286 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
291 default y if MACH_SUN8I_A23
292 default y if MACH_SUN8I_A33
293 default y if MACH_SUN8I_A83T
294 default y if MACH_SUNXI_H3_H5
295 default y if MACH_SUN8I_R40
296 default y if MACH_SUN8I_V3S
298 config RESERVE_ALLWINNER_BOOT0_HEADER
299 bool "reserve space for Allwinner boot0 header"
300 select ENABLE_ARM_SOC_BOOT0_HOOK
302 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
303 filled with magic values post build. The Allwinner provided boot0
304 blob relies on this information to load and execute U-Boot.
305 Only needed on 64-bit Allwinner boards so far when using boot0.
307 config ARM_BOOT_HOOK_RMR
311 select ENABLE_ARM_SOC_BOOT0_HOOK
313 Insert some ARM32 code at the very beginning of the U-Boot binary
314 which uses an RMR register write to bring the core into AArch64 mode.
315 The very first instruction acts as a switch, since it's carefully
316 chosen to be a NOP in one mode and a branch in the other, so the
317 code would only be executed if not already in AArch64.
318 This allows both the SPL and the U-Boot proper to be entered in
319 either mode and switch to AArch64 if needed.
322 config SUNXI_DRAM_DDR3
325 config SUNXI_DRAM_DDR2
328 config SUNXI_DRAM_LPDDR3
332 prompt "DRAM Type and Timing"
333 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
334 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
336 config SUNXI_DRAM_DDR3_1333
338 select SUNXI_DRAM_DDR3
339 depends on !MACH_SUN8I_V3S
341 This option is the original only supported memory type, which suits
342 many H3/H5/A64 boards available now.
344 config SUNXI_DRAM_LPDDR3_STOCK
345 bool "LPDDR3 with Allwinner stock configuration"
346 select SUNXI_DRAM_LPDDR3
348 This option is the LPDDR3 timing used by the stock boot0 by
351 config SUNXI_DRAM_DDR2_V3S
352 bool "DDR2 found in V3s chip"
353 select SUNXI_DRAM_DDR2
354 depends on MACH_SUN8I_V3S
356 This option is only for the DDR2 memory chip which is co-packaged in
363 int "sunxi dram type"
364 depends on MACH_SUN8I_A83T
367 Set the dram type, 3: DDR3, 7: LPDDR3
370 int "sunxi dram clock speed"
371 default 792 if MACH_SUN9I
372 default 648 if MACH_SUN8I_R40
373 default 312 if MACH_SUN6I || MACH_SUN8I
374 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
376 default 672 if MACH_SUN50I
378 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
379 must be a multiple of 24. For the sun9i (A80), the tested values
380 (for DDR3-1600) are 312 to 792.
382 if MACH_SUN5I || MACH_SUN7I
384 int "sunxi mbus clock speed"
387 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
392 int "sunxi dram zq value"
393 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
394 default 127 if MACH_SUN7I
395 default 14779 if MACH_SUN8I_V3S
396 default 3881979 if MACH_SUN8I_R40
397 default 4145117 if MACH_SUN9I
398 default 3881915 if MACH_SUN50I
400 Set the dram zq value.
403 bool "sunxi dram odt enable"
404 default n if !MACH_SUN8I_A23
405 default y if MACH_SUN8I_A23
406 default y if MACH_SUN8I_R40
407 default y if MACH_SUN50I
409 Select this to enable dram odt (on die termination).
411 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
413 int "sunxi dram emr1 value"
414 default 0 if MACH_SUN4I
415 default 4 if MACH_SUN5I || MACH_SUN7I
417 Set the dram controller emr1 value.
420 hex "sunxi dram tpr3 value"
423 Set the dram controller tpr3 parameter. This parameter configures
424 the delay on the command lane and also phase shifts, which are
425 applied for sampling incoming read data. The default value 0
426 means that no phase/delay adjustments are necessary. Properly
427 configuring this parameter increases reliability at high DRAM
430 config DRAM_DQS_GATING_DELAY
431 hex "sunxi dram dqs_gating_delay value"
434 Set the dram controller dqs_gating_delay parmeter. Each byte
435 encodes the DQS gating delay for each byte lane. The delay
436 granularity is 1/4 cycle. For example, the value 0x05060606
437 means that the delay is 5 quarter-cycles for one lane (1.25
438 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
439 The default value 0 means autodetection. The results of hardware
440 autodetection are not very reliable and depend on the chip
441 temperature (sometimes producing different results on cold start
442 and warm reboot). But the accuracy of hardware autodetection
443 is usually good enough, unless running at really high DRAM
444 clocks speeds (up to 600MHz). If unsure, keep as 0.
447 prompt "sunxi dram timings"
448 default DRAM_TIMINGS_VENDOR_MAGIC
450 Select the timings of the DDR3 chips.
452 config DRAM_TIMINGS_VENDOR_MAGIC
453 bool "Magic vendor timings from Android"
455 The same DRAM timings as in the Allwinner boot0 bootloader.
457 config DRAM_TIMINGS_DDR3_1066F_1333H
458 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
460 Use the timings of the standard JEDEC DDR3-1066F speed bin for
461 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
462 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
463 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
464 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
465 that down binning to DDR3-1066F is supported (because DDR3-1066F
466 uses a bit faster timings than DDR3-1333H).
468 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
469 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
471 Use the timings of the slowest possible JEDEC speed bin for the
472 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
473 DDR3-800E, DDR3-1066G or DDR3-1333J.
480 config DRAM_ODT_CORRECTION
481 int "sunxi dram odt correction value"
484 Set the dram odt correction value (range -255 - 255). In allwinner
485 fex files, this option is found in bits 8-15 of the u32 odt_en variable
486 in the [dram] section. When bit 31 of the odt_en variable is set
487 then the correction is negative. Usually the value for this is 0.
491 default 1008000000 if MACH_SUN4I
492 default 1008000000 if MACH_SUN5I
493 default 1008000000 if MACH_SUN6I
494 default 912000000 if MACH_SUN7I
495 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
496 default 1008000000 if MACH_SUN8I
497 default 1008000000 if MACH_SUN9I
499 config SYS_CONFIG_NAME
500 default "sun4i" if MACH_SUN4I
501 default "sun5i" if MACH_SUN5I
502 default "sun6i" if MACH_SUN6I
503 default "sun7i" if MACH_SUN7I
504 default "sun8i" if MACH_SUN8I
505 default "sun9i" if MACH_SUN9I
506 default "sun50i" if MACH_SUN50I
515 bool "UART0 on MicroSD breakout board"
518 Repurpose the SD card slot for getting access to the UART0 serial
519 console. Primarily useful only for low level u-boot debugging on
520 tablets, where normal UART0 is difficult to access and requires
521 device disassembly and/or soldering. As the SD card can't be used
522 at the same time, the system can be only booted in the FEL mode.
523 Only enable this if you really know what you are doing.
525 config OLD_SUNXI_KERNEL_COMPAT
526 bool "Enable workarounds for booting old kernels"
529 Set this to enable various workarounds for old kernels, this results in
530 sub-optimal settings for newer kernels, only enable if needed.
533 string "MAC power pin"
536 Set the pin used to power the MAC. This takes a string in the format
537 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
540 string "Card detect pin for mmc0"
541 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
544 Set the card detect pin for mmc0, leave empty to not use cd. This
545 takes a string in the format understood by sunxi_name_to_gpio, e.g.
546 PH1 for pin 1 of port H.
549 string "Card detect pin for mmc1"
552 See MMC0_CD_PIN help text.
555 string "Card detect pin for mmc2"
558 See MMC0_CD_PIN help text.
561 string "Card detect pin for mmc3"
564 See MMC0_CD_PIN help text.
567 string "Pins for mmc1"
570 Set the pins used for mmc1, when applicable. This takes a string in the
571 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
574 string "Pins for mmc2"
577 See MMC1_PINS help text.
580 string "Pins for mmc3"
583 See MMC1_PINS help text.
585 config MMC_SUNXI_SLOT_EXTRA
586 int "mmc extra slot number"
589 sunxi builds always enable mmc0, some boards also have a second sdcard
590 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
593 config INITIAL_USB_SCAN_DELAY
594 int "delay initial usb scan by x ms to allow builtin devices to init"
597 Some boards have on board usb devices which need longer than the
598 USB spec's 1 second to connect from board powerup. Set this config
599 option to a non 0 value to add an extra delay before the first usb
603 string "Vbus enable pin for usb0 (otg)"
606 Set the Vbus enable pin for usb0 (otg). This takes a string in the
607 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
610 string "Vbus detect pin for usb0 (otg)"
613 Set the Vbus detect pin for usb0 (otg). This takes a string in the
614 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
617 string "ID detect pin for usb0 (otg)"
620 Set the ID detect pin for usb0 (otg). This takes a string in the
621 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
624 string "Vbus enable pin for usb1 (ehci0)"
625 default "PH6" if MACH_SUN4I || MACH_SUN7I
626 default "PH27" if MACH_SUN6I
628 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
629 a string in the format understood by sunxi_name_to_gpio, e.g.
630 PH1 for pin 1 of port H.
633 string "Vbus enable pin for usb2 (ehci1)"
634 default "PH3" if MACH_SUN4I || MACH_SUN7I
635 default "PH24" if MACH_SUN6I
637 See USB1_VBUS_PIN help text.
640 string "Vbus enable pin for usb3 (ehci2)"
643 See USB1_VBUS_PIN help text.
646 bool "Enable I2C/TWI controller 0"
647 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
648 default n if MACH_SUN6I || MACH_SUN8I
651 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
652 its clock and setting up the bus. This is especially useful on devices
653 with slaves connected to the bus or with pins exposed through e.g. an
654 expansion port/header.
657 bool "Enable I2C/TWI controller 1"
661 See I2C0_ENABLE help text.
664 bool "Enable I2C/TWI controller 2"
668 See I2C0_ENABLE help text.
670 if MACH_SUN6I || MACH_SUN7I
672 bool "Enable I2C/TWI controller 3"
676 See I2C0_ENABLE help text.
681 bool "Enable the PRCM I2C/TWI controller"
682 # This is used for the pmic on H3
683 default y if SY8106A_POWER
686 Set this to y to enable the I2C controller which is part of the PRCM.
691 bool "Enable I2C/TWI controller 4"
695 See I2C0_ENABLE help text.
699 bool "Enable support for gpio-s on axp PMICs"
702 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
705 bool "Enable graphical uboot console on HDMI, LCD or VGA"
706 depends on !MACH_SUN8I_A83T
707 depends on !MACH_SUNXI_H3_H5
708 depends on !MACH_SUN8I_R40
709 depends on !MACH_SUN8I_V3S
710 depends on !MACH_SUN9I
711 depends on !MACH_SUN50I
713 imply VIDEO_DT_SIMPLEFB
716 Say Y here to add support for using a cfb console on the HDMI, LCD
717 or VGA output found on most sunxi devices. See doc/README.video for
718 info on how to select the video output and mode.
721 bool "HDMI output support"
722 depends on VIDEO_SUNXI && !MACH_SUN8I
725 Say Y here to add support for outputting video over HDMI.
728 bool "VGA output support"
729 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
732 Say Y here to add support for outputting video over VGA.
734 config VIDEO_VGA_VIA_LCD
735 bool "VGA via LCD controller support"
736 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
739 Say Y here to add support for external DACs connected to the parallel
740 LCD interface driving a VGA connector, such as found on the
743 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
744 bool "Force sync active high for VGA via LCD controller support"
745 depends on VIDEO_VGA_VIA_LCD
748 Say Y here if you've a board which uses opendrain drivers for the vga
749 hsync and vsync signals. Opendrain drivers cannot generate steep enough
750 positive edges for a stable video output, so on boards with opendrain
751 drivers the sync signals must always be active high.
753 config VIDEO_VGA_EXTERNAL_DAC_EN
754 string "LCD panel power enable pin"
755 depends on VIDEO_VGA_VIA_LCD
758 Set the enable pin for the external VGA DAC. This takes a string in the
759 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
761 config VIDEO_COMPOSITE
762 bool "Composite video output support"
763 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
766 Say Y here to add support for outputting composite video.
768 config VIDEO_LCD_MODE
769 string "LCD panel timing details"
770 depends on VIDEO_SUNXI
773 LCD panel timing details string, leave empty if there is no LCD panel.
774 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
775 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
776 Also see: http://linux-sunxi.org/LCD
778 config VIDEO_LCD_DCLK_PHASE
779 int "LCD panel display clock phase"
780 depends on VIDEO_SUNXI || DM_VIDEO
783 Select LCD panel display clock phase shift, range 0-3.
785 config VIDEO_LCD_POWER
786 string "LCD panel power enable pin"
787 depends on VIDEO_SUNXI
790 Set the power enable pin for the LCD panel. This takes a string in the
791 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
793 config VIDEO_LCD_RESET
794 string "LCD panel reset pin"
795 depends on VIDEO_SUNXI
798 Set the reset pin for the LCD panel. This takes a string in the format
799 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
801 config VIDEO_LCD_BL_EN
802 string "LCD panel backlight enable pin"
803 depends on VIDEO_SUNXI
806 Set the backlight enable pin for the LCD panel. This takes a string in the
807 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
810 config VIDEO_LCD_BL_PWM
811 string "LCD panel backlight pwm pin"
812 depends on VIDEO_SUNXI
815 Set the backlight pwm pin for the LCD panel. This takes a string in the
816 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
818 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
819 bool "LCD panel backlight pwm is inverted"
820 depends on VIDEO_SUNXI
823 Set this if the backlight pwm output is active low.
825 config VIDEO_LCD_PANEL_I2C
826 bool "LCD panel needs to be configured via i2c"
827 depends on VIDEO_SUNXI
831 Say y here if the LCD panel needs to be configured via i2c. This
832 will add a bitbang i2c controller using gpios to talk to the LCD.
834 config VIDEO_LCD_PANEL_I2C_SDA
835 string "LCD panel i2c interface SDA pin"
836 depends on VIDEO_LCD_PANEL_I2C
839 Set the SDA pin for the LCD i2c interface. This takes a string in the
840 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
842 config VIDEO_LCD_PANEL_I2C_SCL
843 string "LCD panel i2c interface SCL pin"
844 depends on VIDEO_LCD_PANEL_I2C
847 Set the SCL pin for the LCD i2c interface. This takes a string in the
848 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
851 # Note only one of these may be selected at a time! But hidden choices are
852 # not supported by Kconfig
853 config VIDEO_LCD_IF_PARALLEL
856 config VIDEO_LCD_IF_LVDS
864 bool "Display Engine 2 video driver"
868 imply VIDEO_DT_SIMPLEFB
871 Say y here if you want to build DE2 video driver which is present on
872 newer SoCs. Currently only HDMI output is supported.
876 prompt "LCD panel support"
877 depends on VIDEO_SUNXI
879 Select which type of LCD panel to support.
881 config VIDEO_LCD_PANEL_PARALLEL
882 bool "Generic parallel interface LCD panel"
883 select VIDEO_LCD_IF_PARALLEL
885 config VIDEO_LCD_PANEL_LVDS
886 bool "Generic lvds interface LCD panel"
887 select VIDEO_LCD_IF_LVDS
889 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
890 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
891 select VIDEO_LCD_SSD2828
892 select VIDEO_LCD_IF_PARALLEL
894 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
896 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
897 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
898 select VIDEO_LCD_ANX9804
899 select VIDEO_LCD_IF_PARALLEL
900 select VIDEO_LCD_PANEL_I2C
902 Select this for eDP LCD panels with 4 lanes running at 1.62G,
903 connected via an ANX9804 bridge chip.
905 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
906 bool "Hitachi tx18d42vm LCD panel"
907 select VIDEO_LCD_HITACHI_TX18D42VM
908 select VIDEO_LCD_IF_LVDS
910 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
912 config VIDEO_LCD_TL059WV5C0
913 bool "tl059wv5c0 LCD panel"
914 select VIDEO_LCD_PANEL_I2C
915 select VIDEO_LCD_IF_PARALLEL
917 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
918 Aigo M60/M608/M606 tablets.
923 string "SATA power pin"
926 Set the pins used to power the SATA. This takes a string in the
927 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
931 int "GMAC Transmit Clock Delay Chain"
934 Set the GMAC Transmit Clock Delay Chain value.
936 config SPL_STACK_R_ADDR
937 default 0x4fe00000 if MACH_SUN4I
938 default 0x4fe00000 if MACH_SUN5I
939 default 0x4fe00000 if MACH_SUN6I
940 default 0x4fe00000 if MACH_SUN7I
941 default 0x4fe00000 if MACH_SUN8I
942 default 0x2fe00000 if MACH_SUN9I
943 default 0x4fe00000 if MACH_SUN50I
946 bool "Support for SPI Flash on Allwinner SoCs in SPL"
947 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
949 Enable support for SPI Flash. This option allows SPL to read from
950 sunxi SPI Flash. It uses the same method as the boot ROM, so does
951 not need any extra configuration.