4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
155 select SUNXI_DRAM_DW_16BIT
157 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
160 bool "sun9i (Allwinner A80)"
162 select SUNXI_HIGH_SRAM
163 select SUNXI_GEN_SUN6I
167 bool "sun50i (Allwinner A64)"
171 select SUNXI_GEN_SUN6I
172 select SUNXI_HIGH_SRAM
175 select SUNXI_DRAM_DW_32BIT
179 config MACH_SUN50I_H5
180 bool "sun50i (Allwinner H5)"
182 select MACH_SUNXI_H3_H5
183 select SUNXI_HIGH_SRAM
189 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
192 default y if MACH_SUN8I_A23
193 default y if MACH_SUN8I_A33
194 default y if MACH_SUN8I_A83T
195 default y if MACH_SUNXI_H3_H5
196 default y if MACH_SUN8I_R40
197 default y if MACH_SUN8I_V3S
199 config RESERVE_ALLWINNER_BOOT0_HEADER
200 bool "reserve space for Allwinner boot0 header"
201 select ENABLE_ARM_SOC_BOOT0_HOOK
203 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
204 filled with magic values post build. The Allwinner provided boot0
205 blob relies on this information to load and execute U-Boot.
206 Only needed on 64-bit Allwinner boards so far when using boot0.
208 config ARM_BOOT_HOOK_RMR
212 select ENABLE_ARM_SOC_BOOT0_HOOK
214 Insert some ARM32 code at the very beginning of the U-Boot binary
215 which uses an RMR register write to bring the core into AArch64 mode.
216 The very first instruction acts as a switch, since it's carefully
217 chosen to be a NOP in one mode and a branch in the other, so the
218 code would only be executed if not already in AArch64.
219 This allows both the SPL and the U-Boot proper to be entered in
220 either mode and switch to AArch64 if needed.
223 config SUNXI_DRAM_DDR3
226 config SUNXI_DRAM_DDR2
229 config SUNXI_DRAM_LPDDR3
233 prompt "DRAM Type and Timing"
234 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
235 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
237 config SUNXI_DRAM_DDR3_1333
239 select SUNXI_DRAM_DDR3
240 depends on !MACH_SUN8I_V3S
242 This option is the original only supported memory type, which suits
243 many H3/H5/A64 boards available now.
245 config SUNXI_DRAM_LPDDR3_STOCK
246 bool "LPDDR3 with Allwinner stock configuration"
247 select SUNXI_DRAM_LPDDR3
249 This option is the LPDDR3 timing used by the stock boot0 by
252 config SUNXI_DRAM_DDR2_V3S
253 bool "DDR2 found in V3s chip"
254 select SUNXI_DRAM_DDR2
255 depends on MACH_SUN8I_V3S
257 This option is only for the DDR2 memory chip which is co-packaged in
264 int "sunxi dram type"
265 depends on MACH_SUN8I_A83T
268 Set the dram type, 3: DDR3, 7: LPDDR3
271 int "sunxi dram clock speed"
272 default 792 if MACH_SUN9I
273 default 648 if MACH_SUN8I_R40
274 default 312 if MACH_SUN6I || MACH_SUN8I
275 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
277 default 672 if MACH_SUN50I
279 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
280 must be a multiple of 24. For the sun9i (A80), the tested values
281 (for DDR3-1600) are 312 to 792.
283 if MACH_SUN5I || MACH_SUN7I
285 int "sunxi mbus clock speed"
288 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
293 int "sunxi dram zq value"
294 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
295 default 127 if MACH_SUN7I
296 default 14779 if MACH_SUN8I_V3S
297 default 3881979 if MACH_SUN8I_R40
298 default 4145117 if MACH_SUN9I
299 default 3881915 if MACH_SUN50I
301 Set the dram zq value.
304 bool "sunxi dram odt enable"
305 default n if !MACH_SUN8I_A23
306 default y if MACH_SUN8I_A23
307 default y if MACH_SUN8I_R40
308 default y if MACH_SUN50I
310 Select this to enable dram odt (on die termination).
312 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
314 int "sunxi dram emr1 value"
315 default 0 if MACH_SUN4I
316 default 4 if MACH_SUN5I || MACH_SUN7I
318 Set the dram controller emr1 value.
321 hex "sunxi dram tpr3 value"
324 Set the dram controller tpr3 parameter. This parameter configures
325 the delay on the command lane and also phase shifts, which are
326 applied for sampling incoming read data. The default value 0
327 means that no phase/delay adjustments are necessary. Properly
328 configuring this parameter increases reliability at high DRAM
331 config DRAM_DQS_GATING_DELAY
332 hex "sunxi dram dqs_gating_delay value"
335 Set the dram controller dqs_gating_delay parmeter. Each byte
336 encodes the DQS gating delay for each byte lane. The delay
337 granularity is 1/4 cycle. For example, the value 0x05060606
338 means that the delay is 5 quarter-cycles for one lane (1.25
339 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
340 The default value 0 means autodetection. The results of hardware
341 autodetection are not very reliable and depend on the chip
342 temperature (sometimes producing different results on cold start
343 and warm reboot). But the accuracy of hardware autodetection
344 is usually good enough, unless running at really high DRAM
345 clocks speeds (up to 600MHz). If unsure, keep as 0.
348 prompt "sunxi dram timings"
349 default DRAM_TIMINGS_VENDOR_MAGIC
351 Select the timings of the DDR3 chips.
353 config DRAM_TIMINGS_VENDOR_MAGIC
354 bool "Magic vendor timings from Android"
356 The same DRAM timings as in the Allwinner boot0 bootloader.
358 config DRAM_TIMINGS_DDR3_1066F_1333H
359 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
361 Use the timings of the standard JEDEC DDR3-1066F speed bin for
362 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
363 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
364 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
365 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
366 that down binning to DDR3-1066F is supported (because DDR3-1066F
367 uses a bit faster timings than DDR3-1333H).
369 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
370 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
372 Use the timings of the slowest possible JEDEC speed bin for the
373 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
374 DDR3-800E, DDR3-1066G or DDR3-1333J.
381 config DRAM_ODT_CORRECTION
382 int "sunxi dram odt correction value"
385 Set the dram odt correction value (range -255 - 255). In allwinner
386 fex files, this option is found in bits 8-15 of the u32 odt_en variable
387 in the [dram] section. When bit 31 of the odt_en variable is set
388 then the correction is negative. Usually the value for this is 0.
392 default 1008000000 if MACH_SUN4I
393 default 1008000000 if MACH_SUN5I
394 default 1008000000 if MACH_SUN6I
395 default 912000000 if MACH_SUN7I
396 default 1008000000 if MACH_SUN8I
397 default 1008000000 if MACH_SUN9I
398 default 816000000 if MACH_SUN50I
400 config SYS_CONFIG_NAME
401 default "sun4i" if MACH_SUN4I
402 default "sun5i" if MACH_SUN5I
403 default "sun6i" if MACH_SUN6I
404 default "sun7i" if MACH_SUN7I
405 default "sun8i" if MACH_SUN8I
406 default "sun9i" if MACH_SUN9I
407 default "sun50i" if MACH_SUN50I
416 bool "UART0 on MicroSD breakout board"
419 Repurpose the SD card slot for getting access to the UART0 serial
420 console. Primarily useful only for low level u-boot debugging on
421 tablets, where normal UART0 is difficult to access and requires
422 device disassembly and/or soldering. As the SD card can't be used
423 at the same time, the system can be only booted in the FEL mode.
424 Only enable this if you really know what you are doing.
426 config OLD_SUNXI_KERNEL_COMPAT
427 bool "Enable workarounds for booting old kernels"
430 Set this to enable various workarounds for old kernels, this results in
431 sub-optimal settings for newer kernels, only enable if needed.
434 string "MAC power pin"
437 Set the pin used to power the MAC. This takes a string in the format
438 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
441 string "Card detect pin for mmc0"
442 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
445 Set the card detect pin for mmc0, leave empty to not use cd. This
446 takes a string in the format understood by sunxi_name_to_gpio, e.g.
447 PH1 for pin 1 of port H.
450 string "Card detect pin for mmc1"
453 See MMC0_CD_PIN help text.
456 string "Card detect pin for mmc2"
459 See MMC0_CD_PIN help text.
462 string "Card detect pin for mmc3"
465 See MMC0_CD_PIN help text.
468 string "Pins for mmc1"
471 Set the pins used for mmc1, when applicable. This takes a string in the
472 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
475 string "Pins for mmc2"
478 See MMC1_PINS help text.
481 string "Pins for mmc3"
484 See MMC1_PINS help text.
486 config MMC_SUNXI_SLOT_EXTRA
487 int "mmc extra slot number"
490 sunxi builds always enable mmc0, some boards also have a second sdcard
491 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
494 config INITIAL_USB_SCAN_DELAY
495 int "delay initial usb scan by x ms to allow builtin devices to init"
498 Some boards have on board usb devices which need longer than the
499 USB spec's 1 second to connect from board powerup. Set this config
500 option to a non 0 value to add an extra delay before the first usb
504 string "Vbus enable pin for usb0 (otg)"
507 Set the Vbus enable pin for usb0 (otg). This takes a string in the
508 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
511 string "Vbus detect pin for usb0 (otg)"
514 Set the Vbus detect pin for usb0 (otg). This takes a string in the
515 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
518 string "ID detect pin for usb0 (otg)"
521 Set the ID detect pin for usb0 (otg). This takes a string in the
522 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
525 string "Vbus enable pin for usb1 (ehci0)"
526 default "PH6" if MACH_SUN4I || MACH_SUN7I
527 default "PH27" if MACH_SUN6I
529 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
530 a string in the format understood by sunxi_name_to_gpio, e.g.
531 PH1 for pin 1 of port H.
534 string "Vbus enable pin for usb2 (ehci1)"
535 default "PH3" if MACH_SUN4I || MACH_SUN7I
536 default "PH24" if MACH_SUN6I
538 See USB1_VBUS_PIN help text.
541 string "Vbus enable pin for usb3 (ehci2)"
544 See USB1_VBUS_PIN help text.
547 bool "Enable I2C/TWI controller 0"
548 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
549 default n if MACH_SUN6I || MACH_SUN8I
552 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
553 its clock and setting up the bus. This is especially useful on devices
554 with slaves connected to the bus or with pins exposed through e.g. an
555 expansion port/header.
558 bool "Enable I2C/TWI controller 1"
562 See I2C0_ENABLE help text.
565 bool "Enable I2C/TWI controller 2"
569 See I2C0_ENABLE help text.
571 if MACH_SUN6I || MACH_SUN7I
573 bool "Enable I2C/TWI controller 3"
577 See I2C0_ENABLE help text.
582 bool "Enable the PRCM I2C/TWI controller"
583 # This is used for the pmic on H3
584 default y if SY8106A_POWER
587 Set this to y to enable the I2C controller which is part of the PRCM.
592 bool "Enable I2C/TWI controller 4"
596 See I2C0_ENABLE help text.
600 bool "Enable support for gpio-s on axp PMICs"
603 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
606 bool "Enable graphical uboot console on HDMI, LCD or VGA"
607 depends on !MACH_SUN8I_A83T
608 depends on !MACH_SUNXI_H3_H5
609 depends on !MACH_SUN8I_R40
610 depends on !MACH_SUN8I_V3S
611 depends on !MACH_SUN9I
612 depends on !MACH_SUN50I
615 Say Y here to add support for using a cfb console on the HDMI, LCD
616 or VGA output found on most sunxi devices. See doc/README.video for
617 info on how to select the video output and mode.
620 bool "HDMI output support"
621 depends on VIDEO && !MACH_SUN8I
624 Say Y here to add support for outputting video over HDMI.
627 bool "VGA output support"
628 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
631 Say Y here to add support for outputting video over VGA.
633 config VIDEO_VGA_VIA_LCD
634 bool "VGA via LCD controller support"
635 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
638 Say Y here to add support for external DACs connected to the parallel
639 LCD interface driving a VGA connector, such as found on the
642 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
643 bool "Force sync active high for VGA via LCD controller support"
644 depends on VIDEO_VGA_VIA_LCD
647 Say Y here if you've a board which uses opendrain drivers for the vga
648 hsync and vsync signals. Opendrain drivers cannot generate steep enough
649 positive edges for a stable video output, so on boards with opendrain
650 drivers the sync signals must always be active high.
652 config VIDEO_VGA_EXTERNAL_DAC_EN
653 string "LCD panel power enable pin"
654 depends on VIDEO_VGA_VIA_LCD
657 Set the enable pin for the external VGA DAC. This takes a string in the
658 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
660 config VIDEO_COMPOSITE
661 bool "Composite video output support"
662 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
665 Say Y here to add support for outputting composite video.
667 config VIDEO_LCD_MODE
668 string "LCD panel timing details"
672 LCD panel timing details string, leave empty if there is no LCD panel.
673 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
674 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
675 Also see: http://linux-sunxi.org/LCD
677 config VIDEO_LCD_DCLK_PHASE
678 int "LCD panel display clock phase"
682 Select LCD panel display clock phase shift, range 0-3.
684 config VIDEO_LCD_POWER
685 string "LCD panel power enable pin"
689 Set the power enable pin for the LCD panel. This takes a string in the
690 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
692 config VIDEO_LCD_RESET
693 string "LCD panel reset pin"
697 Set the reset pin for the LCD panel. This takes a string in the format
698 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
700 config VIDEO_LCD_BL_EN
701 string "LCD panel backlight enable pin"
705 Set the backlight enable pin for the LCD panel. This takes a string in the
706 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
709 config VIDEO_LCD_BL_PWM
710 string "LCD panel backlight pwm pin"
714 Set the backlight pwm pin for the LCD panel. This takes a string in the
715 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
717 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
718 bool "LCD panel backlight pwm is inverted"
722 Set this if the backlight pwm output is active low.
724 config VIDEO_LCD_PANEL_I2C
725 bool "LCD panel needs to be configured via i2c"
730 Say y here if the LCD panel needs to be configured via i2c. This
731 will add a bitbang i2c controller using gpios to talk to the LCD.
733 config VIDEO_LCD_PANEL_I2C_SDA
734 string "LCD panel i2c interface SDA pin"
735 depends on VIDEO_LCD_PANEL_I2C
738 Set the SDA pin for the LCD i2c interface. This takes a string in the
739 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
741 config VIDEO_LCD_PANEL_I2C_SCL
742 string "LCD panel i2c interface SCL pin"
743 depends on VIDEO_LCD_PANEL_I2C
746 Set the SCL pin for the LCD i2c interface. This takes a string in the
747 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
750 # Note only one of these may be selected at a time! But hidden choices are
751 # not supported by Kconfig
752 config VIDEO_LCD_IF_PARALLEL
755 config VIDEO_LCD_IF_LVDS
763 bool "Display Engine 2 video driver"
769 Say y here if you want to build DE2 video driver which is present on
770 newer SoCs. Currently only HDMI output is supported.
774 prompt "LCD panel support"
777 Select which type of LCD panel to support.
779 config VIDEO_LCD_PANEL_PARALLEL
780 bool "Generic parallel interface LCD panel"
781 select VIDEO_LCD_IF_PARALLEL
783 config VIDEO_LCD_PANEL_LVDS
784 bool "Generic lvds interface LCD panel"
785 select VIDEO_LCD_IF_LVDS
787 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
788 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
789 select VIDEO_LCD_SSD2828
790 select VIDEO_LCD_IF_PARALLEL
792 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
794 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
795 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
796 select VIDEO_LCD_ANX9804
797 select VIDEO_LCD_IF_PARALLEL
798 select VIDEO_LCD_PANEL_I2C
800 Select this for eDP LCD panels with 4 lanes running at 1.62G,
801 connected via an ANX9804 bridge chip.
803 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
804 bool "Hitachi tx18d42vm LCD panel"
805 select VIDEO_LCD_HITACHI_TX18D42VM
806 select VIDEO_LCD_IF_LVDS
808 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
810 config VIDEO_LCD_TL059WV5C0
811 bool "tl059wv5c0 LCD panel"
812 select VIDEO_LCD_PANEL_I2C
813 select VIDEO_LCD_IF_PARALLEL
815 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
816 Aigo M60/M608/M606 tablets.
821 string "SATA power pin"
824 Set the pins used to power the SATA. This takes a string in the
825 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
829 int "GMAC Transmit Clock Delay Chain"
832 Set the GMAC Transmit Clock Delay Chain value.
834 config SPL_STACK_R_ADDR
835 default 0x4fe00000 if MACH_SUN4I
836 default 0x4fe00000 if MACH_SUN5I
837 default 0x4fe00000 if MACH_SUN6I
838 default 0x4fe00000 if MACH_SUN7I
839 default 0x4fe00000 if MACH_SUN8I
840 default 0x2fe00000 if MACH_SUN9I
841 default 0x4fe00000 if MACH_SUN50I