4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun9i platforms,
28 bool "Allwinner sun6i internal P2WI controller"
30 If you say yes to this option, support will be included for the
31 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
33 The P2WI looks like an SMBus controller (which supports only byte
34 accesses), except that it only supports one slave device.
35 This interface is used to connect to specific PMIC devices (like the
41 Support for the PRCM (Power/Reset/Clock Management) unit available
45 bool "Sunxi AXP PMIC bus access helpers"
47 Select this PMIC bus access helpers for Sunxi platform PRCM or other
48 AXP family PMIC devices.
51 bool "Allwinner sunXi Reduced Serial Bus Driver"
53 Say y here to enable support for Allwinner's Reduced Serial Bus
54 (RSB) support. This controller is responsible for communicating
55 with various RSB based devices, such as AXP223, AXP8XX PMICs,
58 config SUNXI_HIGH_SRAM
62 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
63 with the first SRAM region being located at address 0.
64 Some newer SoCs map the boot ROM at address 0 instead and move the
65 SRAM to 64KB, just behind the mask ROM.
66 Chips using the latter setup are supposed to select this option to
67 adjust the addresses accordingly.
69 # Note only one of these may be selected at a time! But hidden choices are
70 # not supported by Kconfig
71 config SUNXI_GEN_SUN4I
74 Select this for sunxi SoCs which have resets and clocks set up
75 as the original A10 (mach-sun4i).
77 config SUNXI_GEN_SUN6I
80 Select this for sunxi SoCs which have sun6i like periphery, like
81 separate ahb reset control registers, custom pmic bus, new style
87 Select this for sunxi SoCs which uses a DRAM controller like the
88 DesignWare controller used in H3, mainly SoCs after H3, which do
89 not have official open-source DRAM initialization code, but can
90 use modified H3 DRAM initialization code.
93 config SUNXI_DRAM_DW_16BIT
96 Select this for sunxi SoCs with DesignWare DRAM controller and
97 have only 16-bit memory buswidth.
99 config SUNXI_DRAM_DW_32BIT
102 Select this for sunxi SoCs with DesignWare DRAM controller with
103 32-bit memory buswidth.
106 config MACH_SUNXI_H3_H5
111 select SUNXI_DRAM_DW_32BIT
112 select SUNXI_GEN_SUN6I
116 prompt "Sunxi SoC Variant"
120 bool "sun4i (Allwinner A10)"
122 select ARM_CORTEX_CPU_IS_UP
124 select SUNXI_GEN_SUN4I
128 bool "sun5i (Allwinner A13)"
130 select ARM_CORTEX_CPU_IS_UP
132 select SUNXI_GEN_SUN4I
134 imply CONS_INDEX_2 if !DM_SERIAL
137 bool "sun6i (Allwinner A31)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
145 select SUNXI_GEN_SUN6I
147 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
150 bool "sun7i (Allwinner A20)"
152 select CPU_V7_HAS_NONSEC
153 select CPU_V7_HAS_VIRT
154 select ARCH_SUPPORT_PSCI
156 select SUNXI_GEN_SUN4I
158 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
160 config MACH_SUN8I_A23
161 bool "sun8i (Allwinner A23)"
163 select CPU_V7_HAS_NONSEC
164 select CPU_V7_HAS_VIRT
165 select ARCH_SUPPORT_PSCI
166 select SUNXI_GEN_SUN6I
168 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
169 imply CONS_INDEX_5 if !DM_SERIAL
171 config MACH_SUN8I_A33
172 bool "sun8i (Allwinner A33)"
174 select CPU_V7_HAS_NONSEC
175 select CPU_V7_HAS_VIRT
176 select ARCH_SUPPORT_PSCI
177 select SUNXI_GEN_SUN6I
179 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
180 imply CONS_INDEX_5 if !DM_SERIAL
182 config MACH_SUN8I_A83T
183 bool "sun8i (Allwinner A83T)"
185 select SUNXI_GEN_SUN6I
186 select MMC_SUNXI_HAS_NEW_MODE
190 bool "sun8i (Allwinner H3)"
192 select CPU_V7_HAS_NONSEC
193 select CPU_V7_HAS_VIRT
194 select ARCH_SUPPORT_PSCI
195 select MACH_SUNXI_H3_H5
196 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
198 config MACH_SUN8I_R40
199 bool "sun8i (Allwinner R40)"
201 select CPU_V7_HAS_NONSEC
202 select CPU_V7_HAS_VIRT
203 select ARCH_SUPPORT_PSCI
204 select SUNXI_GEN_SUN6I
207 select SUNXI_DRAM_DW_32BIT
209 config MACH_SUN8I_V3S
210 bool "sun8i (Allwinner V3s)"
212 select CPU_V7_HAS_NONSEC
213 select CPU_V7_HAS_VIRT
214 select ARCH_SUPPORT_PSCI
215 select SUNXI_GEN_SUN6I
217 select SUNXI_DRAM_DW_16BIT
219 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
222 bool "sun9i (Allwinner A80)"
226 select SUNXI_HIGH_SRAM
227 select SUNXI_GEN_SUN6I
232 bool "sun50i (Allwinner A64)"
236 select SUNXI_GEN_SUN6I
237 select SUNXI_HIGH_SRAM
240 select SUNXI_DRAM_DW_32BIT
244 config MACH_SUN50I_H5
245 bool "sun50i (Allwinner H5)"
247 select MACH_SUNXI_H3_H5
248 select SUNXI_HIGH_SRAM
254 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
259 default y if MACH_SUN8I_A23
260 default y if MACH_SUN8I_A33
261 default y if MACH_SUN8I_A83T
262 default y if MACH_SUNXI_H3_H5
263 default y if MACH_SUN8I_R40
264 default y if MACH_SUN8I_V3S
266 config RESERVE_ALLWINNER_BOOT0_HEADER
267 bool "reserve space for Allwinner boot0 header"
268 select ENABLE_ARM_SOC_BOOT0_HOOK
270 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
271 filled with magic values post build. The Allwinner provided boot0
272 blob relies on this information to load and execute U-Boot.
273 Only needed on 64-bit Allwinner boards so far when using boot0.
275 config ARM_BOOT_HOOK_RMR
279 select ENABLE_ARM_SOC_BOOT0_HOOK
281 Insert some ARM32 code at the very beginning of the U-Boot binary
282 which uses an RMR register write to bring the core into AArch64 mode.
283 The very first instruction acts as a switch, since it's carefully
284 chosen to be a NOP in one mode and a branch in the other, so the
285 code would only be executed if not already in AArch64.
286 This allows both the SPL and the U-Boot proper to be entered in
287 either mode and switch to AArch64 if needed.
290 config SUNXI_DRAM_DDR3
293 config SUNXI_DRAM_DDR2
296 config SUNXI_DRAM_LPDDR3
300 prompt "DRAM Type and Timing"
301 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
302 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
304 config SUNXI_DRAM_DDR3_1333
306 select SUNXI_DRAM_DDR3
307 depends on !MACH_SUN8I_V3S
309 This option is the original only supported memory type, which suits
310 many H3/H5/A64 boards available now.
312 config SUNXI_DRAM_LPDDR3_STOCK
313 bool "LPDDR3 with Allwinner stock configuration"
314 select SUNXI_DRAM_LPDDR3
316 This option is the LPDDR3 timing used by the stock boot0 by
319 config SUNXI_DRAM_DDR2_V3S
320 bool "DDR2 found in V3s chip"
321 select SUNXI_DRAM_DDR2
322 depends on MACH_SUN8I_V3S
324 This option is only for the DDR2 memory chip which is co-packaged in
331 int "sunxi dram type"
332 depends on MACH_SUN8I_A83T
335 Set the dram type, 3: DDR3, 7: LPDDR3
338 int "sunxi dram clock speed"
339 default 792 if MACH_SUN9I
340 default 648 if MACH_SUN8I_R40
341 default 312 if MACH_SUN6I || MACH_SUN8I
342 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
344 default 672 if MACH_SUN50I
346 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
347 must be a multiple of 24. For the sun9i (A80), the tested values
348 (for DDR3-1600) are 312 to 792.
350 if MACH_SUN5I || MACH_SUN7I
352 int "sunxi mbus clock speed"
355 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
360 int "sunxi dram zq value"
361 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
362 default 127 if MACH_SUN7I
363 default 14779 if MACH_SUN8I_V3S
364 default 3881979 if MACH_SUN8I_R40
365 default 4145117 if MACH_SUN9I
366 default 3881915 if MACH_SUN50I
368 Set the dram zq value.
371 bool "sunxi dram odt enable"
372 default n if !MACH_SUN8I_A23
373 default y if MACH_SUN8I_A23
374 default y if MACH_SUN8I_R40
375 default y if MACH_SUN50I
377 Select this to enable dram odt (on die termination).
379 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
381 int "sunxi dram emr1 value"
382 default 0 if MACH_SUN4I
383 default 4 if MACH_SUN5I || MACH_SUN7I
385 Set the dram controller emr1 value.
388 hex "sunxi dram tpr3 value"
391 Set the dram controller tpr3 parameter. This parameter configures
392 the delay on the command lane and also phase shifts, which are
393 applied for sampling incoming read data. The default value 0
394 means that no phase/delay adjustments are necessary. Properly
395 configuring this parameter increases reliability at high DRAM
398 config DRAM_DQS_GATING_DELAY
399 hex "sunxi dram dqs_gating_delay value"
402 Set the dram controller dqs_gating_delay parmeter. Each byte
403 encodes the DQS gating delay for each byte lane. The delay
404 granularity is 1/4 cycle. For example, the value 0x05060606
405 means that the delay is 5 quarter-cycles for one lane (1.25
406 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
407 The default value 0 means autodetection. The results of hardware
408 autodetection are not very reliable and depend on the chip
409 temperature (sometimes producing different results on cold start
410 and warm reboot). But the accuracy of hardware autodetection
411 is usually good enough, unless running at really high DRAM
412 clocks speeds (up to 600MHz). If unsure, keep as 0.
415 prompt "sunxi dram timings"
416 default DRAM_TIMINGS_VENDOR_MAGIC
418 Select the timings of the DDR3 chips.
420 config DRAM_TIMINGS_VENDOR_MAGIC
421 bool "Magic vendor timings from Android"
423 The same DRAM timings as in the Allwinner boot0 bootloader.
425 config DRAM_TIMINGS_DDR3_1066F_1333H
426 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
428 Use the timings of the standard JEDEC DDR3-1066F speed bin for
429 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
430 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
431 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
432 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
433 that down binning to DDR3-1066F is supported (because DDR3-1066F
434 uses a bit faster timings than DDR3-1333H).
436 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
437 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
439 Use the timings of the slowest possible JEDEC speed bin for the
440 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
441 DDR3-800E, DDR3-1066G or DDR3-1333J.
448 config DRAM_ODT_CORRECTION
449 int "sunxi dram odt correction value"
452 Set the dram odt correction value (range -255 - 255). In allwinner
453 fex files, this option is found in bits 8-15 of the u32 odt_en variable
454 in the [dram] section. When bit 31 of the odt_en variable is set
455 then the correction is negative. Usually the value for this is 0.
459 default 1008000000 if MACH_SUN4I
460 default 1008000000 if MACH_SUN5I
461 default 1008000000 if MACH_SUN6I
462 default 912000000 if MACH_SUN7I
463 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
464 default 1008000000 if MACH_SUN8I
465 default 1008000000 if MACH_SUN9I
467 config SYS_CONFIG_NAME
468 default "sun4i" if MACH_SUN4I
469 default "sun5i" if MACH_SUN5I
470 default "sun6i" if MACH_SUN6I
471 default "sun7i" if MACH_SUN7I
472 default "sun8i" if MACH_SUN8I
473 default "sun9i" if MACH_SUN9I
474 default "sun50i" if MACH_SUN50I
483 bool "UART0 on MicroSD breakout board"
486 Repurpose the SD card slot for getting access to the UART0 serial
487 console. Primarily useful only for low level u-boot debugging on
488 tablets, where normal UART0 is difficult to access and requires
489 device disassembly and/or soldering. As the SD card can't be used
490 at the same time, the system can be only booted in the FEL mode.
491 Only enable this if you really know what you are doing.
493 config OLD_SUNXI_KERNEL_COMPAT
494 bool "Enable workarounds for booting old kernels"
497 Set this to enable various workarounds for old kernels, this results in
498 sub-optimal settings for newer kernels, only enable if needed.
501 string "MAC power pin"
504 Set the pin used to power the MAC. This takes a string in the format
505 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
508 string "Card detect pin for mmc0"
509 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
512 Set the card detect pin for mmc0, leave empty to not use cd. This
513 takes a string in the format understood by sunxi_name_to_gpio, e.g.
514 PH1 for pin 1 of port H.
517 string "Card detect pin for mmc1"
520 See MMC0_CD_PIN help text.
523 string "Card detect pin for mmc2"
526 See MMC0_CD_PIN help text.
529 string "Card detect pin for mmc3"
532 See MMC0_CD_PIN help text.
535 string "Pins for mmc1"
538 Set the pins used for mmc1, when applicable. This takes a string in the
539 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
542 string "Pins for mmc2"
545 See MMC1_PINS help text.
548 string "Pins for mmc3"
551 See MMC1_PINS help text.
553 config MMC_SUNXI_SLOT_EXTRA
554 int "mmc extra slot number"
557 sunxi builds always enable mmc0, some boards also have a second sdcard
558 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
561 config INITIAL_USB_SCAN_DELAY
562 int "delay initial usb scan by x ms to allow builtin devices to init"
565 Some boards have on board usb devices which need longer than the
566 USB spec's 1 second to connect from board powerup. Set this config
567 option to a non 0 value to add an extra delay before the first usb
571 string "Vbus enable pin for usb0 (otg)"
574 Set the Vbus enable pin for usb0 (otg). This takes a string in the
575 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
578 string "Vbus detect pin for usb0 (otg)"
581 Set the Vbus detect pin for usb0 (otg). This takes a string in the
582 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
585 string "ID detect pin for usb0 (otg)"
588 Set the ID detect pin for usb0 (otg). This takes a string in the
589 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
592 string "Vbus enable pin for usb1 (ehci0)"
593 default "PH6" if MACH_SUN4I || MACH_SUN7I
594 default "PH27" if MACH_SUN6I
596 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
597 a string in the format understood by sunxi_name_to_gpio, e.g.
598 PH1 for pin 1 of port H.
601 string "Vbus enable pin for usb2 (ehci1)"
602 default "PH3" if MACH_SUN4I || MACH_SUN7I
603 default "PH24" if MACH_SUN6I
605 See USB1_VBUS_PIN help text.
608 string "Vbus enable pin for usb3 (ehci2)"
611 See USB1_VBUS_PIN help text.
614 bool "Enable I2C/TWI controller 0"
615 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
616 default n if MACH_SUN6I || MACH_SUN8I
619 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
620 its clock and setting up the bus. This is especially useful on devices
621 with slaves connected to the bus or with pins exposed through e.g. an
622 expansion port/header.
625 bool "Enable I2C/TWI controller 1"
629 See I2C0_ENABLE help text.
632 bool "Enable I2C/TWI controller 2"
636 See I2C0_ENABLE help text.
638 if MACH_SUN6I || MACH_SUN7I
640 bool "Enable I2C/TWI controller 3"
644 See I2C0_ENABLE help text.
649 bool "Enable the PRCM I2C/TWI controller"
650 # This is used for the pmic on H3
651 default y if SY8106A_POWER
654 Set this to y to enable the I2C controller which is part of the PRCM.
659 bool "Enable I2C/TWI controller 4"
663 See I2C0_ENABLE help text.
667 bool "Enable support for gpio-s on axp PMICs"
670 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
673 bool "Enable graphical uboot console on HDMI, LCD or VGA"
674 depends on !MACH_SUN8I_A83T
675 depends on !MACH_SUNXI_H3_H5
676 depends on !MACH_SUN8I_R40
677 depends on !MACH_SUN8I_V3S
678 depends on !MACH_SUN9I
679 depends on !MACH_SUN50I
681 imply VIDEO_DT_SIMPLEFB
684 Say Y here to add support for using a cfb console on the HDMI, LCD
685 or VGA output found on most sunxi devices. See doc/README.video for
686 info on how to select the video output and mode.
689 bool "HDMI output support"
690 depends on VIDEO_SUNXI && !MACH_SUN8I
693 Say Y here to add support for outputting video over HDMI.
696 bool "VGA output support"
697 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
700 Say Y here to add support for outputting video over VGA.
702 config VIDEO_VGA_VIA_LCD
703 bool "VGA via LCD controller support"
704 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
707 Say Y here to add support for external DACs connected to the parallel
708 LCD interface driving a VGA connector, such as found on the
711 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
712 bool "Force sync active high for VGA via LCD controller support"
713 depends on VIDEO_VGA_VIA_LCD
716 Say Y here if you've a board which uses opendrain drivers for the vga
717 hsync and vsync signals. Opendrain drivers cannot generate steep enough
718 positive edges for a stable video output, so on boards with opendrain
719 drivers the sync signals must always be active high.
721 config VIDEO_VGA_EXTERNAL_DAC_EN
722 string "LCD panel power enable pin"
723 depends on VIDEO_VGA_VIA_LCD
726 Set the enable pin for the external VGA DAC. This takes a string in the
727 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
729 config VIDEO_COMPOSITE
730 bool "Composite video output support"
731 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
734 Say Y here to add support for outputting composite video.
736 config VIDEO_LCD_MODE
737 string "LCD panel timing details"
738 depends on VIDEO_SUNXI
741 LCD panel timing details string, leave empty if there is no LCD panel.
742 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
743 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
744 Also see: http://linux-sunxi.org/LCD
746 config VIDEO_LCD_DCLK_PHASE
747 int "LCD panel display clock phase"
748 depends on VIDEO_SUNXI || DM_VIDEO
751 Select LCD panel display clock phase shift, range 0-3.
753 config VIDEO_LCD_POWER
754 string "LCD panel power enable pin"
755 depends on VIDEO_SUNXI
758 Set the power enable pin for the LCD panel. This takes a string in the
759 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
761 config VIDEO_LCD_RESET
762 string "LCD panel reset pin"
763 depends on VIDEO_SUNXI
766 Set the reset pin for the LCD panel. This takes a string in the format
767 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
769 config VIDEO_LCD_BL_EN
770 string "LCD panel backlight enable pin"
771 depends on VIDEO_SUNXI
774 Set the backlight enable pin for the LCD panel. This takes a string in the
775 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
778 config VIDEO_LCD_BL_PWM
779 string "LCD panel backlight pwm pin"
780 depends on VIDEO_SUNXI
783 Set the backlight pwm pin for the LCD panel. This takes a string in the
784 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
786 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
787 bool "LCD panel backlight pwm is inverted"
788 depends on VIDEO_SUNXI
791 Set this if the backlight pwm output is active low.
793 config VIDEO_LCD_PANEL_I2C
794 bool "LCD panel needs to be configured via i2c"
795 depends on VIDEO_SUNXI
799 Say y here if the LCD panel needs to be configured via i2c. This
800 will add a bitbang i2c controller using gpios to talk to the LCD.
802 config VIDEO_LCD_PANEL_I2C_SDA
803 string "LCD panel i2c interface SDA pin"
804 depends on VIDEO_LCD_PANEL_I2C
807 Set the SDA pin for the LCD i2c interface. This takes a string in the
808 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
810 config VIDEO_LCD_PANEL_I2C_SCL
811 string "LCD panel i2c interface SCL pin"
812 depends on VIDEO_LCD_PANEL_I2C
815 Set the SCL pin for the LCD i2c interface. This takes a string in the
816 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
819 # Note only one of these may be selected at a time! But hidden choices are
820 # not supported by Kconfig
821 config VIDEO_LCD_IF_PARALLEL
824 config VIDEO_LCD_IF_LVDS
832 bool "Display Engine 2 video driver"
836 imply VIDEO_DT_SIMPLEFB
839 Say y here if you want to build DE2 video driver which is present on
840 newer SoCs. Currently only HDMI output is supported.
844 prompt "LCD panel support"
845 depends on VIDEO_SUNXI
847 Select which type of LCD panel to support.
849 config VIDEO_LCD_PANEL_PARALLEL
850 bool "Generic parallel interface LCD panel"
851 select VIDEO_LCD_IF_PARALLEL
853 config VIDEO_LCD_PANEL_LVDS
854 bool "Generic lvds interface LCD panel"
855 select VIDEO_LCD_IF_LVDS
857 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
858 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
859 select VIDEO_LCD_SSD2828
860 select VIDEO_LCD_IF_PARALLEL
862 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
864 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
865 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
866 select VIDEO_LCD_ANX9804
867 select VIDEO_LCD_IF_PARALLEL
868 select VIDEO_LCD_PANEL_I2C
870 Select this for eDP LCD panels with 4 lanes running at 1.62G,
871 connected via an ANX9804 bridge chip.
873 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
874 bool "Hitachi tx18d42vm LCD panel"
875 select VIDEO_LCD_HITACHI_TX18D42VM
876 select VIDEO_LCD_IF_LVDS
878 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
880 config VIDEO_LCD_TL059WV5C0
881 bool "tl059wv5c0 LCD panel"
882 select VIDEO_LCD_PANEL_I2C
883 select VIDEO_LCD_IF_PARALLEL
885 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
886 Aigo M60/M608/M606 tablets.
891 string "SATA power pin"
894 Set the pins used to power the SATA. This takes a string in the
895 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
899 int "GMAC Transmit Clock Delay Chain"
902 Set the GMAC Transmit Clock Delay Chain value.
904 config SPL_STACK_R_ADDR
905 default 0x4fe00000 if MACH_SUN4I
906 default 0x4fe00000 if MACH_SUN5I
907 default 0x4fe00000 if MACH_SUN6I
908 default 0x4fe00000 if MACH_SUN7I
909 default 0x4fe00000 if MACH_SUN8I
910 default 0x2fe00000 if MACH_SUN9I
911 default 0x4fe00000 if MACH_SUN50I
914 bool "Support for SPI Flash on Allwinner SoCs in SPL"
915 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
917 Enable support for SPI Flash. This option allows SPL to read from
918 sunxi SPI Flash. It uses the same method as the boot ROM, so does
919 not need any extra configuration.