4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
154 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
157 bool "sun9i (Allwinner A80)"
159 select SUNXI_HIGH_SRAM
160 select SUNXI_GEN_SUN6I
164 bool "sun50i (Allwinner A64)"
168 select SUNXI_GEN_SUN6I
169 select SUNXI_HIGH_SRAM
172 select SUNXI_DRAM_DW_32BIT
176 config MACH_SUN50I_H5
177 bool "sun50i (Allwinner H5)"
179 select MACH_SUNXI_H3_H5
180 select SUNXI_HIGH_SRAM
186 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
189 default y if MACH_SUN8I_A23
190 default y if MACH_SUN8I_A33
191 default y if MACH_SUN8I_A83T
192 default y if MACH_SUNXI_H3_H5
193 default y if MACH_SUN8I_R40
194 default y if MACH_SUN8I_V3S
196 config RESERVE_ALLWINNER_BOOT0_HEADER
197 bool "reserve space for Allwinner boot0 header"
198 select ENABLE_ARM_SOC_BOOT0_HOOK
200 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
201 filled with magic values post build. The Allwinner provided boot0
202 blob relies on this information to load and execute U-Boot.
203 Only needed on 64-bit Allwinner boards so far when using boot0.
205 config ARM_BOOT_HOOK_RMR
209 select ENABLE_ARM_SOC_BOOT0_HOOK
211 Insert some ARM32 code at the very beginning of the U-Boot binary
212 which uses an RMR register write to bring the core into AArch64 mode.
213 The very first instruction acts as a switch, since it's carefully
214 chosen to be a NOP in one mode and a branch in the other, so the
215 code would only be executed if not already in AArch64.
216 This allows both the SPL and the U-Boot proper to be entered in
217 either mode and switch to AArch64 if needed.
220 config SUNXI_DRAM_DDR3
223 config SUNXI_DRAM_DDR2
227 prompt "DRAM Type and Timing"
228 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
229 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
231 config SUNXI_DRAM_DDR3_1333
233 select SUNXI_DRAM_DDR3
234 depends on !MACH_SUN8I_V3S
236 This option is the original only supported memory type, which suits
237 many H3/H5/A64 boards available now.
239 config SUNXI_DRAM_DDR2_V3S
240 bool "DDR2 found in V3s chip"
241 select SUNXI_DRAM_DDR2
242 depends on MACH_SUN8I_V3S
244 This option is only for the DDR2 memory chip which is co-packaged in
251 int "sunxi dram type"
252 depends on MACH_SUN8I_A83T
255 Set the dram type, 3: DDR3, 7: LPDDR3
258 int "sunxi dram clock speed"
259 default 792 if MACH_SUN9I
260 default 648 if MACH_SUN8I_R40
261 default 312 if MACH_SUN6I || MACH_SUN8I
262 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
263 default 672 if MACH_SUN50I
265 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
266 must be a multiple of 24. For the sun9i (A80), the tested values
267 (for DDR3-1600) are 312 to 792.
269 if MACH_SUN5I || MACH_SUN7I
271 int "sunxi mbus clock speed"
274 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
279 int "sunxi dram zq value"
280 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
281 default 127 if MACH_SUN7I
282 default 3881979 if MACH_SUN8I_R40
283 default 4145117 if MACH_SUN9I
284 default 3881915 if MACH_SUN50I
286 Set the dram zq value.
289 bool "sunxi dram odt enable"
290 default n if !MACH_SUN8I_A23
291 default y if MACH_SUN8I_A23
292 default y if MACH_SUN8I_R40
293 default y if MACH_SUN50I
295 Select this to enable dram odt (on die termination).
297 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
299 int "sunxi dram emr1 value"
300 default 0 if MACH_SUN4I
301 default 4 if MACH_SUN5I || MACH_SUN7I
303 Set the dram controller emr1 value.
306 hex "sunxi dram tpr3 value"
309 Set the dram controller tpr3 parameter. This parameter configures
310 the delay on the command lane and also phase shifts, which are
311 applied for sampling incoming read data. The default value 0
312 means that no phase/delay adjustments are necessary. Properly
313 configuring this parameter increases reliability at high DRAM
316 config DRAM_DQS_GATING_DELAY
317 hex "sunxi dram dqs_gating_delay value"
320 Set the dram controller dqs_gating_delay parmeter. Each byte
321 encodes the DQS gating delay for each byte lane. The delay
322 granularity is 1/4 cycle. For example, the value 0x05060606
323 means that the delay is 5 quarter-cycles for one lane (1.25
324 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
325 The default value 0 means autodetection. The results of hardware
326 autodetection are not very reliable and depend on the chip
327 temperature (sometimes producing different results on cold start
328 and warm reboot). But the accuracy of hardware autodetection
329 is usually good enough, unless running at really high DRAM
330 clocks speeds (up to 600MHz). If unsure, keep as 0.
333 prompt "sunxi dram timings"
334 default DRAM_TIMINGS_VENDOR_MAGIC
336 Select the timings of the DDR3 chips.
338 config DRAM_TIMINGS_VENDOR_MAGIC
339 bool "Magic vendor timings from Android"
341 The same DRAM timings as in the Allwinner boot0 bootloader.
343 config DRAM_TIMINGS_DDR3_1066F_1333H
344 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
346 Use the timings of the standard JEDEC DDR3-1066F speed bin for
347 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
348 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
349 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
350 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
351 that down binning to DDR3-1066F is supported (because DDR3-1066F
352 uses a bit faster timings than DDR3-1333H).
354 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
355 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
357 Use the timings of the slowest possible JEDEC speed bin for the
358 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
359 DDR3-800E, DDR3-1066G or DDR3-1333J.
366 config DRAM_ODT_CORRECTION
367 int "sunxi dram odt correction value"
370 Set the dram odt correction value (range -255 - 255). In allwinner
371 fex files, this option is found in bits 8-15 of the u32 odt_en variable
372 in the [dram] section. When bit 31 of the odt_en variable is set
373 then the correction is negative. Usually the value for this is 0.
377 default 1008000000 if MACH_SUN4I
378 default 1008000000 if MACH_SUN5I
379 default 1008000000 if MACH_SUN6I
380 default 912000000 if MACH_SUN7I
381 default 1008000000 if MACH_SUN8I
382 default 1008000000 if MACH_SUN9I
383 default 816000000 if MACH_SUN50I
385 config SYS_CONFIG_NAME
386 default "sun4i" if MACH_SUN4I
387 default "sun5i" if MACH_SUN5I
388 default "sun6i" if MACH_SUN6I
389 default "sun7i" if MACH_SUN7I
390 default "sun8i" if MACH_SUN8I
391 default "sun9i" if MACH_SUN9I
392 default "sun50i" if MACH_SUN50I
401 bool "UART0 on MicroSD breakout board"
404 Repurpose the SD card slot for getting access to the UART0 serial
405 console. Primarily useful only for low level u-boot debugging on
406 tablets, where normal UART0 is difficult to access and requires
407 device disassembly and/or soldering. As the SD card can't be used
408 at the same time, the system can be only booted in the FEL mode.
409 Only enable this if you really know what you are doing.
411 config OLD_SUNXI_KERNEL_COMPAT
412 bool "Enable workarounds for booting old kernels"
415 Set this to enable various workarounds for old kernels, this results in
416 sub-optimal settings for newer kernels, only enable if needed.
419 string "MAC power pin"
422 Set the pin used to power the MAC. This takes a string in the format
423 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
426 string "Card detect pin for mmc0"
427 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
430 Set the card detect pin for mmc0, leave empty to not use cd. This
431 takes a string in the format understood by sunxi_name_to_gpio, e.g.
432 PH1 for pin 1 of port H.
435 string "Card detect pin for mmc1"
438 See MMC0_CD_PIN help text.
441 string "Card detect pin for mmc2"
444 See MMC0_CD_PIN help text.
447 string "Card detect pin for mmc3"
450 See MMC0_CD_PIN help text.
453 string "Pins for mmc1"
456 Set the pins used for mmc1, when applicable. This takes a string in the
457 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
460 string "Pins for mmc2"
463 See MMC1_PINS help text.
466 string "Pins for mmc3"
469 See MMC1_PINS help text.
471 config MMC_SUNXI_SLOT_EXTRA
472 int "mmc extra slot number"
475 sunxi builds always enable mmc0, some boards also have a second sdcard
476 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
479 config INITIAL_USB_SCAN_DELAY
480 int "delay initial usb scan by x ms to allow builtin devices to init"
483 Some boards have on board usb devices which need longer than the
484 USB spec's 1 second to connect from board powerup. Set this config
485 option to a non 0 value to add an extra delay before the first usb
489 string "Vbus enable pin for usb0 (otg)"
492 Set the Vbus enable pin for usb0 (otg). This takes a string in the
493 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
496 string "Vbus detect pin for usb0 (otg)"
499 Set the Vbus detect pin for usb0 (otg). This takes a string in the
500 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
503 string "ID detect pin for usb0 (otg)"
506 Set the ID detect pin for usb0 (otg). This takes a string in the
507 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
510 string "Vbus enable pin for usb1 (ehci0)"
511 default "PH6" if MACH_SUN4I || MACH_SUN7I
512 default "PH27" if MACH_SUN6I
514 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
515 a string in the format understood by sunxi_name_to_gpio, e.g.
516 PH1 for pin 1 of port H.
519 string "Vbus enable pin for usb2 (ehci1)"
520 default "PH3" if MACH_SUN4I || MACH_SUN7I
521 default "PH24" if MACH_SUN6I
523 See USB1_VBUS_PIN help text.
526 string "Vbus enable pin for usb3 (ehci2)"
529 See USB1_VBUS_PIN help text.
532 bool "Enable I2C/TWI controller 0"
533 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
534 default n if MACH_SUN6I || MACH_SUN8I
537 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
538 its clock and setting up the bus. This is especially useful on devices
539 with slaves connected to the bus or with pins exposed through e.g. an
540 expansion port/header.
543 bool "Enable I2C/TWI controller 1"
547 See I2C0_ENABLE help text.
550 bool "Enable I2C/TWI controller 2"
554 See I2C0_ENABLE help text.
556 if MACH_SUN6I || MACH_SUN7I
558 bool "Enable I2C/TWI controller 3"
562 See I2C0_ENABLE help text.
567 bool "Enable the PRCM I2C/TWI controller"
568 # This is used for the pmic on H3
569 default y if SY8106A_POWER
572 Set this to y to enable the I2C controller which is part of the PRCM.
577 bool "Enable I2C/TWI controller 4"
581 See I2C0_ENABLE help text.
585 bool "Enable support for gpio-s on axp PMICs"
588 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
591 bool "Enable graphical uboot console on HDMI, LCD or VGA"
592 depends on !MACH_SUN8I_A83T
593 depends on !MACH_SUNXI_H3_H5
594 depends on !MACH_SUN8I_R40
595 depends on !MACH_SUN8I_V3S
596 depends on !MACH_SUN9I
597 depends on !MACH_SUN50I
600 Say Y here to add support for using a cfb console on the HDMI, LCD
601 or VGA output found on most sunxi devices. See doc/README.video for
602 info on how to select the video output and mode.
605 bool "HDMI output support"
606 depends on VIDEO && !MACH_SUN8I
609 Say Y here to add support for outputting video over HDMI.
612 bool "VGA output support"
613 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
616 Say Y here to add support for outputting video over VGA.
618 config VIDEO_VGA_VIA_LCD
619 bool "VGA via LCD controller support"
620 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
623 Say Y here to add support for external DACs connected to the parallel
624 LCD interface driving a VGA connector, such as found on the
627 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
628 bool "Force sync active high for VGA via LCD controller support"
629 depends on VIDEO_VGA_VIA_LCD
632 Say Y here if you've a board which uses opendrain drivers for the vga
633 hsync and vsync signals. Opendrain drivers cannot generate steep enough
634 positive edges for a stable video output, so on boards with opendrain
635 drivers the sync signals must always be active high.
637 config VIDEO_VGA_EXTERNAL_DAC_EN
638 string "LCD panel power enable pin"
639 depends on VIDEO_VGA_VIA_LCD
642 Set the enable pin for the external VGA DAC. This takes a string in the
643 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
645 config VIDEO_COMPOSITE
646 bool "Composite video output support"
647 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
650 Say Y here to add support for outputting composite video.
652 config VIDEO_LCD_MODE
653 string "LCD panel timing details"
657 LCD panel timing details string, leave empty if there is no LCD panel.
658 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
659 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
660 Also see: http://linux-sunxi.org/LCD
662 config VIDEO_LCD_DCLK_PHASE
663 int "LCD panel display clock phase"
667 Select LCD panel display clock phase shift, range 0-3.
669 config VIDEO_LCD_POWER
670 string "LCD panel power enable pin"
674 Set the power enable pin for the LCD panel. This takes a string in the
675 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
677 config VIDEO_LCD_RESET
678 string "LCD panel reset pin"
682 Set the reset pin for the LCD panel. This takes a string in the format
683 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
685 config VIDEO_LCD_BL_EN
686 string "LCD panel backlight enable pin"
690 Set the backlight enable pin for the LCD panel. This takes a string in the
691 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
694 config VIDEO_LCD_BL_PWM
695 string "LCD panel backlight pwm pin"
699 Set the backlight pwm pin for the LCD panel. This takes a string in the
700 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
702 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
703 bool "LCD panel backlight pwm is inverted"
707 Set this if the backlight pwm output is active low.
709 config VIDEO_LCD_PANEL_I2C
710 bool "LCD panel needs to be configured via i2c"
715 Say y here if the LCD panel needs to be configured via i2c. This
716 will add a bitbang i2c controller using gpios to talk to the LCD.
718 config VIDEO_LCD_PANEL_I2C_SDA
719 string "LCD panel i2c interface SDA pin"
720 depends on VIDEO_LCD_PANEL_I2C
723 Set the SDA pin for the LCD i2c interface. This takes a string in the
724 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
726 config VIDEO_LCD_PANEL_I2C_SCL
727 string "LCD panel i2c interface SCL pin"
728 depends on VIDEO_LCD_PANEL_I2C
731 Set the SCL pin for the LCD i2c interface. This takes a string in the
732 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
735 # Note only one of these may be selected at a time! But hidden choices are
736 # not supported by Kconfig
737 config VIDEO_LCD_IF_PARALLEL
740 config VIDEO_LCD_IF_LVDS
748 bool "Display Engine 2 video driver"
754 Say y here if you want to build DE2 video driver which is present on
755 newer SoCs. Currently only HDMI output is supported.
759 prompt "LCD panel support"
762 Select which type of LCD panel to support.
764 config VIDEO_LCD_PANEL_PARALLEL
765 bool "Generic parallel interface LCD panel"
766 select VIDEO_LCD_IF_PARALLEL
768 config VIDEO_LCD_PANEL_LVDS
769 bool "Generic lvds interface LCD panel"
770 select VIDEO_LCD_IF_LVDS
772 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
773 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
774 select VIDEO_LCD_SSD2828
775 select VIDEO_LCD_IF_PARALLEL
777 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
779 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
780 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
781 select VIDEO_LCD_ANX9804
782 select VIDEO_LCD_IF_PARALLEL
783 select VIDEO_LCD_PANEL_I2C
785 Select this for eDP LCD panels with 4 lanes running at 1.62G,
786 connected via an ANX9804 bridge chip.
788 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
789 bool "Hitachi tx18d42vm LCD panel"
790 select VIDEO_LCD_HITACHI_TX18D42VM
791 select VIDEO_LCD_IF_LVDS
793 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
795 config VIDEO_LCD_TL059WV5C0
796 bool "tl059wv5c0 LCD panel"
797 select VIDEO_LCD_PANEL_I2C
798 select VIDEO_LCD_IF_PARALLEL
800 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
801 Aigo M60/M608/M606 tablets.
806 string "SATA power pin"
809 Set the pins used to power the SATA. This takes a string in the
810 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
814 int "GMAC Transmit Clock Delay Chain"
817 Set the GMAC Transmit Clock Delay Chain value.
819 config SPL_STACK_R_ADDR
820 default 0x4fe00000 if MACH_SUN4I
821 default 0x4fe00000 if MACH_SUN5I
822 default 0x4fe00000 if MACH_SUN6I
823 default 0x4fe00000 if MACH_SUN7I
824 default 0x4fe00000 if MACH_SUN8I
825 default 0x2fe00000 if MACH_SUN9I
826 default 0x4fe00000 if MACH_SUN50I