4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
63 select SUNXI_GEN_SUN6I
67 prompt "Sunxi SoC Variant"
71 bool "sun4i (Allwinner A10)"
73 select ARM_CORTEX_CPU_IS_UP
74 select SUNXI_GEN_SUN4I
78 bool "sun5i (Allwinner A13)"
80 select ARM_CORTEX_CPU_IS_UP
81 select SUNXI_GEN_SUN4I
85 bool "sun6i (Allwinner A31)"
87 select CPU_V7_HAS_NONSEC
88 select CPU_V7_HAS_VIRT
89 select ARCH_SUPPORT_PSCI
90 select SUNXI_GEN_SUN6I
92 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
95 bool "sun7i (Allwinner A20)"
97 select CPU_V7_HAS_NONSEC
98 select CPU_V7_HAS_VIRT
99 select ARCH_SUPPORT_PSCI
100 select SUNXI_GEN_SUN4I
102 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
104 config MACH_SUN8I_A23
105 bool "sun8i (Allwinner A23)"
107 select CPU_V7_HAS_NONSEC
108 select CPU_V7_HAS_VIRT
109 select ARCH_SUPPORT_PSCI
110 select SUNXI_GEN_SUN6I
112 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
114 config MACH_SUN8I_A33
115 bool "sun8i (Allwinner A33)"
117 select CPU_V7_HAS_NONSEC
118 select CPU_V7_HAS_VIRT
119 select ARCH_SUPPORT_PSCI
120 select SUNXI_GEN_SUN6I
122 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
124 config MACH_SUN8I_A83T
125 bool "sun8i (Allwinner A83T)"
127 select SUNXI_GEN_SUN6I
131 bool "sun8i (Allwinner H3)"
133 select CPU_V7_HAS_NONSEC
134 select CPU_V7_HAS_VIRT
135 select ARCH_SUPPORT_PSCI
136 select MACH_SUNXI_H3_H5
137 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
139 config MACH_SUN8I_R40
140 bool "sun8i (Allwinner R40)"
142 select CPU_V7_HAS_NONSEC
143 select CPU_V7_HAS_VIRT
144 select ARCH_SUPPORT_PSCI
145 select SUNXI_GEN_SUN6I
148 config MACH_SUN8I_V3S
149 bool "sun8i (Allwinner V3s)"
151 select CPU_V7_HAS_NONSEC
152 select CPU_V7_HAS_VIRT
153 select ARCH_SUPPORT_PSCI
154 select SUNXI_GEN_SUN6I
155 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
158 bool "sun9i (Allwinner A80)"
160 select SUNXI_HIGH_SRAM
161 select SUNXI_GEN_SUN6I
165 bool "sun50i (Allwinner A64)"
169 select SUNXI_GEN_SUN6I
170 select SUNXI_HIGH_SRAM
173 config MACH_SUN50I_H5
174 bool "sun50i (Allwinner H5)"
176 select MACH_SUNXI_H3_H5
177 select SUNXI_HIGH_SRAM
181 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
184 default y if MACH_SUN8I_A23
185 default y if MACH_SUN8I_A33
186 default y if MACH_SUN8I_A83T
187 default y if MACH_SUNXI_H3_H5
188 default y if MACH_SUN8I_R40
189 default y if MACH_SUN8I_V3S
191 config RESERVE_ALLWINNER_BOOT0_HEADER
192 bool "reserve space for Allwinner boot0 header"
193 select ENABLE_ARM_SOC_BOOT0_HOOK
195 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
196 filled with magic values post build. The Allwinner provided boot0
197 blob relies on this information to load and execute U-Boot.
198 Only needed on 64-bit Allwinner boards so far when using boot0.
200 config ARM_BOOT_HOOK_RMR
204 select ENABLE_ARM_SOC_BOOT0_HOOK
206 Insert some ARM32 code at the very beginning of the U-Boot binary
207 which uses an RMR register write to bring the core into AArch64 mode.
208 The very first instruction acts as a switch, since it's carefully
209 chosen to be a NOP in one mode and a branch in the other, so the
210 code would only be executed if not already in AArch64.
211 This allows both the SPL and the U-Boot proper to be entered in
212 either mode and switch to AArch64 if needed.
215 int "sunxi dram type"
216 depends on MACH_SUN8I_A83T
219 Set the dram type, 3: DDR3, 7: LPDDR3
222 int "sunxi dram clock speed"
223 default 792 if MACH_SUN9I
224 default 648 if MACH_SUN8I_R40
225 default 312 if MACH_SUN6I || MACH_SUN8I
226 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
227 default 672 if MACH_SUN50I
229 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
230 must be a multiple of 24. For the sun9i (A80), the tested values
231 (for DDR3-1600) are 312 to 792.
233 if MACH_SUN5I || MACH_SUN7I
235 int "sunxi mbus clock speed"
238 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
243 int "sunxi dram zq value"
244 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
245 default 127 if MACH_SUN7I
246 default 3881979 if MACH_SUN8I_R40
247 default 4145117 if MACH_SUN9I
248 default 3881915 if MACH_SUN50I
250 Set the dram zq value.
253 bool "sunxi dram odt enable"
254 default n if !MACH_SUN8I_A23
255 default y if MACH_SUN8I_A23
256 default y if MACH_SUN8I_R40
257 default y if MACH_SUN50I
259 Select this to enable dram odt (on die termination).
261 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
263 int "sunxi dram emr1 value"
264 default 0 if MACH_SUN4I
265 default 4 if MACH_SUN5I || MACH_SUN7I
267 Set the dram controller emr1 value.
270 hex "sunxi dram tpr3 value"
273 Set the dram controller tpr3 parameter. This parameter configures
274 the delay on the command lane and also phase shifts, which are
275 applied for sampling incoming read data. The default value 0
276 means that no phase/delay adjustments are necessary. Properly
277 configuring this parameter increases reliability at high DRAM
280 config DRAM_DQS_GATING_DELAY
281 hex "sunxi dram dqs_gating_delay value"
284 Set the dram controller dqs_gating_delay parmeter. Each byte
285 encodes the DQS gating delay for each byte lane. The delay
286 granularity is 1/4 cycle. For example, the value 0x05060606
287 means that the delay is 5 quarter-cycles for one lane (1.25
288 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
289 The default value 0 means autodetection. The results of hardware
290 autodetection are not very reliable and depend on the chip
291 temperature (sometimes producing different results on cold start
292 and warm reboot). But the accuracy of hardware autodetection
293 is usually good enough, unless running at really high DRAM
294 clocks speeds (up to 600MHz). If unsure, keep as 0.
297 prompt "sunxi dram timings"
298 default DRAM_TIMINGS_VENDOR_MAGIC
300 Select the timings of the DDR3 chips.
302 config DRAM_TIMINGS_VENDOR_MAGIC
303 bool "Magic vendor timings from Android"
305 The same DRAM timings as in the Allwinner boot0 bootloader.
307 config DRAM_TIMINGS_DDR3_1066F_1333H
308 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
310 Use the timings of the standard JEDEC DDR3-1066F speed bin for
311 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
312 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
313 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
314 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
315 that down binning to DDR3-1066F is supported (because DDR3-1066F
316 uses a bit faster timings than DDR3-1333H).
318 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
319 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
321 Use the timings of the slowest possible JEDEC speed bin for the
322 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
323 DDR3-800E, DDR3-1066G or DDR3-1333J.
330 config DRAM_ODT_CORRECTION
331 int "sunxi dram odt correction value"
334 Set the dram odt correction value (range -255 - 255). In allwinner
335 fex files, this option is found in bits 8-15 of the u32 odt_en variable
336 in the [dram] section. When bit 31 of the odt_en variable is set
337 then the correction is negative. Usually the value for this is 0.
341 default 1008000000 if MACH_SUN4I
342 default 1008000000 if MACH_SUN5I
343 default 1008000000 if MACH_SUN6I
344 default 912000000 if MACH_SUN7I
345 default 1008000000 if MACH_SUN8I
346 default 1008000000 if MACH_SUN9I
347 default 816000000 if MACH_SUN50I
349 config SYS_CONFIG_NAME
350 default "sun4i" if MACH_SUN4I
351 default "sun5i" if MACH_SUN5I
352 default "sun6i" if MACH_SUN6I
353 default "sun7i" if MACH_SUN7I
354 default "sun8i" if MACH_SUN8I
355 default "sun9i" if MACH_SUN9I
356 default "sun50i" if MACH_SUN50I
365 bool "UART0 on MicroSD breakout board"
368 Repurpose the SD card slot for getting access to the UART0 serial
369 console. Primarily useful only for low level u-boot debugging on
370 tablets, where normal UART0 is difficult to access and requires
371 device disassembly and/or soldering. As the SD card can't be used
372 at the same time, the system can be only booted in the FEL mode.
373 Only enable this if you really know what you are doing.
375 config OLD_SUNXI_KERNEL_COMPAT
376 bool "Enable workarounds for booting old kernels"
379 Set this to enable various workarounds for old kernels, this results in
380 sub-optimal settings for newer kernels, only enable if needed.
383 string "MAC power pin"
386 Set the pin used to power the MAC. This takes a string in the format
387 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
390 string "Card detect pin for mmc0"
391 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
394 Set the card detect pin for mmc0, leave empty to not use cd. This
395 takes a string in the format understood by sunxi_name_to_gpio, e.g.
396 PH1 for pin 1 of port H.
399 string "Card detect pin for mmc1"
402 See MMC0_CD_PIN help text.
405 string "Card detect pin for mmc2"
408 See MMC0_CD_PIN help text.
411 string "Card detect pin for mmc3"
414 See MMC0_CD_PIN help text.
417 string "Pins for mmc1"
420 Set the pins used for mmc1, when applicable. This takes a string in the
421 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
424 string "Pins for mmc2"
427 See MMC1_PINS help text.
430 string "Pins for mmc3"
433 See MMC1_PINS help text.
435 config MMC_SUNXI_SLOT_EXTRA
436 int "mmc extra slot number"
439 sunxi builds always enable mmc0, some boards also have a second sdcard
440 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
443 config INITIAL_USB_SCAN_DELAY
444 int "delay initial usb scan by x ms to allow builtin devices to init"
447 Some boards have on board usb devices which need longer than the
448 USB spec's 1 second to connect from board powerup. Set this config
449 option to a non 0 value to add an extra delay before the first usb
453 string "Vbus enable pin for usb0 (otg)"
456 Set the Vbus enable pin for usb0 (otg). This takes a string in the
457 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
460 string "Vbus detect pin for usb0 (otg)"
463 Set the Vbus detect pin for usb0 (otg). This takes a string in the
464 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
467 string "ID detect pin for usb0 (otg)"
470 Set the ID detect pin for usb0 (otg). This takes a string in the
471 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
474 string "Vbus enable pin for usb1 (ehci0)"
475 default "PH6" if MACH_SUN4I || MACH_SUN7I
476 default "PH27" if MACH_SUN6I
478 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
479 a string in the format understood by sunxi_name_to_gpio, e.g.
480 PH1 for pin 1 of port H.
483 string "Vbus enable pin for usb2 (ehci1)"
484 default "PH3" if MACH_SUN4I || MACH_SUN7I
485 default "PH24" if MACH_SUN6I
487 See USB1_VBUS_PIN help text.
490 string "Vbus enable pin for usb3 (ehci2)"
493 See USB1_VBUS_PIN help text.
496 bool "Enable I2C/TWI controller 0"
497 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
498 default n if MACH_SUN6I || MACH_SUN8I
501 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
502 its clock and setting up the bus. This is especially useful on devices
503 with slaves connected to the bus or with pins exposed through e.g. an
504 expansion port/header.
507 bool "Enable I2C/TWI controller 1"
511 See I2C0_ENABLE help text.
514 bool "Enable I2C/TWI controller 2"
518 See I2C0_ENABLE help text.
520 if MACH_SUN6I || MACH_SUN7I
522 bool "Enable I2C/TWI controller 3"
526 See I2C0_ENABLE help text.
531 bool "Enable the PRCM I2C/TWI controller"
532 # This is used for the pmic on H3
533 default y if SY8106A_POWER
536 Set this to y to enable the I2C controller which is part of the PRCM.
541 bool "Enable I2C/TWI controller 4"
545 See I2C0_ENABLE help text.
549 bool "Enable support for gpio-s on axp PMICs"
552 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
555 bool "Enable graphical uboot console on HDMI, LCD or VGA"
556 depends on !MACH_SUN8I_A83T
557 depends on !MACH_SUNXI_H3_H5
558 depends on !MACH_SUN8I_R40
559 depends on !MACH_SUN8I_V3S
560 depends on !MACH_SUN9I
561 depends on !MACH_SUN50I
564 Say Y here to add support for using a cfb console on the HDMI, LCD
565 or VGA output found on most sunxi devices. See doc/README.video for
566 info on how to select the video output and mode.
569 bool "HDMI output support"
570 depends on VIDEO && !MACH_SUN8I
573 Say Y here to add support for outputting video over HDMI.
576 bool "VGA output support"
577 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
580 Say Y here to add support for outputting video over VGA.
582 config VIDEO_VGA_VIA_LCD
583 bool "VGA via LCD controller support"
584 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
587 Say Y here to add support for external DACs connected to the parallel
588 LCD interface driving a VGA connector, such as found on the
591 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
592 bool "Force sync active high for VGA via LCD controller support"
593 depends on VIDEO_VGA_VIA_LCD
596 Say Y here if you've a board which uses opendrain drivers for the vga
597 hsync and vsync signals. Opendrain drivers cannot generate steep enough
598 positive edges for a stable video output, so on boards with opendrain
599 drivers the sync signals must always be active high.
601 config VIDEO_VGA_EXTERNAL_DAC_EN
602 string "LCD panel power enable pin"
603 depends on VIDEO_VGA_VIA_LCD
606 Set the enable pin for the external VGA DAC. This takes a string in the
607 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
609 config VIDEO_COMPOSITE
610 bool "Composite video output support"
611 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
614 Say Y here to add support for outputting composite video.
616 config VIDEO_LCD_MODE
617 string "LCD panel timing details"
621 LCD panel timing details string, leave empty if there is no LCD panel.
622 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
623 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
624 Also see: http://linux-sunxi.org/LCD
626 config VIDEO_LCD_DCLK_PHASE
627 int "LCD panel display clock phase"
631 Select LCD panel display clock phase shift, range 0-3.
633 config VIDEO_LCD_POWER
634 string "LCD panel power enable pin"
638 Set the power enable pin for the LCD panel. This takes a string in the
639 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
641 config VIDEO_LCD_RESET
642 string "LCD panel reset pin"
646 Set the reset pin for the LCD panel. This takes a string in the format
647 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
649 config VIDEO_LCD_BL_EN
650 string "LCD panel backlight enable pin"
654 Set the backlight enable pin for the LCD panel. This takes a string in the
655 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
658 config VIDEO_LCD_BL_PWM
659 string "LCD panel backlight pwm pin"
663 Set the backlight pwm pin for the LCD panel. This takes a string in the
664 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
666 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
667 bool "LCD panel backlight pwm is inverted"
671 Set this if the backlight pwm output is active low.
673 config VIDEO_LCD_PANEL_I2C
674 bool "LCD panel needs to be configured via i2c"
679 Say y here if the LCD panel needs to be configured via i2c. This
680 will add a bitbang i2c controller using gpios to talk to the LCD.
682 config VIDEO_LCD_PANEL_I2C_SDA
683 string "LCD panel i2c interface SDA pin"
684 depends on VIDEO_LCD_PANEL_I2C
687 Set the SDA pin for the LCD i2c interface. This takes a string in the
688 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
690 config VIDEO_LCD_PANEL_I2C_SCL
691 string "LCD panel i2c interface SCL pin"
692 depends on VIDEO_LCD_PANEL_I2C
695 Set the SCL pin for the LCD i2c interface. This takes a string in the
696 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
699 # Note only one of these may be selected at a time! But hidden choices are
700 # not supported by Kconfig
701 config VIDEO_LCD_IF_PARALLEL
704 config VIDEO_LCD_IF_LVDS
712 bool "Display Engine 2 video driver"
718 Say y here if you want to build DE2 video driver which is present on
719 newer SoCs. Currently only HDMI output is supported.
723 prompt "LCD panel support"
726 Select which type of LCD panel to support.
728 config VIDEO_LCD_PANEL_PARALLEL
729 bool "Generic parallel interface LCD panel"
730 select VIDEO_LCD_IF_PARALLEL
732 config VIDEO_LCD_PANEL_LVDS
733 bool "Generic lvds interface LCD panel"
734 select VIDEO_LCD_IF_LVDS
736 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
737 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
738 select VIDEO_LCD_SSD2828
739 select VIDEO_LCD_IF_PARALLEL
741 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
743 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
744 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
745 select VIDEO_LCD_ANX9804
746 select VIDEO_LCD_IF_PARALLEL
747 select VIDEO_LCD_PANEL_I2C
749 Select this for eDP LCD panels with 4 lanes running at 1.62G,
750 connected via an ANX9804 bridge chip.
752 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
753 bool "Hitachi tx18d42vm LCD panel"
754 select VIDEO_LCD_HITACHI_TX18D42VM
755 select VIDEO_LCD_IF_LVDS
757 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
759 config VIDEO_LCD_TL059WV5C0
760 bool "tl059wv5c0 LCD panel"
761 select VIDEO_LCD_PANEL_I2C
762 select VIDEO_LCD_IF_PARALLEL
764 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
765 Aigo M60/M608/M606 tablets.
770 string "SATA power pin"
773 Set the pins used to power the SATA. This takes a string in the
774 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
778 int "GMAC Transmit Clock Delay Chain"
781 Set the GMAC Transmit Clock Delay Chain value.
783 config SPL_STACK_R_ADDR
784 default 0x4fe00000 if MACH_SUN4I
785 default 0x4fe00000 if MACH_SUN5I
786 default 0x4fe00000 if MACH_SUN6I
787 default 0x4fe00000 if MACH_SUN7I
788 default 0x4fe00000 if MACH_SUN8I
789 default 0x2fe00000 if MACH_SUN9I
790 default 0x4fe00000 if MACH_SUN50I