4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
51 config DRAM_SUN50I_H616
54 Select this dram controller driver for some sun50i platforms,
58 config DRAM_SUN50I_H616_WRITE_LEVELING
59 bool "H616 DRAM write leveling"
61 Select this when DRAM on your H616 board needs write leveling.
63 config DRAM_SUN50I_H616_READ_CALIBRATION
64 bool "H616 DRAM read calibration"
66 Select this when DRAM on your H616 board needs read calibration.
68 config DRAM_SUN50I_H616_READ_TRAINING
69 bool "H616 DRAM read training"
71 Select this when DRAM on your H616 board needs read training.
73 config DRAM_SUN50I_H616_WRITE_TRAINING
74 bool "H616 DRAM write training"
76 Select this when DRAM on your H616 board needs write training.
78 config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
79 bool "H616 DRAM bit delay compensation"
81 Select this when DRAM on your H616 board needs bit delay
84 config DRAM_SUN50I_H616_UNKNOWN_FEATURE
85 bool "H616 DRAM unknown feature"
87 Select this when DRAM on your H616 board needs this unknown
94 Support for the PRCM (Power/Reset/Clock Management) unit available
99 select DM_PMIC if DM_I2C
100 select PMIC_AXP if DM_I2C
102 Select this PMIC bus access helpers for Sunxi platform PRCM or other
103 AXP family PMIC devices.
105 config SUNXI_SRAM_ADDRESS
107 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
108 default 0x20000 if SUN50I_GEN_H6
111 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
112 with the first SRAM region being located at address 0.
113 Some newer SoCs map the boot ROM at address 0 instead and move the
114 SRAM to a different address.
116 config SUNXI_A64_TIMER_ERRATUM
119 # Note only one of these may be selected at a time! But hidden choices are
120 # not supported by Kconfig
121 config SUNXI_GEN_SUN4I
124 Select this for sunxi SoCs which have resets and clocks set up
125 as the original A10 (mach-sun4i).
127 config SUNXI_GEN_SUN6I
130 Select this for sunxi SoCs which have sun6i like periphery, like
131 separate ahb reset control registers, custom pmic bus, new style
138 select MMC_SUNXI_HAS_NEW_MODE
141 Select this for sunxi SoCs which have H6 like peripherals, clocks
147 Select this for sunxi SoCs which uses a DRAM controller like the
148 DesignWare controller used in H3, mainly SoCs after H3, which do
149 not have official open-source DRAM initialization code, but can
150 use modified H3 DRAM initialization code.
153 config SUNXI_DRAM_DW_16BIT
156 Select this for sunxi SoCs with DesignWare DRAM controller and
157 have only 16-bit memory buswidth.
159 config SUNXI_DRAM_DW_32BIT
162 Select this for sunxi SoCs with DesignWare DRAM controller with
163 32-bit memory buswidth.
166 config MACH_SUNXI_H3_H5
172 select SUNXI_DRAM_DW_32BIT
173 select SUNXI_GEN_SUN6I
176 # TODO: try out A80's 8GiB DRAM space
177 config SUNXI_DRAM_MAX_SIZE
179 default 0x100000000 if MACH_SUN50I_H616
180 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
184 prompt "Sunxi SoC Variant"
188 bool "sun4i (Allwinner A10)"
190 select ARM_CORTEX_CPU_IS_UP
193 select SUNXI_GEN_SUN4I
195 imply SPL_SYS_I2C_LEGACY
199 bool "sun5i (Allwinner A13)"
201 select ARM_CORTEX_CPU_IS_UP
204 select SUNXI_GEN_SUN4I
206 imply CONS_INDEX_2 if !DM_SERIAL
207 imply SPL_SYS_I2C_LEGACY
211 bool "sun6i (Allwinner A31)"
213 select CPU_V7_HAS_NONSEC
214 select CPU_V7_HAS_VIRT
215 select ARCH_SUPPORT_PSCI
220 select SUNXI_GEN_SUN6I
222 select SYS_I2C_SUN6I_P2WI
223 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
226 bool "sun7i (Allwinner A20)"
228 select CPU_V7_HAS_NONSEC
229 select CPU_V7_HAS_VIRT
230 select ARCH_SUPPORT_PSCI
233 select SUNXI_GEN_SUN4I
235 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
236 imply SPL_SYS_I2C_LEGACY
239 config MACH_SUN8I_A23
240 bool "sun8i (Allwinner A23)"
242 select CPU_V7_HAS_NONSEC
243 select CPU_V7_HAS_VIRT
244 select ARCH_SUPPORT_PSCI
245 select DRAM_SUN8I_A23
248 select SUNXI_GEN_SUN6I
250 select SYS_I2C_SUN8I_RSB
251 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
252 imply CONS_INDEX_5 if !DM_SERIAL
254 config MACH_SUN8I_A33
255 bool "sun8i (Allwinner A33)"
257 select CPU_V7_HAS_NONSEC
258 select CPU_V7_HAS_VIRT
259 select ARCH_SUPPORT_PSCI
260 select DRAM_SUN8I_A33
263 select SUNXI_GEN_SUN6I
265 select SYS_I2C_SUN8I_RSB
266 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
267 imply CONS_INDEX_5 if !DM_SERIAL
269 config MACH_SUN8I_A83T
270 bool "sun8i (Allwinner A83T)"
272 select DRAM_SUN8I_A83T
275 select SUNXI_GEN_SUN6I
276 select MMC_SUNXI_HAS_NEW_MODE
277 select MMC_SUNXI_HAS_MODE_SWITCH
279 select SYS_I2C_SUN8I_RSB
282 bool "sun8i (Allwinner H3)"
284 select CPU_V7_HAS_NONSEC
285 select CPU_V7_HAS_VIRT
286 select ARCH_SUPPORT_PSCI
287 select MACH_SUNXI_H3_H5
288 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
290 config MACH_SUN8I_R40
291 bool "sun8i (Allwinner R40)"
293 select CPU_V7_HAS_NONSEC
294 select CPU_V7_HAS_VIRT
295 select ARCH_SUPPORT_PSCI
296 select SUNXI_GEN_SUN6I
297 select MMC_SUNXI_HAS_NEW_MODE
300 select SUNXI_DRAM_DW_32BIT
302 imply SPL_SYS_I2C_LEGACY
304 config MACH_SUN8I_V3S
305 bool "sun8i (Allwinner V3/V3s/S3/S3L)"
307 select CPU_V7_HAS_NONSEC
308 select CPU_V7_HAS_VIRT
309 select ARCH_SUPPORT_PSCI
310 select SUNXI_GEN_SUN6I
312 select SUNXI_DRAM_DW_16BIT
314 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
317 bool "sun9i (Allwinner A80)"
322 select SUNXI_GEN_SUN6I
326 bool "sun50i (Allwinner A64)"
335 select SUNXI_GEN_SUN6I
336 select MMC_SUNXI_HAS_NEW_MODE
339 select SUNXI_DRAM_DW_32BIT
342 select SUNXI_A64_TIMER_ERRATUM
344 config MACH_SUN50I_H5
345 bool "sun50i (Allwinner H5)"
347 select MACH_SUNXI_H3_H5
348 select MMC_SUNXI_HAS_NEW_MODE
352 config MACH_SUN50I_H6
353 bool "sun50i (Allwinner H6)"
356 select DRAM_SUN50I_H6
359 config MACH_SUN50I_H616
360 bool "sun50i (Allwinner H616)"
362 select DRAM_SUN50I_H616
367 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
371 default y if MACH_SUN8I_A23
372 default y if MACH_SUN8I_A33
373 default y if MACH_SUN8I_A83T
374 default y if MACH_SUNXI_H3_H5
375 default y if MACH_SUN8I_R40
376 default y if MACH_SUN8I_V3S
378 config RESERVE_ALLWINNER_BOOT0_HEADER
379 bool "reserve space for Allwinner boot0 header"
380 select ENABLE_ARM_SOC_BOOT0_HOOK
382 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
383 filled with magic values post build. The Allwinner provided boot0
384 blob relies on this information to load and execute U-Boot.
385 Only needed on 64-bit Allwinner boards so far when using boot0.
387 config ARM_BOOT_HOOK_RMR
391 select ENABLE_ARM_SOC_BOOT0_HOOK
393 Insert some ARM32 code at the very beginning of the U-Boot binary
394 which uses an RMR register write to bring the core into AArch64 mode.
395 The very first instruction acts as a switch, since it's carefully
396 chosen to be a NOP in one mode and a branch in the other, so the
397 code would only be executed if not already in AArch64.
398 This allows both the SPL and the U-Boot proper to be entered in
399 either mode and switch to AArch64 if needed.
401 if SUNXI_DRAM_DW || DRAM_SUN50I_H6
402 config SUNXI_DRAM_DDR3
405 config SUNXI_DRAM_DDR2
408 config SUNXI_DRAM_LPDDR3
412 prompt "DRAM Type and Timing"
413 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
414 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
416 config SUNXI_DRAM_DDR3_1333
418 select SUNXI_DRAM_DDR3
420 This option is the original only supported memory type, which suits
421 many H3/H5/A64 boards available now.
423 config SUNXI_DRAM_LPDDR3_STOCK
424 bool "LPDDR3 with Allwinner stock configuration"
425 select SUNXI_DRAM_LPDDR3
427 This option is the LPDDR3 timing used by the stock boot0 by
430 config SUNXI_DRAM_H6_LPDDR3
431 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
432 select SUNXI_DRAM_LPDDR3
433 depends on DRAM_SUN50I_H6
435 This option is the LPDDR3 timing used by the stock boot0 by
438 config SUNXI_DRAM_H6_DDR3_1333
439 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
440 select SUNXI_DRAM_DDR3
441 depends on DRAM_SUN50I_H6
443 This option is the DDR3 timing used by the boot0 on H6 TV boxes
444 which use a DDR3-1333 timing.
446 config SUNXI_DRAM_DDR2_V3S
447 bool "DDR2 found in V3s chip"
448 select SUNXI_DRAM_DDR2
449 depends on MACH_SUN8I_V3S
451 This option is only for the DDR2 memory chip which is co-packaged in
458 int "sunxi dram type"
459 depends on MACH_SUN8I_A83T
462 Set the dram type, 3: DDR3, 7: LPDDR3
465 int "sunxi dram clock speed"
466 default 792 if MACH_SUN9I
467 default 648 if MACH_SUN8I_R40
468 default 312 if MACH_SUN6I || MACH_SUN8I
469 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
471 default 672 if MACH_SUN50I
472 default 744 if MACH_SUN50I_H6
473 default 720 if MACH_SUN50I_H616
475 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
476 must be a multiple of 24. For the sun9i (A80), the tested values
477 (for DDR3-1600) are 312 to 792.
479 if MACH_SUN5I || MACH_SUN7I
481 int "sunxi mbus clock speed"
484 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
489 int "sunxi dram zq value"
490 depends on !MACH_SUN50I_H616
491 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
492 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
493 default 127 if MACH_SUN7I
494 default 14779 if MACH_SUN8I_V3S
495 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
496 default 4145117 if MACH_SUN9I
497 default 3881915 if MACH_SUN50I
499 Set the dram zq value.
502 bool "sunxi dram odt enable"
503 default y if MACH_SUN8I_A23
504 default y if MACH_SUNXI_H3_H5
505 default y if MACH_SUN8I_R40
506 default y if MACH_SUN50I
507 default y if MACH_SUN50I_H6
508 default y if MACH_SUN50I_H616
510 Select this to enable dram odt (on die termination).
512 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
514 int "sunxi dram emr1 value"
515 default 0 if MACH_SUN4I
516 default 4 if MACH_SUN5I || MACH_SUN7I
518 Set the dram controller emr1 value.
521 hex "sunxi dram tpr3 value"
524 Set the dram controller tpr3 parameter. This parameter configures
525 the delay on the command lane and also phase shifts, which are
526 applied for sampling incoming read data. The default value 0
527 means that no phase/delay adjustments are necessary. Properly
528 configuring this parameter increases reliability at high DRAM
531 config DRAM_DQS_GATING_DELAY
532 hex "sunxi dram dqs_gating_delay value"
535 Set the dram controller dqs_gating_delay parmeter. Each byte
536 encodes the DQS gating delay for each byte lane. The delay
537 granularity is 1/4 cycle. For example, the value 0x05060606
538 means that the delay is 5 quarter-cycles for one lane (1.25
539 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
540 The default value 0 means autodetection. The results of hardware
541 autodetection are not very reliable and depend on the chip
542 temperature (sometimes producing different results on cold start
543 and warm reboot). But the accuracy of hardware autodetection
544 is usually good enough, unless running at really high DRAM
545 clocks speeds (up to 600MHz). If unsure, keep as 0.
548 prompt "sunxi dram timings"
549 default DRAM_TIMINGS_VENDOR_MAGIC
551 Select the timings of the DDR3 chips.
553 config DRAM_TIMINGS_VENDOR_MAGIC
554 bool "Magic vendor timings from Android"
556 The same DRAM timings as in the Allwinner boot0 bootloader.
558 config DRAM_TIMINGS_DDR3_1066F_1333H
559 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
561 Use the timings of the standard JEDEC DDR3-1066F speed bin for
562 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
563 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
564 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
565 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
566 that down binning to DDR3-1066F is supported (because DDR3-1066F
567 uses a bit faster timings than DDR3-1333H).
569 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
570 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
572 Use the timings of the slowest possible JEDEC speed bin for the
573 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
574 DDR3-800E, DDR3-1066G or DDR3-1333J.
581 config DRAM_ODT_CORRECTION
582 int "sunxi dram odt correction value"
585 Set the dram odt correction value (range -255 - 255). In allwinner
586 fex files, this option is found in bits 8-15 of the u32 odt_en variable
587 in the [dram] section. When bit 31 of the odt_en variable is set
588 then the correction is negative. Usually the value for this is 0.
592 default 1008000000 if MACH_SUN4I
593 default 1008000000 if MACH_SUN5I
594 default 1008000000 if MACH_SUN6I
595 default 912000000 if MACH_SUN7I
596 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
597 default 1008000000 if MACH_SUN8I
598 default 1008000000 if MACH_SUN9I
599 default 888000000 if MACH_SUN50I_H6
600 default 1008000000 if MACH_SUN50I_H616
602 config SYS_CONFIG_NAME
603 default "sun4i" if MACH_SUN4I
604 default "sun5i" if MACH_SUN5I
605 default "sun6i" if MACH_SUN6I
606 default "sun7i" if MACH_SUN7I
607 default "sun8i" if MACH_SUN8I
608 default "sun9i" if MACH_SUN9I
609 default "sun50i" if MACH_SUN50I
610 default "sun50i" if MACH_SUN50I_H6
611 default "sun50i" if MACH_SUN50I_H616
620 bool "UART0 on MicroSD breakout board"
622 Repurpose the SD card slot for getting access to the UART0 serial
623 console. Primarily useful only for low level u-boot debugging on
624 tablets, where normal UART0 is difficult to access and requires
625 device disassembly and/or soldering. As the SD card can't be used
626 at the same time, the system can be only booted in the FEL mode.
627 Only enable this if you really know what you are doing.
629 config OLD_SUNXI_KERNEL_COMPAT
630 bool "Enable workarounds for booting old kernels"
632 Set this to enable various workarounds for old kernels, this results in
633 sub-optimal settings for newer kernels, only enable if needed.
636 string "MAC power pin"
639 Set the pin used to power the MAC. This takes a string in the format
640 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
643 string "Card detect pin for mmc0"
644 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
647 Set the card detect pin for mmc0, leave empty to not use cd. This
648 takes a string in the format understood by sunxi_name_to_gpio, e.g.
649 PH1 for pin 1 of port H.
652 string "Card detect pin for mmc1"
655 See MMC0_CD_PIN help text.
658 string "Card detect pin for mmc2"
661 See MMC0_CD_PIN help text.
664 string "Card detect pin for mmc3"
667 See MMC0_CD_PIN help text.
670 bool "Pins for mmc1 are on Port H"
671 depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
673 Select this option for boards where mmc1 uses the Port H pinmux.
675 config MMC_SUNXI_SLOT_EXTRA
676 int "mmc extra slot number"
679 sunxi builds always enable mmc0, some boards also have a second sdcard
680 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
683 config INITIAL_USB_SCAN_DELAY
684 int "delay initial usb scan by x ms to allow builtin devices to init"
687 Some boards have on board usb devices which need longer than the
688 USB spec's 1 second to connect from board powerup. Set this config
689 option to a non 0 value to add an extra delay before the first usb
693 string "Vbus enable pin for usb0 (otg)"
696 Set the Vbus enable pin for usb0 (otg). This takes a string in the
697 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
700 string "Vbus detect pin for usb0 (otg)"
703 Set the Vbus detect pin for usb0 (otg). This takes a string in the
704 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
707 string "ID detect pin for usb0 (otg)"
710 Set the ID detect pin for usb0 (otg). This takes a string in the
711 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
714 string "Vbus enable pin for usb1 (ehci0)"
715 default "PH6" if MACH_SUN4I || MACH_SUN7I
716 default "PH27" if MACH_SUN6I
718 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
719 a string in the format understood by sunxi_name_to_gpio, e.g.
720 PH1 for pin 1 of port H.
723 string "Vbus enable pin for usb2 (ehci1)"
724 default "PH3" if MACH_SUN4I || MACH_SUN7I
725 default "PH24" if MACH_SUN6I
727 See USB1_VBUS_PIN help text.
730 string "Vbus enable pin for usb3 (ehci2)"
733 See USB1_VBUS_PIN help text.
736 bool "Enable I2C/TWI controller 0"
737 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
738 default n if MACH_SUN6I || MACH_SUN8I
741 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
742 its clock and setting up the bus. This is especially useful on devices
743 with slaves connected to the bus or with pins exposed through e.g. an
744 expansion port/header.
747 bool "Enable I2C/TWI controller 1"
750 See I2C0_ENABLE help text.
753 bool "Enable I2C/TWI controller 2"
756 See I2C0_ENABLE help text.
758 if MACH_SUN6I || MACH_SUN7I
760 bool "Enable I2C/TWI controller 3"
763 See I2C0_ENABLE help text.
766 if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
768 bool "Enable the PRCM I2C/TWI controller"
769 # This is used for the pmic on H3
770 default y if SY8106A_POWER
773 Set this to y to enable the I2C controller which is part of the PRCM.
778 bool "Enable I2C/TWI controller 4"
781 See I2C0_ENABLE help text.
785 bool "Enable support for gpio-s on axp PMICs"
786 depends on AXP_PMIC_BUS
788 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
791 bool "Enable graphical uboot console on HDMI, LCD or VGA"
792 depends on !MACH_SUN8I_A83T
793 depends on !MACH_SUNXI_H3_H5
794 depends on !MACH_SUN8I_R40
795 depends on !MACH_SUN8I_V3S
796 depends on !MACH_SUN9I
797 depends on !MACH_SUN50I
798 depends on !SUN50I_GEN_H6
801 imply VIDEO_DT_SIMPLEFB
804 Say Y here to add support for using a graphical console on the HDMI,
805 LCD or VGA output found on older sunxi devices. This will also provide
806 a simple_framebuffer device for Linux.
809 bool "HDMI output support"
810 depends on VIDEO_SUNXI && !MACH_SUN8I
813 Say Y here to add support for outputting video over HDMI.
816 bool "VGA output support"
817 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
819 Say Y here to add support for outputting video over VGA.
821 config VIDEO_VGA_VIA_LCD
822 bool "VGA via LCD controller support"
823 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
825 Say Y here to add support for external DACs connected to the parallel
826 LCD interface driving a VGA connector, such as found on the
829 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
830 bool "Force sync active high for VGA via LCD controller support"
831 depends on VIDEO_VGA_VIA_LCD
833 Say Y here if you've a board which uses opendrain drivers for the vga
834 hsync and vsync signals. Opendrain drivers cannot generate steep enough
835 positive edges for a stable video output, so on boards with opendrain
836 drivers the sync signals must always be active high.
838 config VIDEO_VGA_EXTERNAL_DAC_EN
839 string "LCD panel power enable pin"
840 depends on VIDEO_VGA_VIA_LCD
843 Set the enable pin for the external VGA DAC. This takes a string in the
844 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
846 config VIDEO_COMPOSITE
847 bool "Composite video output support"
848 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
850 Say Y here to add support for outputting composite video.
852 config VIDEO_LCD_MODE
853 string "LCD panel timing details"
854 depends on VIDEO_SUNXI
857 LCD panel timing details string, leave empty if there is no LCD panel.
858 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
859 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
860 Also see: http://linux-sunxi.org/LCD
862 config VIDEO_LCD_DCLK_PHASE
863 int "LCD panel display clock phase"
864 depends on VIDEO_SUNXI || DM_VIDEO
867 Select LCD panel display clock phase shift, range 0-3.
869 config VIDEO_LCD_POWER
870 string "LCD panel power enable pin"
871 depends on VIDEO_SUNXI
874 Set the power enable pin for the LCD panel. This takes a string in the
875 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
877 config VIDEO_LCD_RESET
878 string "LCD panel reset pin"
879 depends on VIDEO_SUNXI
882 Set the reset pin for the LCD panel. This takes a string in the format
883 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
885 config VIDEO_LCD_BL_EN
886 string "LCD panel backlight enable pin"
887 depends on VIDEO_SUNXI
890 Set the backlight enable pin for the LCD panel. This takes a string in the
891 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
894 config VIDEO_LCD_BL_PWM
895 string "LCD panel backlight pwm pin"
896 depends on VIDEO_SUNXI
899 Set the backlight pwm pin for the LCD panel. This takes a string in the
900 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
902 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
903 bool "LCD panel backlight pwm is inverted"
904 depends on VIDEO_SUNXI
907 Set this if the backlight pwm output is active low.
909 config VIDEO_LCD_PANEL_I2C
910 bool "LCD panel needs to be configured via i2c"
911 depends on VIDEO_SUNXI
914 Say y here if the LCD panel needs to be configured via i2c. This
915 will add a bitbang i2c controller using gpios to talk to the LCD.
917 config VIDEO_LCD_PANEL_I2C_SDA
918 string "LCD panel i2c interface SDA pin"
919 depends on VIDEO_LCD_PANEL_I2C
922 Set the SDA pin for the LCD i2c interface. This takes a string in the
923 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
925 config VIDEO_LCD_PANEL_I2C_SCL
926 string "LCD panel i2c interface SCL pin"
927 depends on VIDEO_LCD_PANEL_I2C
930 Set the SCL pin for the LCD i2c interface. This takes a string in the
931 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
934 # Note only one of these may be selected at a time! But hidden choices are
935 # not supported by Kconfig
936 config VIDEO_LCD_IF_PARALLEL
939 config VIDEO_LCD_IF_LVDS
946 bool "Display Engine 2 video driver"
951 imply VIDEO_DT_SIMPLEFB
954 Say y here if you want to build DE2 video driver which is present on
955 newer SoCs. Currently only HDMI output is supported.
959 prompt "LCD panel support"
960 depends on VIDEO_SUNXI
962 Select which type of LCD panel to support.
964 config VIDEO_LCD_PANEL_PARALLEL
965 bool "Generic parallel interface LCD panel"
966 select VIDEO_LCD_IF_PARALLEL
968 config VIDEO_LCD_PANEL_LVDS
969 bool "Generic lvds interface LCD panel"
970 select VIDEO_LCD_IF_LVDS
972 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
973 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
974 select VIDEO_LCD_SSD2828
975 select VIDEO_LCD_IF_PARALLEL
977 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
979 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
980 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
981 select VIDEO_LCD_ANX9804
982 select VIDEO_LCD_IF_PARALLEL
983 select VIDEO_LCD_PANEL_I2C
985 Select this for eDP LCD panels with 4 lanes running at 1.62G,
986 connected via an ANX9804 bridge chip.
988 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
989 bool "Hitachi tx18d42vm LCD panel"
990 select VIDEO_LCD_HITACHI_TX18D42VM
991 select VIDEO_LCD_IF_LVDS
993 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
995 config VIDEO_LCD_TL059WV5C0
996 bool "tl059wv5c0 LCD panel"
997 select VIDEO_LCD_PANEL_I2C
998 select VIDEO_LCD_IF_PARALLEL
1000 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
1001 Aigo M60/M608/M606 tablets.
1006 string "SATA power pin"
1009 Set the pins used to power the SATA. This takes a string in the
1010 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
1013 config GMAC_TX_DELAY
1014 int "GMAC Transmit Clock Delay Chain"
1017 Set the GMAC Transmit Clock Delay Chain value.
1019 config SPL_STACK_R_ADDR
1020 default 0x4fe00000 if MACH_SUN4I
1021 default 0x4fe00000 if MACH_SUN5I
1022 default 0x4fe00000 if MACH_SUN6I
1023 default 0x4fe00000 if MACH_SUN7I
1024 default 0x4fe00000 if MACH_SUN8I
1025 default 0x2fe00000 if MACH_SUN9I
1026 default 0x4fe00000 if MACH_SUN50I
1027 default 0x4fe00000 if SUN50I_GEN_H6
1029 config SPL_SPI_SUNXI
1030 bool "Support for SPI Flash on Allwinner SoCs in SPL"
1031 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
1033 Enable support for SPI Flash. This option allows SPL to read from
1034 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1035 not need any extra configuration.
1037 config PINE64_DT_SELECTION
1038 bool "Enable Pine64 device tree selection code"
1039 depends on MACH_SUN50I
1041 The original Pine A64 and Pine A64+ are similar but different
1042 boards and can be differed by the DRAM size. Pine A64 has
1043 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1044 option, the device tree selection code specific to Pine64 which
1045 utilizes the DRAM size will be enabled.
1047 config PINEPHONE_DT_SELECTION
1048 bool "Enable PinePhone device tree selection code"
1049 depends on MACH_SUN50I
1051 Enable this option to automatically select the device tree for the
1052 correct PinePhone hardware revision during boot.
1054 config BLUETOOTH_DT_DEVICE_FIXUP
1055 string "Fixup the Bluetooth controller address"
1058 This option specifies the DT compatible name of the Bluetooth
1059 controller for which to set the "local-bd-address" property.
1060 Set this option if your device ships with the Bluetooth controller
1062 The used address is "bdaddr" if set, and "ethaddr" with the LSB
1067 config CHIP_DIP_SCAN
1068 bool "Enable DIPs detection for CHIP board"
1069 select SUPPORT_EXTENSION_SCAN
1073 select W1_EEPROM_DS24XXX
1074 select CMD_EXTENSION