4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
158 select DM_SCSI if SCSI
161 select SUNXI_GEN_SUN4I
165 bool "sun5i (Allwinner A13)"
167 select ARM_CORTEX_CPU_IS_UP
170 select SUNXI_GEN_SUN4I
172 imply CONS_INDEX_2 if !DM_SERIAL
175 bool "sun6i (Allwinner A31)"
177 select CPU_V7_HAS_NONSEC
178 select CPU_V7_HAS_VIRT
179 select ARCH_SUPPORT_PSCI
184 select SUNXI_GEN_SUN6I
186 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
189 bool "sun7i (Allwinner A20)"
191 select CPU_V7_HAS_NONSEC
192 select CPU_V7_HAS_VIRT
193 select ARCH_SUPPORT_PSCI
196 select SUNXI_GEN_SUN4I
198 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
200 config MACH_SUN8I_A23
201 bool "sun8i (Allwinner A23)"
203 select CPU_V7_HAS_NONSEC
204 select CPU_V7_HAS_VIRT
205 select ARCH_SUPPORT_PSCI
206 select DRAM_SUN8I_A23
208 select SUNXI_GEN_SUN6I
210 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
211 imply CONS_INDEX_5 if !DM_SERIAL
213 config MACH_SUN8I_A33
214 bool "sun8i (Allwinner A33)"
216 select CPU_V7_HAS_NONSEC
217 select CPU_V7_HAS_VIRT
218 select ARCH_SUPPORT_PSCI
219 select DRAM_SUN8I_A33
221 select SUNXI_GEN_SUN6I
223 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
224 imply CONS_INDEX_5 if !DM_SERIAL
226 config MACH_SUN8I_A83T
227 bool "sun8i (Allwinner A83T)"
229 select DRAM_SUN8I_A83T
231 select SUNXI_GEN_SUN6I
232 select MMC_SUNXI_HAS_NEW_MODE
236 bool "sun8i (Allwinner H3)"
238 select CPU_V7_HAS_NONSEC
239 select CPU_V7_HAS_VIRT
240 select ARCH_SUPPORT_PSCI
241 select MACH_SUNXI_H3_H5
242 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
244 config MACH_SUN8I_R40
245 bool "sun8i (Allwinner R40)"
247 select CPU_V7_HAS_NONSEC
248 select CPU_V7_HAS_VIRT
249 select ARCH_SUPPORT_PSCI
250 select SUNXI_GEN_SUN6I
253 select SUNXI_DRAM_DW_32BIT
255 config MACH_SUN8I_V3S
256 bool "sun8i (Allwinner V3s)"
258 select CPU_V7_HAS_NONSEC
259 select CPU_V7_HAS_VIRT
260 select ARCH_SUPPORT_PSCI
261 select SUNXI_GEN_SUN6I
263 select SUNXI_DRAM_DW_16BIT
265 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
268 bool "sun9i (Allwinner A80)"
272 select SUNXI_GEN_SUN6I
277 bool "sun50i (Allwinner A64)"
282 select SUNXI_GEN_SUN6I
285 select SUNXI_DRAM_DW_32BIT
288 select SUNXI_A64_TIMER_ERRATUM
290 config MACH_SUN50I_H5
291 bool "sun50i (Allwinner H5)"
293 select MACH_SUNXI_H3_H5
297 config MACH_SUN50I_H6
298 bool "sun50i (Allwinner H6)"
303 select DRAM_SUN50I_H6
307 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
312 default y if MACH_SUN8I_A23
313 default y if MACH_SUN8I_A33
314 default y if MACH_SUN8I_A83T
315 default y if MACH_SUNXI_H3_H5
316 default y if MACH_SUN8I_R40
317 default y if MACH_SUN8I_V3S
319 config RESERVE_ALLWINNER_BOOT0_HEADER
320 bool "reserve space for Allwinner boot0 header"
321 select ENABLE_ARM_SOC_BOOT0_HOOK
323 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
324 filled with magic values post build. The Allwinner provided boot0
325 blob relies on this information to load and execute U-Boot.
326 Only needed on 64-bit Allwinner boards so far when using boot0.
328 config ARM_BOOT_HOOK_RMR
332 select ENABLE_ARM_SOC_BOOT0_HOOK
334 Insert some ARM32 code at the very beginning of the U-Boot binary
335 which uses an RMR register write to bring the core into AArch64 mode.
336 The very first instruction acts as a switch, since it's carefully
337 chosen to be a NOP in one mode and a branch in the other, so the
338 code would only be executed if not already in AArch64.
339 This allows both the SPL and the U-Boot proper to be entered in
340 either mode and switch to AArch64 if needed.
343 config SUNXI_DRAM_DDR3
346 config SUNXI_DRAM_DDR2
349 config SUNXI_DRAM_LPDDR3
353 prompt "DRAM Type and Timing"
354 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
355 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
357 config SUNXI_DRAM_DDR3_1333
359 select SUNXI_DRAM_DDR3
360 depends on !MACH_SUN8I_V3S
362 This option is the original only supported memory type, which suits
363 many H3/H5/A64 boards available now.
365 config SUNXI_DRAM_LPDDR3_STOCK
366 bool "LPDDR3 with Allwinner stock configuration"
367 select SUNXI_DRAM_LPDDR3
369 This option is the LPDDR3 timing used by the stock boot0 by
372 config SUNXI_DRAM_DDR2_V3S
373 bool "DDR2 found in V3s chip"
374 select SUNXI_DRAM_DDR2
375 depends on MACH_SUN8I_V3S
377 This option is only for the DDR2 memory chip which is co-packaged in
384 int "sunxi dram type"
385 depends on MACH_SUN8I_A83T
388 Set the dram type, 3: DDR3, 7: LPDDR3
391 int "sunxi dram clock speed"
392 default 792 if MACH_SUN9I
393 default 648 if MACH_SUN8I_R40
394 default 312 if MACH_SUN6I || MACH_SUN8I
395 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
397 default 672 if MACH_SUN50I
398 default 744 if MACH_SUN50I_H6
400 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
401 must be a multiple of 24. For the sun9i (A80), the tested values
402 (for DDR3-1600) are 312 to 792.
404 if MACH_SUN5I || MACH_SUN7I
406 int "sunxi mbus clock speed"
409 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
414 int "sunxi dram zq value"
415 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
416 default 127 if MACH_SUN7I
417 default 14779 if MACH_SUN8I_V3S
418 default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
419 default 4145117 if MACH_SUN9I
420 default 3881915 if MACH_SUN50I
422 Set the dram zq value.
425 bool "sunxi dram odt enable"
426 default y if MACH_SUN8I_A23
427 default y if MACH_SUN8I_R40
428 default y if MACH_SUN50I
429 default y if MACH_SUN50I_H6
431 Select this to enable dram odt (on die termination).
433 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
435 int "sunxi dram emr1 value"
436 default 0 if MACH_SUN4I
437 default 4 if MACH_SUN5I || MACH_SUN7I
439 Set the dram controller emr1 value.
442 hex "sunxi dram tpr3 value"
445 Set the dram controller tpr3 parameter. This parameter configures
446 the delay on the command lane and also phase shifts, which are
447 applied for sampling incoming read data. The default value 0
448 means that no phase/delay adjustments are necessary. Properly
449 configuring this parameter increases reliability at high DRAM
452 config DRAM_DQS_GATING_DELAY
453 hex "sunxi dram dqs_gating_delay value"
456 Set the dram controller dqs_gating_delay parmeter. Each byte
457 encodes the DQS gating delay for each byte lane. The delay
458 granularity is 1/4 cycle. For example, the value 0x05060606
459 means that the delay is 5 quarter-cycles for one lane (1.25
460 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
461 The default value 0 means autodetection. The results of hardware
462 autodetection are not very reliable and depend on the chip
463 temperature (sometimes producing different results on cold start
464 and warm reboot). But the accuracy of hardware autodetection
465 is usually good enough, unless running at really high DRAM
466 clocks speeds (up to 600MHz). If unsure, keep as 0.
469 prompt "sunxi dram timings"
470 default DRAM_TIMINGS_VENDOR_MAGIC
472 Select the timings of the DDR3 chips.
474 config DRAM_TIMINGS_VENDOR_MAGIC
475 bool "Magic vendor timings from Android"
477 The same DRAM timings as in the Allwinner boot0 bootloader.
479 config DRAM_TIMINGS_DDR3_1066F_1333H
480 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
482 Use the timings of the standard JEDEC DDR3-1066F speed bin for
483 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
484 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
485 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
486 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
487 that down binning to DDR3-1066F is supported (because DDR3-1066F
488 uses a bit faster timings than DDR3-1333H).
490 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
491 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
493 Use the timings of the slowest possible JEDEC speed bin for the
494 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
495 DDR3-800E, DDR3-1066G or DDR3-1333J.
502 config DRAM_ODT_CORRECTION
503 int "sunxi dram odt correction value"
506 Set the dram odt correction value (range -255 - 255). In allwinner
507 fex files, this option is found in bits 8-15 of the u32 odt_en variable
508 in the [dram] section. When bit 31 of the odt_en variable is set
509 then the correction is negative. Usually the value for this is 0.
513 default 1008000000 if MACH_SUN4I
514 default 1008000000 if MACH_SUN5I
515 default 1008000000 if MACH_SUN6I
516 default 912000000 if MACH_SUN7I
517 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
518 default 1008000000 if MACH_SUN8I
519 default 1008000000 if MACH_SUN9I
520 default 888000000 if MACH_SUN50I_H6
522 config SYS_CONFIG_NAME
523 default "sun4i" if MACH_SUN4I
524 default "sun5i" if MACH_SUN5I
525 default "sun6i" if MACH_SUN6I
526 default "sun7i" if MACH_SUN7I
527 default "sun8i" if MACH_SUN8I
528 default "sun9i" if MACH_SUN9I
529 default "sun50i" if MACH_SUN50I
530 default "sun50i" if MACH_SUN50I_H6
539 bool "UART0 on MicroSD breakout board"
542 Repurpose the SD card slot for getting access to the UART0 serial
543 console. Primarily useful only for low level u-boot debugging on
544 tablets, where normal UART0 is difficult to access and requires
545 device disassembly and/or soldering. As the SD card can't be used
546 at the same time, the system can be only booted in the FEL mode.
547 Only enable this if you really know what you are doing.
549 config OLD_SUNXI_KERNEL_COMPAT
550 bool "Enable workarounds for booting old kernels"
553 Set this to enable various workarounds for old kernels, this results in
554 sub-optimal settings for newer kernels, only enable if needed.
557 string "MAC power pin"
560 Set the pin used to power the MAC. This takes a string in the format
561 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
564 string "Card detect pin for mmc0"
565 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
568 Set the card detect pin for mmc0, leave empty to not use cd. This
569 takes a string in the format understood by sunxi_name_to_gpio, e.g.
570 PH1 for pin 1 of port H.
573 string "Card detect pin for mmc1"
576 See MMC0_CD_PIN help text.
579 string "Card detect pin for mmc2"
582 See MMC0_CD_PIN help text.
585 string "Card detect pin for mmc3"
588 See MMC0_CD_PIN help text.
591 string "Pins for mmc1"
594 Set the pins used for mmc1, when applicable. This takes a string in the
595 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
598 string "Pins for mmc2"
601 See MMC1_PINS help text.
604 string "Pins for mmc3"
607 See MMC1_PINS help text.
609 config MMC_SUNXI_SLOT_EXTRA
610 int "mmc extra slot number"
613 sunxi builds always enable mmc0, some boards also have a second sdcard
614 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
617 config INITIAL_USB_SCAN_DELAY
618 int "delay initial usb scan by x ms to allow builtin devices to init"
621 Some boards have on board usb devices which need longer than the
622 USB spec's 1 second to connect from board powerup. Set this config
623 option to a non 0 value to add an extra delay before the first usb
627 string "Vbus enable pin for usb0 (otg)"
630 Set the Vbus enable pin for usb0 (otg). This takes a string in the
631 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
634 string "Vbus detect pin for usb0 (otg)"
637 Set the Vbus detect pin for usb0 (otg). This takes a string in the
638 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
641 string "ID detect pin for usb0 (otg)"
644 Set the ID detect pin for usb0 (otg). This takes a string in the
645 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
648 string "Vbus enable pin for usb1 (ehci0)"
649 default "PH6" if MACH_SUN4I || MACH_SUN7I
650 default "PH27" if MACH_SUN6I
652 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
653 a string in the format understood by sunxi_name_to_gpio, e.g.
654 PH1 for pin 1 of port H.
657 string "Vbus enable pin for usb2 (ehci1)"
658 default "PH3" if MACH_SUN4I || MACH_SUN7I
659 default "PH24" if MACH_SUN6I
661 See USB1_VBUS_PIN help text.
664 string "Vbus enable pin for usb3 (ehci2)"
667 See USB1_VBUS_PIN help text.
670 bool "Enable I2C/TWI controller 0"
671 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
672 default n if MACH_SUN6I || MACH_SUN8I
675 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
676 its clock and setting up the bus. This is especially useful on devices
677 with slaves connected to the bus or with pins exposed through e.g. an
678 expansion port/header.
681 bool "Enable I2C/TWI controller 1"
685 See I2C0_ENABLE help text.
688 bool "Enable I2C/TWI controller 2"
692 See I2C0_ENABLE help text.
694 if MACH_SUN6I || MACH_SUN7I
696 bool "Enable I2C/TWI controller 3"
700 See I2C0_ENABLE help text.
705 bool "Enable the PRCM I2C/TWI controller"
706 # This is used for the pmic on H3
707 default y if SY8106A_POWER
710 Set this to y to enable the I2C controller which is part of the PRCM.
715 bool "Enable I2C/TWI controller 4"
719 See I2C0_ENABLE help text.
723 bool "Enable support for gpio-s on axp PMICs"
726 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
729 bool "Enable graphical uboot console on HDMI, LCD or VGA"
730 depends on !MACH_SUN8I_A83T
731 depends on !MACH_SUNXI_H3_H5
732 depends on !MACH_SUN8I_R40
733 depends on !MACH_SUN8I_V3S
734 depends on !MACH_SUN9I
735 depends on !MACH_SUN50I
736 depends on !MACH_SUN50I_H6
738 imply VIDEO_DT_SIMPLEFB
741 Say Y here to add support for using a cfb console on the HDMI, LCD
742 or VGA output found on most sunxi devices. See doc/README.video for
743 info on how to select the video output and mode.
746 bool "HDMI output support"
747 depends on VIDEO_SUNXI && !MACH_SUN8I
750 Say Y here to add support for outputting video over HDMI.
753 bool "VGA output support"
754 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
757 Say Y here to add support for outputting video over VGA.
759 config VIDEO_VGA_VIA_LCD
760 bool "VGA via LCD controller support"
761 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
764 Say Y here to add support for external DACs connected to the parallel
765 LCD interface driving a VGA connector, such as found on the
768 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
769 bool "Force sync active high for VGA via LCD controller support"
770 depends on VIDEO_VGA_VIA_LCD
773 Say Y here if you've a board which uses opendrain drivers for the vga
774 hsync and vsync signals. Opendrain drivers cannot generate steep enough
775 positive edges for a stable video output, so on boards with opendrain
776 drivers the sync signals must always be active high.
778 config VIDEO_VGA_EXTERNAL_DAC_EN
779 string "LCD panel power enable pin"
780 depends on VIDEO_VGA_VIA_LCD
783 Set the enable pin for the external VGA DAC. This takes a string in the
784 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
786 config VIDEO_COMPOSITE
787 bool "Composite video output support"
788 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
791 Say Y here to add support for outputting composite video.
793 config VIDEO_LCD_MODE
794 string "LCD panel timing details"
795 depends on VIDEO_SUNXI
798 LCD panel timing details string, leave empty if there is no LCD panel.
799 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
800 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
801 Also see: http://linux-sunxi.org/LCD
803 config VIDEO_LCD_DCLK_PHASE
804 int "LCD panel display clock phase"
805 depends on VIDEO_SUNXI || DM_VIDEO
808 Select LCD panel display clock phase shift, range 0-3.
810 config VIDEO_LCD_POWER
811 string "LCD panel power enable pin"
812 depends on VIDEO_SUNXI
815 Set the power enable pin for the LCD panel. This takes a string in the
816 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
818 config VIDEO_LCD_RESET
819 string "LCD panel reset pin"
820 depends on VIDEO_SUNXI
823 Set the reset pin for the LCD panel. This takes a string in the format
824 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
826 config VIDEO_LCD_BL_EN
827 string "LCD panel backlight enable pin"
828 depends on VIDEO_SUNXI
831 Set the backlight enable pin for the LCD panel. This takes a string in the
832 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
835 config VIDEO_LCD_BL_PWM
836 string "LCD panel backlight pwm pin"
837 depends on VIDEO_SUNXI
840 Set the backlight pwm pin for the LCD panel. This takes a string in the
841 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
843 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
844 bool "LCD panel backlight pwm is inverted"
845 depends on VIDEO_SUNXI
848 Set this if the backlight pwm output is active low.
850 config VIDEO_LCD_PANEL_I2C
851 bool "LCD panel needs to be configured via i2c"
852 depends on VIDEO_SUNXI
856 Say y here if the LCD panel needs to be configured via i2c. This
857 will add a bitbang i2c controller using gpios to talk to the LCD.
859 config VIDEO_LCD_PANEL_I2C_SDA
860 string "LCD panel i2c interface SDA pin"
861 depends on VIDEO_LCD_PANEL_I2C
864 Set the SDA pin for the LCD i2c interface. This takes a string in the
865 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
867 config VIDEO_LCD_PANEL_I2C_SCL
868 string "LCD panel i2c interface SCL pin"
869 depends on VIDEO_LCD_PANEL_I2C
872 Set the SCL pin for the LCD i2c interface. This takes a string in the
873 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
876 # Note only one of these may be selected at a time! But hidden choices are
877 # not supported by Kconfig
878 config VIDEO_LCD_IF_PARALLEL
881 config VIDEO_LCD_IF_LVDS
889 bool "Display Engine 2 video driver"
893 imply VIDEO_DT_SIMPLEFB
896 Say y here if you want to build DE2 video driver which is present on
897 newer SoCs. Currently only HDMI output is supported.
901 prompt "LCD panel support"
902 depends on VIDEO_SUNXI
904 Select which type of LCD panel to support.
906 config VIDEO_LCD_PANEL_PARALLEL
907 bool "Generic parallel interface LCD panel"
908 select VIDEO_LCD_IF_PARALLEL
910 config VIDEO_LCD_PANEL_LVDS
911 bool "Generic lvds interface LCD panel"
912 select VIDEO_LCD_IF_LVDS
914 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
915 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
916 select VIDEO_LCD_SSD2828
917 select VIDEO_LCD_IF_PARALLEL
919 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
921 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
922 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
923 select VIDEO_LCD_ANX9804
924 select VIDEO_LCD_IF_PARALLEL
925 select VIDEO_LCD_PANEL_I2C
927 Select this for eDP LCD panels with 4 lanes running at 1.62G,
928 connected via an ANX9804 bridge chip.
930 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
931 bool "Hitachi tx18d42vm LCD panel"
932 select VIDEO_LCD_HITACHI_TX18D42VM
933 select VIDEO_LCD_IF_LVDS
935 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
937 config VIDEO_LCD_TL059WV5C0
938 bool "tl059wv5c0 LCD panel"
939 select VIDEO_LCD_PANEL_I2C
940 select VIDEO_LCD_IF_PARALLEL
942 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
943 Aigo M60/M608/M606 tablets.
948 string "SATA power pin"
951 Set the pins used to power the SATA. This takes a string in the
952 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
956 int "GMAC Transmit Clock Delay Chain"
959 Set the GMAC Transmit Clock Delay Chain value.
961 config SPL_STACK_R_ADDR
962 default 0x4fe00000 if MACH_SUN4I
963 default 0x4fe00000 if MACH_SUN5I
964 default 0x4fe00000 if MACH_SUN6I
965 default 0x4fe00000 if MACH_SUN7I
966 default 0x4fe00000 if MACH_SUN8I
967 default 0x2fe00000 if MACH_SUN9I
968 default 0x4fe00000 if MACH_SUN50I
969 default 0x4fe00000 if MACH_SUN50I_H6
972 bool "Support for SPI Flash on Allwinner SoCs in SPL"
973 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
975 Enable support for SPI Flash. This option allows SPL to read from
976 sunxi SPI Flash. It uses the same method as the boot ROM, so does
977 not need any extra configuration.
979 config PINE64_DT_SELECTION
980 bool "Enable Pine64 device tree selection code"
981 depends on MACH_SUN50I
983 The original Pine A64 and Pine A64+ are similar but different
984 boards and can be differed by the DRAM size. Pine A64 has
985 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
986 option, the device tree selection code specific to Pine64 which
987 utilizes the DRAM size will be enabled.