4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
158 select DM_SCSI if SCSI
161 select SUNXI_GEN_SUN4I
165 bool "sun5i (Allwinner A13)"
167 select ARM_CORTEX_CPU_IS_UP
170 select SUNXI_GEN_SUN4I
172 imply CONS_INDEX_2 if !DM_SERIAL
175 bool "sun6i (Allwinner A31)"
177 select CPU_V7_HAS_NONSEC
178 select CPU_V7_HAS_VIRT
179 select ARCH_SUPPORT_PSCI
184 select SUNXI_GEN_SUN6I
186 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
189 bool "sun7i (Allwinner A20)"
191 select CPU_V7_HAS_NONSEC
192 select CPU_V7_HAS_VIRT
193 select ARCH_SUPPORT_PSCI
196 select SUNXI_GEN_SUN4I
198 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
200 config MACH_SUN8I_A23
201 bool "sun8i (Allwinner A23)"
203 select CPU_V7_HAS_NONSEC
204 select CPU_V7_HAS_VIRT
205 select ARCH_SUPPORT_PSCI
206 select DRAM_SUN8I_A23
208 select SUNXI_GEN_SUN6I
210 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
211 imply CONS_INDEX_5 if !DM_SERIAL
213 config MACH_SUN8I_A33
214 bool "sun8i (Allwinner A33)"
216 select CPU_V7_HAS_NONSEC
217 select CPU_V7_HAS_VIRT
218 select ARCH_SUPPORT_PSCI
219 select DRAM_SUN8I_A33
221 select SUNXI_GEN_SUN6I
223 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
224 imply CONS_INDEX_5 if !DM_SERIAL
226 config MACH_SUN8I_A83T
227 bool "sun8i (Allwinner A83T)"
229 select DRAM_SUN8I_A83T
231 select SUNXI_GEN_SUN6I
232 select MMC_SUNXI_HAS_NEW_MODE
236 bool "sun8i (Allwinner H3)"
238 select CPU_V7_HAS_NONSEC
239 select CPU_V7_HAS_VIRT
240 select ARCH_SUPPORT_PSCI
241 select MACH_SUNXI_H3_H5
242 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
244 config MACH_SUN8I_R40
245 bool "sun8i (Allwinner R40)"
247 select CPU_V7_HAS_NONSEC
248 select CPU_V7_HAS_VIRT
249 select ARCH_SUPPORT_PSCI
250 select SUNXI_GEN_SUN6I
253 select SUNXI_DRAM_DW_32BIT
255 config MACH_SUN8I_V3S
256 bool "sun8i (Allwinner V3s)"
258 select CPU_V7_HAS_NONSEC
259 select CPU_V7_HAS_VIRT
260 select ARCH_SUPPORT_PSCI
261 select SUNXI_GEN_SUN6I
263 select SUNXI_DRAM_DW_16BIT
265 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
268 bool "sun9i (Allwinner A80)"
272 select SUNXI_GEN_SUN6I
277 bool "sun50i (Allwinner A64)"
283 select SUNXI_GEN_SUN6I
286 select SUNXI_DRAM_DW_32BIT
289 select SUNXI_A64_TIMER_ERRATUM
291 config MACH_SUN50I_H5
292 bool "sun50i (Allwinner H5)"
294 select MACH_SUNXI_H3_H5
298 config MACH_SUN50I_H6
299 bool "sun50i (Allwinner H6)"
304 select DRAM_SUN50I_H6
308 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
313 default y if MACH_SUN8I_A23
314 default y if MACH_SUN8I_A33
315 default y if MACH_SUN8I_A83T
316 default y if MACH_SUNXI_H3_H5
317 default y if MACH_SUN8I_R40
318 default y if MACH_SUN8I_V3S
320 config RESERVE_ALLWINNER_BOOT0_HEADER
321 bool "reserve space for Allwinner boot0 header"
322 select ENABLE_ARM_SOC_BOOT0_HOOK
324 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
325 filled with magic values post build. The Allwinner provided boot0
326 blob relies on this information to load and execute U-Boot.
327 Only needed on 64-bit Allwinner boards so far when using boot0.
329 config ARM_BOOT_HOOK_RMR
333 select ENABLE_ARM_SOC_BOOT0_HOOK
335 Insert some ARM32 code at the very beginning of the U-Boot binary
336 which uses an RMR register write to bring the core into AArch64 mode.
337 The very first instruction acts as a switch, since it's carefully
338 chosen to be a NOP in one mode and a branch in the other, so the
339 code would only be executed if not already in AArch64.
340 This allows both the SPL and the U-Boot proper to be entered in
341 either mode and switch to AArch64 if needed.
344 config SUNXI_DRAM_DDR3
347 config SUNXI_DRAM_DDR2
350 config SUNXI_DRAM_LPDDR3
354 prompt "DRAM Type and Timing"
355 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
356 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
358 config SUNXI_DRAM_DDR3_1333
360 select SUNXI_DRAM_DDR3
361 depends on !MACH_SUN8I_V3S
363 This option is the original only supported memory type, which suits
364 many H3/H5/A64 boards available now.
366 config SUNXI_DRAM_LPDDR3_STOCK
367 bool "LPDDR3 with Allwinner stock configuration"
368 select SUNXI_DRAM_LPDDR3
370 This option is the LPDDR3 timing used by the stock boot0 by
373 config SUNXI_DRAM_DDR2_V3S
374 bool "DDR2 found in V3s chip"
375 select SUNXI_DRAM_DDR2
376 depends on MACH_SUN8I_V3S
378 This option is only for the DDR2 memory chip which is co-packaged in
385 int "sunxi dram type"
386 depends on MACH_SUN8I_A83T
389 Set the dram type, 3: DDR3, 7: LPDDR3
392 int "sunxi dram clock speed"
393 default 792 if MACH_SUN9I
394 default 648 if MACH_SUN8I_R40
395 default 312 if MACH_SUN6I || MACH_SUN8I
396 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
398 default 672 if MACH_SUN50I
399 default 744 if MACH_SUN50I_H6
401 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
402 must be a multiple of 24. For the sun9i (A80), the tested values
403 (for DDR3-1600) are 312 to 792.
405 if MACH_SUN5I || MACH_SUN7I
407 int "sunxi mbus clock speed"
410 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
415 int "sunxi dram zq value"
416 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
417 default 127 if MACH_SUN7I
418 default 14779 if MACH_SUN8I_V3S
419 default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
420 default 4145117 if MACH_SUN9I
421 default 3881915 if MACH_SUN50I
423 Set the dram zq value.
426 bool "sunxi dram odt enable"
427 default y if MACH_SUN8I_A23
428 default y if MACH_SUN8I_R40
429 default y if MACH_SUN50I
430 default y if MACH_SUN50I_H6
432 Select this to enable dram odt (on die termination).
434 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
436 int "sunxi dram emr1 value"
437 default 0 if MACH_SUN4I
438 default 4 if MACH_SUN5I || MACH_SUN7I
440 Set the dram controller emr1 value.
443 hex "sunxi dram tpr3 value"
446 Set the dram controller tpr3 parameter. This parameter configures
447 the delay on the command lane and also phase shifts, which are
448 applied for sampling incoming read data. The default value 0
449 means that no phase/delay adjustments are necessary. Properly
450 configuring this parameter increases reliability at high DRAM
453 config DRAM_DQS_GATING_DELAY
454 hex "sunxi dram dqs_gating_delay value"
457 Set the dram controller dqs_gating_delay parmeter. Each byte
458 encodes the DQS gating delay for each byte lane. The delay
459 granularity is 1/4 cycle. For example, the value 0x05060606
460 means that the delay is 5 quarter-cycles for one lane (1.25
461 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
462 The default value 0 means autodetection. The results of hardware
463 autodetection are not very reliable and depend on the chip
464 temperature (sometimes producing different results on cold start
465 and warm reboot). But the accuracy of hardware autodetection
466 is usually good enough, unless running at really high DRAM
467 clocks speeds (up to 600MHz). If unsure, keep as 0.
470 prompt "sunxi dram timings"
471 default DRAM_TIMINGS_VENDOR_MAGIC
473 Select the timings of the DDR3 chips.
475 config DRAM_TIMINGS_VENDOR_MAGIC
476 bool "Magic vendor timings from Android"
478 The same DRAM timings as in the Allwinner boot0 bootloader.
480 config DRAM_TIMINGS_DDR3_1066F_1333H
481 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
483 Use the timings of the standard JEDEC DDR3-1066F speed bin for
484 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
485 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
486 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
487 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
488 that down binning to DDR3-1066F is supported (because DDR3-1066F
489 uses a bit faster timings than DDR3-1333H).
491 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
492 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
494 Use the timings of the slowest possible JEDEC speed bin for the
495 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
496 DDR3-800E, DDR3-1066G or DDR3-1333J.
503 config DRAM_ODT_CORRECTION
504 int "sunxi dram odt correction value"
507 Set the dram odt correction value (range -255 - 255). In allwinner
508 fex files, this option is found in bits 8-15 of the u32 odt_en variable
509 in the [dram] section. When bit 31 of the odt_en variable is set
510 then the correction is negative. Usually the value for this is 0.
514 default 1008000000 if MACH_SUN4I
515 default 1008000000 if MACH_SUN5I
516 default 1008000000 if MACH_SUN6I
517 default 912000000 if MACH_SUN7I
518 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
519 default 1008000000 if MACH_SUN8I
520 default 1008000000 if MACH_SUN9I
521 default 888000000 if MACH_SUN50I_H6
523 config SYS_CONFIG_NAME
524 default "sun4i" if MACH_SUN4I
525 default "sun5i" if MACH_SUN5I
526 default "sun6i" if MACH_SUN6I
527 default "sun7i" if MACH_SUN7I
528 default "sun8i" if MACH_SUN8I
529 default "sun9i" if MACH_SUN9I
530 default "sun50i" if MACH_SUN50I
531 default "sun50i" if MACH_SUN50I_H6
540 bool "UART0 on MicroSD breakout board"
543 Repurpose the SD card slot for getting access to the UART0 serial
544 console. Primarily useful only for low level u-boot debugging on
545 tablets, where normal UART0 is difficult to access and requires
546 device disassembly and/or soldering. As the SD card can't be used
547 at the same time, the system can be only booted in the FEL mode.
548 Only enable this if you really know what you are doing.
550 config OLD_SUNXI_KERNEL_COMPAT
551 bool "Enable workarounds for booting old kernels"
554 Set this to enable various workarounds for old kernels, this results in
555 sub-optimal settings for newer kernels, only enable if needed.
558 string "MAC power pin"
561 Set the pin used to power the MAC. This takes a string in the format
562 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
565 string "Card detect pin for mmc0"
566 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
569 Set the card detect pin for mmc0, leave empty to not use cd. This
570 takes a string in the format understood by sunxi_name_to_gpio, e.g.
571 PH1 for pin 1 of port H.
574 string "Card detect pin for mmc1"
577 See MMC0_CD_PIN help text.
580 string "Card detect pin for mmc2"
583 See MMC0_CD_PIN help text.
586 string "Card detect pin for mmc3"
589 See MMC0_CD_PIN help text.
592 string "Pins for mmc1"
595 Set the pins used for mmc1, when applicable. This takes a string in the
596 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
599 string "Pins for mmc2"
602 See MMC1_PINS help text.
605 string "Pins for mmc3"
608 See MMC1_PINS help text.
610 config MMC_SUNXI_SLOT_EXTRA
611 int "mmc extra slot number"
614 sunxi builds always enable mmc0, some boards also have a second sdcard
615 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
618 config INITIAL_USB_SCAN_DELAY
619 int "delay initial usb scan by x ms to allow builtin devices to init"
622 Some boards have on board usb devices which need longer than the
623 USB spec's 1 second to connect from board powerup. Set this config
624 option to a non 0 value to add an extra delay before the first usb
628 string "Vbus enable pin for usb0 (otg)"
631 Set the Vbus enable pin for usb0 (otg). This takes a string in the
632 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
635 string "Vbus detect pin for usb0 (otg)"
638 Set the Vbus detect pin for usb0 (otg). This takes a string in the
639 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
642 string "ID detect pin for usb0 (otg)"
645 Set the ID detect pin for usb0 (otg). This takes a string in the
646 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
649 string "Vbus enable pin for usb1 (ehci0)"
650 default "PH6" if MACH_SUN4I || MACH_SUN7I
651 default "PH27" if MACH_SUN6I
653 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
654 a string in the format understood by sunxi_name_to_gpio, e.g.
655 PH1 for pin 1 of port H.
658 string "Vbus enable pin for usb2 (ehci1)"
659 default "PH3" if MACH_SUN4I || MACH_SUN7I
660 default "PH24" if MACH_SUN6I
662 See USB1_VBUS_PIN help text.
665 string "Vbus enable pin for usb3 (ehci2)"
668 See USB1_VBUS_PIN help text.
671 bool "Enable I2C/TWI controller 0"
672 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
673 default n if MACH_SUN6I || MACH_SUN8I
676 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
677 its clock and setting up the bus. This is especially useful on devices
678 with slaves connected to the bus or with pins exposed through e.g. an
679 expansion port/header.
682 bool "Enable I2C/TWI controller 1"
686 See I2C0_ENABLE help text.
689 bool "Enable I2C/TWI controller 2"
693 See I2C0_ENABLE help text.
695 if MACH_SUN6I || MACH_SUN7I
697 bool "Enable I2C/TWI controller 3"
701 See I2C0_ENABLE help text.
706 bool "Enable the PRCM I2C/TWI controller"
707 # This is used for the pmic on H3
708 default y if SY8106A_POWER
711 Set this to y to enable the I2C controller which is part of the PRCM.
716 bool "Enable I2C/TWI controller 4"
720 See I2C0_ENABLE help text.
724 bool "Enable support for gpio-s on axp PMICs"
727 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
730 bool "Enable graphical uboot console on HDMI, LCD or VGA"
731 depends on !MACH_SUN8I_A83T
732 depends on !MACH_SUNXI_H3_H5
733 depends on !MACH_SUN8I_R40
734 depends on !MACH_SUN8I_V3S
735 depends on !MACH_SUN9I
736 depends on !MACH_SUN50I
737 depends on !MACH_SUN50I_H6
739 imply VIDEO_DT_SIMPLEFB
742 Say Y here to add support for using a cfb console on the HDMI, LCD
743 or VGA output found on most sunxi devices. See doc/README.video for
744 info on how to select the video output and mode.
747 bool "HDMI output support"
748 depends on VIDEO_SUNXI && !MACH_SUN8I
751 Say Y here to add support for outputting video over HDMI.
754 bool "VGA output support"
755 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
758 Say Y here to add support for outputting video over VGA.
760 config VIDEO_VGA_VIA_LCD
761 bool "VGA via LCD controller support"
762 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
765 Say Y here to add support for external DACs connected to the parallel
766 LCD interface driving a VGA connector, such as found on the
769 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
770 bool "Force sync active high for VGA via LCD controller support"
771 depends on VIDEO_VGA_VIA_LCD
774 Say Y here if you've a board which uses opendrain drivers for the vga
775 hsync and vsync signals. Opendrain drivers cannot generate steep enough
776 positive edges for a stable video output, so on boards with opendrain
777 drivers the sync signals must always be active high.
779 config VIDEO_VGA_EXTERNAL_DAC_EN
780 string "LCD panel power enable pin"
781 depends on VIDEO_VGA_VIA_LCD
784 Set the enable pin for the external VGA DAC. This takes a string in the
785 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
787 config VIDEO_COMPOSITE
788 bool "Composite video output support"
789 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
792 Say Y here to add support for outputting composite video.
794 config VIDEO_LCD_MODE
795 string "LCD panel timing details"
796 depends on VIDEO_SUNXI
799 LCD panel timing details string, leave empty if there is no LCD panel.
800 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
801 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
802 Also see: http://linux-sunxi.org/LCD
804 config VIDEO_LCD_DCLK_PHASE
805 int "LCD panel display clock phase"
806 depends on VIDEO_SUNXI || DM_VIDEO
809 Select LCD panel display clock phase shift, range 0-3.
811 config VIDEO_LCD_POWER
812 string "LCD panel power enable pin"
813 depends on VIDEO_SUNXI
816 Set the power enable pin for the LCD panel. This takes a string in the
817 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
819 config VIDEO_LCD_RESET
820 string "LCD panel reset pin"
821 depends on VIDEO_SUNXI
824 Set the reset pin for the LCD panel. This takes a string in the format
825 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
827 config VIDEO_LCD_BL_EN
828 string "LCD panel backlight enable pin"
829 depends on VIDEO_SUNXI
832 Set the backlight enable pin for the LCD panel. This takes a string in the
833 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
836 config VIDEO_LCD_BL_PWM
837 string "LCD panel backlight pwm pin"
838 depends on VIDEO_SUNXI
841 Set the backlight pwm pin for the LCD panel. This takes a string in the
842 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
844 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
845 bool "LCD panel backlight pwm is inverted"
846 depends on VIDEO_SUNXI
849 Set this if the backlight pwm output is active low.
851 config VIDEO_LCD_PANEL_I2C
852 bool "LCD panel needs to be configured via i2c"
853 depends on VIDEO_SUNXI
857 Say y here if the LCD panel needs to be configured via i2c. This
858 will add a bitbang i2c controller using gpios to talk to the LCD.
860 config VIDEO_LCD_PANEL_I2C_SDA
861 string "LCD panel i2c interface SDA pin"
862 depends on VIDEO_LCD_PANEL_I2C
865 Set the SDA pin for the LCD i2c interface. This takes a string in the
866 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
868 config VIDEO_LCD_PANEL_I2C_SCL
869 string "LCD panel i2c interface SCL pin"
870 depends on VIDEO_LCD_PANEL_I2C
873 Set the SCL pin for the LCD i2c interface. This takes a string in the
874 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
877 # Note only one of these may be selected at a time! But hidden choices are
878 # not supported by Kconfig
879 config VIDEO_LCD_IF_PARALLEL
882 config VIDEO_LCD_IF_LVDS
890 bool "Display Engine 2 video driver"
894 imply VIDEO_DT_SIMPLEFB
897 Say y here if you want to build DE2 video driver which is present on
898 newer SoCs. Currently only HDMI output is supported.
902 prompt "LCD panel support"
903 depends on VIDEO_SUNXI
905 Select which type of LCD panel to support.
907 config VIDEO_LCD_PANEL_PARALLEL
908 bool "Generic parallel interface LCD panel"
909 select VIDEO_LCD_IF_PARALLEL
911 config VIDEO_LCD_PANEL_LVDS
912 bool "Generic lvds interface LCD panel"
913 select VIDEO_LCD_IF_LVDS
915 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
916 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
917 select VIDEO_LCD_SSD2828
918 select VIDEO_LCD_IF_PARALLEL
920 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
922 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
923 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
924 select VIDEO_LCD_ANX9804
925 select VIDEO_LCD_IF_PARALLEL
926 select VIDEO_LCD_PANEL_I2C
928 Select this for eDP LCD panels with 4 lanes running at 1.62G,
929 connected via an ANX9804 bridge chip.
931 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
932 bool "Hitachi tx18d42vm LCD panel"
933 select VIDEO_LCD_HITACHI_TX18D42VM
934 select VIDEO_LCD_IF_LVDS
936 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
938 config VIDEO_LCD_TL059WV5C0
939 bool "tl059wv5c0 LCD panel"
940 select VIDEO_LCD_PANEL_I2C
941 select VIDEO_LCD_IF_PARALLEL
943 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
944 Aigo M60/M608/M606 tablets.
949 string "SATA power pin"
952 Set the pins used to power the SATA. This takes a string in the
953 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
957 int "GMAC Transmit Clock Delay Chain"
960 Set the GMAC Transmit Clock Delay Chain value.
962 config SPL_STACK_R_ADDR
963 default 0x4fe00000 if MACH_SUN4I
964 default 0x4fe00000 if MACH_SUN5I
965 default 0x4fe00000 if MACH_SUN6I
966 default 0x4fe00000 if MACH_SUN7I
967 default 0x4fe00000 if MACH_SUN8I
968 default 0x2fe00000 if MACH_SUN9I
969 default 0x4fe00000 if MACH_SUN50I
970 default 0x4fe00000 if MACH_SUN50I_H6
973 bool "Support for SPI Flash on Allwinner SoCs in SPL"
974 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
976 Enable support for SPI Flash. This option allows SPL to read from
977 sunxi SPI Flash. It uses the same method as the boot ROM, so does
978 not need any extra configuration.
980 config PINE64_DT_SELECTION
981 bool "Enable Pine64 device tree selection code"
982 depends on MACH_SUN50I
984 The original Pine A64 and Pine A64+ are similar but different
985 boards and can be differed by the DRAM size. Pine A64 has
986 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
987 option, the device tree selection code specific to Pine64 which
988 utilizes the DRAM size will be enabled.