4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun6i platforms,
16 bool "Allwinner sun6i internal P2WI controller"
18 If you say yes to this option, support will be included for the
19 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
21 The P2WI looks like an SMBus controller (which supports only byte
22 accesses), except that it only supports one slave device.
23 This interface is used to connect to specific PMIC devices (like the
29 Support for the PRCM (Power/Reset/Clock Management) unit available
33 bool "Sunxi AXP PMIC bus access helpers"
35 Select this PMIC bus access helpers for Sunxi platform PRCM or other
36 AXP family PMIC devices.
39 bool "Allwinner sunXi Reduced Serial Bus Driver"
41 Say y here to enable support for Allwinner's Reduced Serial Bus
42 (RSB) support. This controller is responsible for communicating
43 with various RSB based devices, such as AXP223, AXP8XX PMICs,
46 config SUNXI_HIGH_SRAM
50 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
51 with the first SRAM region being located at address 0.
52 Some newer SoCs map the boot ROM at address 0 instead and move the
53 SRAM to 64KB, just behind the mask ROM.
54 Chips using the latter setup are supposed to select this option to
55 adjust the addresses accordingly.
57 # Note only one of these may be selected at a time! But hidden choices are
58 # not supported by Kconfig
59 config SUNXI_GEN_SUN4I
62 Select this for sunxi SoCs which have resets and clocks set up
63 as the original A10 (mach-sun4i).
65 config SUNXI_GEN_SUN6I
68 Select this for sunxi SoCs which have sun6i like periphery, like
69 separate ahb reset control registers, custom pmic bus, new style
75 Select this for sunxi SoCs which uses a DRAM controller like the
76 DesignWare controller used in H3, mainly SoCs after H3, which do
77 not have official open-source DRAM initialization code, but can
78 use modified H3 DRAM initialization code.
81 config SUNXI_DRAM_DW_16BIT
84 Select this for sunxi SoCs with DesignWare DRAM controller and
85 have only 16-bit memory buswidth.
87 config SUNXI_DRAM_DW_32BIT
90 Select this for sunxi SoCs with DesignWare DRAM controller with
91 32-bit memory buswidth.
94 config MACH_SUNXI_H3_H5
99 select SUNXI_DRAM_DW_32BIT
100 select SUNXI_GEN_SUN6I
104 prompt "Sunxi SoC Variant"
108 bool "sun4i (Allwinner A10)"
110 select ARM_CORTEX_CPU_IS_UP
111 select SUNXI_GEN_SUN4I
115 bool "sun5i (Allwinner A13)"
117 select ARM_CORTEX_CPU_IS_UP
118 select SUNXI_GEN_SUN4I
120 imply CONS_INDEX_2 if !DM_SERIAL
123 bool "sun6i (Allwinner A31)"
125 select CPU_V7_HAS_NONSEC
126 select CPU_V7_HAS_VIRT
127 select ARCH_SUPPORT_PSCI
131 select SUNXI_GEN_SUN6I
133 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 bool "sun7i (Allwinner A20)"
138 select CPU_V7_HAS_NONSEC
139 select CPU_V7_HAS_VIRT
140 select ARCH_SUPPORT_PSCI
141 select SUNXI_GEN_SUN4I
143 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
145 config MACH_SUN8I_A23
146 bool "sun8i (Allwinner A23)"
148 select CPU_V7_HAS_NONSEC
149 select CPU_V7_HAS_VIRT
150 select ARCH_SUPPORT_PSCI
151 select SUNXI_GEN_SUN6I
153 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
154 imply CONS_INDEX_5 if !DM_SERIAL
156 config MACH_SUN8I_A33
157 bool "sun8i (Allwinner A33)"
159 select CPU_V7_HAS_NONSEC
160 select CPU_V7_HAS_VIRT
161 select ARCH_SUPPORT_PSCI
162 select SUNXI_GEN_SUN6I
164 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
165 imply CONS_INDEX_5 if !DM_SERIAL
167 config MACH_SUN8I_A83T
168 bool "sun8i (Allwinner A83T)"
170 select SUNXI_GEN_SUN6I
171 select MMC_SUNXI_HAS_NEW_MODE
175 bool "sun8i (Allwinner H3)"
177 select CPU_V7_HAS_NONSEC
178 select CPU_V7_HAS_VIRT
179 select ARCH_SUPPORT_PSCI
180 select MACH_SUNXI_H3_H5
181 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
183 config MACH_SUN8I_R40
184 bool "sun8i (Allwinner R40)"
186 select CPU_V7_HAS_NONSEC
187 select CPU_V7_HAS_VIRT
188 select ARCH_SUPPORT_PSCI
189 select SUNXI_GEN_SUN6I
192 select SUNXI_DRAM_DW_32BIT
194 config MACH_SUN8I_V3S
195 bool "sun8i (Allwinner V3s)"
197 select CPU_V7_HAS_NONSEC
198 select CPU_V7_HAS_VIRT
199 select ARCH_SUPPORT_PSCI
200 select SUNXI_GEN_SUN6I
202 select SUNXI_DRAM_DW_16BIT
204 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
207 bool "sun9i (Allwinner A80)"
210 select SUNXI_HIGH_SRAM
211 select SUNXI_GEN_SUN6I
216 bool "sun50i (Allwinner A64)"
220 select SUNXI_GEN_SUN6I
221 select SUNXI_HIGH_SRAM
224 select SUNXI_DRAM_DW_32BIT
228 config MACH_SUN50I_H5
229 bool "sun50i (Allwinner H5)"
231 select MACH_SUNXI_H3_H5
232 select SUNXI_HIGH_SRAM
238 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
243 default y if MACH_SUN8I_A23
244 default y if MACH_SUN8I_A33
245 default y if MACH_SUN8I_A83T
246 default y if MACH_SUNXI_H3_H5
247 default y if MACH_SUN8I_R40
248 default y if MACH_SUN8I_V3S
250 config RESERVE_ALLWINNER_BOOT0_HEADER
251 bool "reserve space for Allwinner boot0 header"
252 select ENABLE_ARM_SOC_BOOT0_HOOK
254 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
255 filled with magic values post build. The Allwinner provided boot0
256 blob relies on this information to load and execute U-Boot.
257 Only needed on 64-bit Allwinner boards so far when using boot0.
259 config ARM_BOOT_HOOK_RMR
263 select ENABLE_ARM_SOC_BOOT0_HOOK
265 Insert some ARM32 code at the very beginning of the U-Boot binary
266 which uses an RMR register write to bring the core into AArch64 mode.
267 The very first instruction acts as a switch, since it's carefully
268 chosen to be a NOP in one mode and a branch in the other, so the
269 code would only be executed if not already in AArch64.
270 This allows both the SPL and the U-Boot proper to be entered in
271 either mode and switch to AArch64 if needed.
274 config SUNXI_DRAM_DDR3
277 config SUNXI_DRAM_DDR2
280 config SUNXI_DRAM_LPDDR3
284 prompt "DRAM Type and Timing"
285 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
286 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
288 config SUNXI_DRAM_DDR3_1333
290 select SUNXI_DRAM_DDR3
291 depends on !MACH_SUN8I_V3S
293 This option is the original only supported memory type, which suits
294 many H3/H5/A64 boards available now.
296 config SUNXI_DRAM_LPDDR3_STOCK
297 bool "LPDDR3 with Allwinner stock configuration"
298 select SUNXI_DRAM_LPDDR3
300 This option is the LPDDR3 timing used by the stock boot0 by
303 config SUNXI_DRAM_DDR2_V3S
304 bool "DDR2 found in V3s chip"
305 select SUNXI_DRAM_DDR2
306 depends on MACH_SUN8I_V3S
308 This option is only for the DDR2 memory chip which is co-packaged in
315 int "sunxi dram type"
316 depends on MACH_SUN8I_A83T
319 Set the dram type, 3: DDR3, 7: LPDDR3
322 int "sunxi dram clock speed"
323 default 792 if MACH_SUN9I
324 default 648 if MACH_SUN8I_R40
325 default 312 if MACH_SUN6I || MACH_SUN8I
326 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
328 default 672 if MACH_SUN50I
330 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
331 must be a multiple of 24. For the sun9i (A80), the tested values
332 (for DDR3-1600) are 312 to 792.
334 if MACH_SUN5I || MACH_SUN7I
336 int "sunxi mbus clock speed"
339 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
344 int "sunxi dram zq value"
345 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
346 default 127 if MACH_SUN7I
347 default 14779 if MACH_SUN8I_V3S
348 default 3881979 if MACH_SUN8I_R40
349 default 4145117 if MACH_SUN9I
350 default 3881915 if MACH_SUN50I
352 Set the dram zq value.
355 bool "sunxi dram odt enable"
356 default n if !MACH_SUN8I_A23
357 default y if MACH_SUN8I_A23
358 default y if MACH_SUN8I_R40
359 default y if MACH_SUN50I
361 Select this to enable dram odt (on die termination).
363 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
365 int "sunxi dram emr1 value"
366 default 0 if MACH_SUN4I
367 default 4 if MACH_SUN5I || MACH_SUN7I
369 Set the dram controller emr1 value.
372 hex "sunxi dram tpr3 value"
375 Set the dram controller tpr3 parameter. This parameter configures
376 the delay on the command lane and also phase shifts, which are
377 applied for sampling incoming read data. The default value 0
378 means that no phase/delay adjustments are necessary. Properly
379 configuring this parameter increases reliability at high DRAM
382 config DRAM_DQS_GATING_DELAY
383 hex "sunxi dram dqs_gating_delay value"
386 Set the dram controller dqs_gating_delay parmeter. Each byte
387 encodes the DQS gating delay for each byte lane. The delay
388 granularity is 1/4 cycle. For example, the value 0x05060606
389 means that the delay is 5 quarter-cycles for one lane (1.25
390 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
391 The default value 0 means autodetection. The results of hardware
392 autodetection are not very reliable and depend on the chip
393 temperature (sometimes producing different results on cold start
394 and warm reboot). But the accuracy of hardware autodetection
395 is usually good enough, unless running at really high DRAM
396 clocks speeds (up to 600MHz). If unsure, keep as 0.
399 prompt "sunxi dram timings"
400 default DRAM_TIMINGS_VENDOR_MAGIC
402 Select the timings of the DDR3 chips.
404 config DRAM_TIMINGS_VENDOR_MAGIC
405 bool "Magic vendor timings from Android"
407 The same DRAM timings as in the Allwinner boot0 bootloader.
409 config DRAM_TIMINGS_DDR3_1066F_1333H
410 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
412 Use the timings of the standard JEDEC DDR3-1066F speed bin for
413 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
414 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
415 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
416 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
417 that down binning to DDR3-1066F is supported (because DDR3-1066F
418 uses a bit faster timings than DDR3-1333H).
420 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
421 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
423 Use the timings of the slowest possible JEDEC speed bin for the
424 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
425 DDR3-800E, DDR3-1066G or DDR3-1333J.
432 config DRAM_ODT_CORRECTION
433 int "sunxi dram odt correction value"
436 Set the dram odt correction value (range -255 - 255). In allwinner
437 fex files, this option is found in bits 8-15 of the u32 odt_en variable
438 in the [dram] section. When bit 31 of the odt_en variable is set
439 then the correction is negative. Usually the value for this is 0.
443 default 1008000000 if MACH_SUN4I
444 default 1008000000 if MACH_SUN5I
445 default 1008000000 if MACH_SUN6I
446 default 912000000 if MACH_SUN7I
447 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
448 default 1008000000 if MACH_SUN8I
449 default 1008000000 if MACH_SUN9I
451 config SYS_CONFIG_NAME
452 default "sun4i" if MACH_SUN4I
453 default "sun5i" if MACH_SUN5I
454 default "sun6i" if MACH_SUN6I
455 default "sun7i" if MACH_SUN7I
456 default "sun8i" if MACH_SUN8I
457 default "sun9i" if MACH_SUN9I
458 default "sun50i" if MACH_SUN50I
467 bool "UART0 on MicroSD breakout board"
470 Repurpose the SD card slot for getting access to the UART0 serial
471 console. Primarily useful only for low level u-boot debugging on
472 tablets, where normal UART0 is difficult to access and requires
473 device disassembly and/or soldering. As the SD card can't be used
474 at the same time, the system can be only booted in the FEL mode.
475 Only enable this if you really know what you are doing.
477 config OLD_SUNXI_KERNEL_COMPAT
478 bool "Enable workarounds for booting old kernels"
481 Set this to enable various workarounds for old kernels, this results in
482 sub-optimal settings for newer kernels, only enable if needed.
485 string "MAC power pin"
488 Set the pin used to power the MAC. This takes a string in the format
489 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
492 string "Card detect pin for mmc0"
493 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
496 Set the card detect pin for mmc0, leave empty to not use cd. This
497 takes a string in the format understood by sunxi_name_to_gpio, e.g.
498 PH1 for pin 1 of port H.
501 string "Card detect pin for mmc1"
504 See MMC0_CD_PIN help text.
507 string "Card detect pin for mmc2"
510 See MMC0_CD_PIN help text.
513 string "Card detect pin for mmc3"
516 See MMC0_CD_PIN help text.
519 string "Pins for mmc1"
522 Set the pins used for mmc1, when applicable. This takes a string in the
523 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
526 string "Pins for mmc2"
529 See MMC1_PINS help text.
532 string "Pins for mmc3"
535 See MMC1_PINS help text.
537 config MMC_SUNXI_SLOT_EXTRA
538 int "mmc extra slot number"
541 sunxi builds always enable mmc0, some boards also have a second sdcard
542 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
545 config INITIAL_USB_SCAN_DELAY
546 int "delay initial usb scan by x ms to allow builtin devices to init"
549 Some boards have on board usb devices which need longer than the
550 USB spec's 1 second to connect from board powerup. Set this config
551 option to a non 0 value to add an extra delay before the first usb
555 string "Vbus enable pin for usb0 (otg)"
558 Set the Vbus enable pin for usb0 (otg). This takes a string in the
559 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
562 string "Vbus detect pin for usb0 (otg)"
565 Set the Vbus detect pin for usb0 (otg). This takes a string in the
566 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
569 string "ID detect pin for usb0 (otg)"
572 Set the ID detect pin for usb0 (otg). This takes a string in the
573 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
576 string "Vbus enable pin for usb1 (ehci0)"
577 default "PH6" if MACH_SUN4I || MACH_SUN7I
578 default "PH27" if MACH_SUN6I
580 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
581 a string in the format understood by sunxi_name_to_gpio, e.g.
582 PH1 for pin 1 of port H.
585 string "Vbus enable pin for usb2 (ehci1)"
586 default "PH3" if MACH_SUN4I || MACH_SUN7I
587 default "PH24" if MACH_SUN6I
589 See USB1_VBUS_PIN help text.
592 string "Vbus enable pin for usb3 (ehci2)"
595 See USB1_VBUS_PIN help text.
598 bool "Enable I2C/TWI controller 0"
599 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
600 default n if MACH_SUN6I || MACH_SUN8I
603 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
604 its clock and setting up the bus. This is especially useful on devices
605 with slaves connected to the bus or with pins exposed through e.g. an
606 expansion port/header.
609 bool "Enable I2C/TWI controller 1"
613 See I2C0_ENABLE help text.
616 bool "Enable I2C/TWI controller 2"
620 See I2C0_ENABLE help text.
622 if MACH_SUN6I || MACH_SUN7I
624 bool "Enable I2C/TWI controller 3"
628 See I2C0_ENABLE help text.
633 bool "Enable the PRCM I2C/TWI controller"
634 # This is used for the pmic on H3
635 default y if SY8106A_POWER
638 Set this to y to enable the I2C controller which is part of the PRCM.
643 bool "Enable I2C/TWI controller 4"
647 See I2C0_ENABLE help text.
651 bool "Enable support for gpio-s on axp PMICs"
654 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
657 bool "Enable graphical uboot console on HDMI, LCD or VGA"
658 depends on !MACH_SUN8I_A83T
659 depends on !MACH_SUNXI_H3_H5
660 depends on !MACH_SUN8I_R40
661 depends on !MACH_SUN8I_V3S
662 depends on !MACH_SUN9I
663 depends on !MACH_SUN50I
665 imply VIDEO_DT_SIMPLEFB
668 Say Y here to add support for using a cfb console on the HDMI, LCD
669 or VGA output found on most sunxi devices. See doc/README.video for
670 info on how to select the video output and mode.
673 bool "HDMI output support"
674 depends on VIDEO_SUNXI && !MACH_SUN8I
677 Say Y here to add support for outputting video over HDMI.
680 bool "VGA output support"
681 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
684 Say Y here to add support for outputting video over VGA.
686 config VIDEO_VGA_VIA_LCD
687 bool "VGA via LCD controller support"
688 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
691 Say Y here to add support for external DACs connected to the parallel
692 LCD interface driving a VGA connector, such as found on the
695 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
696 bool "Force sync active high for VGA via LCD controller support"
697 depends on VIDEO_VGA_VIA_LCD
700 Say Y here if you've a board which uses opendrain drivers for the vga
701 hsync and vsync signals. Opendrain drivers cannot generate steep enough
702 positive edges for a stable video output, so on boards with opendrain
703 drivers the sync signals must always be active high.
705 config VIDEO_VGA_EXTERNAL_DAC_EN
706 string "LCD panel power enable pin"
707 depends on VIDEO_VGA_VIA_LCD
710 Set the enable pin for the external VGA DAC. This takes a string in the
711 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
713 config VIDEO_COMPOSITE
714 bool "Composite video output support"
715 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
718 Say Y here to add support for outputting composite video.
720 config VIDEO_LCD_MODE
721 string "LCD panel timing details"
722 depends on VIDEO_SUNXI
725 LCD panel timing details string, leave empty if there is no LCD panel.
726 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
727 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
728 Also see: http://linux-sunxi.org/LCD
730 config VIDEO_LCD_DCLK_PHASE
731 int "LCD panel display clock phase"
732 depends on VIDEO_SUNXI || DM_VIDEO
735 Select LCD panel display clock phase shift, range 0-3.
737 config VIDEO_LCD_POWER
738 string "LCD panel power enable pin"
739 depends on VIDEO_SUNXI
742 Set the power enable pin for the LCD panel. This takes a string in the
743 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
745 config VIDEO_LCD_RESET
746 string "LCD panel reset pin"
747 depends on VIDEO_SUNXI
750 Set the reset pin for the LCD panel. This takes a string in the format
751 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
753 config VIDEO_LCD_BL_EN
754 string "LCD panel backlight enable pin"
755 depends on VIDEO_SUNXI
758 Set the backlight enable pin for the LCD panel. This takes a string in the
759 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
762 config VIDEO_LCD_BL_PWM
763 string "LCD panel backlight pwm pin"
764 depends on VIDEO_SUNXI
767 Set the backlight pwm pin for the LCD panel. This takes a string in the
768 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
770 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
771 bool "LCD panel backlight pwm is inverted"
772 depends on VIDEO_SUNXI
775 Set this if the backlight pwm output is active low.
777 config VIDEO_LCD_PANEL_I2C
778 bool "LCD panel needs to be configured via i2c"
779 depends on VIDEO_SUNXI
783 Say y here if the LCD panel needs to be configured via i2c. This
784 will add a bitbang i2c controller using gpios to talk to the LCD.
786 config VIDEO_LCD_PANEL_I2C_SDA
787 string "LCD panel i2c interface SDA pin"
788 depends on VIDEO_LCD_PANEL_I2C
791 Set the SDA pin for the LCD i2c interface. This takes a string in the
792 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
794 config VIDEO_LCD_PANEL_I2C_SCL
795 string "LCD panel i2c interface SCL pin"
796 depends on VIDEO_LCD_PANEL_I2C
799 Set the SCL pin for the LCD i2c interface. This takes a string in the
800 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
803 # Note only one of these may be selected at a time! But hidden choices are
804 # not supported by Kconfig
805 config VIDEO_LCD_IF_PARALLEL
808 config VIDEO_LCD_IF_LVDS
816 bool "Display Engine 2 video driver"
820 imply VIDEO_DT_SIMPLEFB
823 Say y here if you want to build DE2 video driver which is present on
824 newer SoCs. Currently only HDMI output is supported.
828 prompt "LCD panel support"
829 depends on VIDEO_SUNXI
831 Select which type of LCD panel to support.
833 config VIDEO_LCD_PANEL_PARALLEL
834 bool "Generic parallel interface LCD panel"
835 select VIDEO_LCD_IF_PARALLEL
837 config VIDEO_LCD_PANEL_LVDS
838 bool "Generic lvds interface LCD panel"
839 select VIDEO_LCD_IF_LVDS
841 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
842 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
843 select VIDEO_LCD_SSD2828
844 select VIDEO_LCD_IF_PARALLEL
846 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
848 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
849 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
850 select VIDEO_LCD_ANX9804
851 select VIDEO_LCD_IF_PARALLEL
852 select VIDEO_LCD_PANEL_I2C
854 Select this for eDP LCD panels with 4 lanes running at 1.62G,
855 connected via an ANX9804 bridge chip.
857 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
858 bool "Hitachi tx18d42vm LCD panel"
859 select VIDEO_LCD_HITACHI_TX18D42VM
860 select VIDEO_LCD_IF_LVDS
862 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
864 config VIDEO_LCD_TL059WV5C0
865 bool "tl059wv5c0 LCD panel"
866 select VIDEO_LCD_PANEL_I2C
867 select VIDEO_LCD_IF_PARALLEL
869 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
870 Aigo M60/M608/M606 tablets.
875 string "SATA power pin"
878 Set the pins used to power the SATA. This takes a string in the
879 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
883 int "GMAC Transmit Clock Delay Chain"
886 Set the GMAC Transmit Clock Delay Chain value.
888 config SPL_STACK_R_ADDR
889 default 0x4fe00000 if MACH_SUN4I
890 default 0x4fe00000 if MACH_SUN5I
891 default 0x4fe00000 if MACH_SUN6I
892 default 0x4fe00000 if MACH_SUN7I
893 default 0x4fe00000 if MACH_SUN8I
894 default 0x2fe00000 if MACH_SUN9I
895 default 0x4fe00000 if MACH_SUN50I
898 bool "Support for SPI Flash on Allwinner SoCs in SPL"
899 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
901 Enable support for SPI Flash. This option allows SPL to read from
902 sunxi SPI Flash. It uses the same method as the boot ROM, so does
903 not need any extra configuration.