4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
87 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
88 with the first SRAM region being located at address 0.
89 Some newer SoCs map the boot ROM at address 0 instead and move the
90 SRAM to a different address.
92 config SUNXI_A64_TIMER_ERRATUM
95 # Note only one of these may be selected at a time! But hidden choices are
96 # not supported by Kconfig
97 config SUNXI_GEN_SUN4I
100 Select this for sunxi SoCs which have resets and clocks set up
101 as the original A10 (mach-sun4i).
103 config SUNXI_GEN_SUN6I
106 Select this for sunxi SoCs which have sun6i like periphery, like
107 separate ahb reset control registers, custom pmic bus, new style
113 Select this for sunxi SoCs which uses a DRAM controller like the
114 DesignWare controller used in H3, mainly SoCs after H3, which do
115 not have official open-source DRAM initialization code, but can
116 use modified H3 DRAM initialization code.
119 config SUNXI_DRAM_DW_16BIT
122 Select this for sunxi SoCs with DesignWare DRAM controller and
123 have only 16-bit memory buswidth.
125 config SUNXI_DRAM_DW_32BIT
128 Select this for sunxi SoCs with DesignWare DRAM controller with
129 32-bit memory buswidth.
132 config MACH_SUNXI_H3_H5
138 select SUNXI_DRAM_DW_32BIT
139 select SUNXI_GEN_SUN6I
143 prompt "Sunxi SoC Variant"
147 bool "sun4i (Allwinner A10)"
149 select ARM_CORTEX_CPU_IS_UP
151 select DM_SCSI if SCSI
154 select SUNXI_GEN_SUN4I
158 bool "sun5i (Allwinner A13)"
160 select ARM_CORTEX_CPU_IS_UP
163 select SUNXI_GEN_SUN4I
165 imply CONS_INDEX_2 if !DM_SERIAL
168 bool "sun6i (Allwinner A31)"
170 select CPU_V7_HAS_NONSEC
171 select CPU_V7_HAS_VIRT
172 select ARCH_SUPPORT_PSCI
177 select SUNXI_GEN_SUN6I
179 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
182 bool "sun7i (Allwinner A20)"
184 select CPU_V7_HAS_NONSEC
185 select CPU_V7_HAS_VIRT
186 select ARCH_SUPPORT_PSCI
189 select SUNXI_GEN_SUN4I
191 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
193 config MACH_SUN8I_A23
194 bool "sun8i (Allwinner A23)"
196 select CPU_V7_HAS_NONSEC
197 select CPU_V7_HAS_VIRT
198 select ARCH_SUPPORT_PSCI
199 select DRAM_SUN8I_A23
201 select SUNXI_GEN_SUN6I
203 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
204 imply CONS_INDEX_5 if !DM_SERIAL
206 config MACH_SUN8I_A33
207 bool "sun8i (Allwinner A33)"
209 select CPU_V7_HAS_NONSEC
210 select CPU_V7_HAS_VIRT
211 select ARCH_SUPPORT_PSCI
212 select DRAM_SUN8I_A33
214 select SUNXI_GEN_SUN6I
216 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
217 imply CONS_INDEX_5 if !DM_SERIAL
219 config MACH_SUN8I_A83T
220 bool "sun8i (Allwinner A83T)"
222 select DRAM_SUN8I_A83T
224 select SUNXI_GEN_SUN6I
225 select MMC_SUNXI_HAS_NEW_MODE
229 bool "sun8i (Allwinner H3)"
231 select CPU_V7_HAS_NONSEC
232 select CPU_V7_HAS_VIRT
233 select ARCH_SUPPORT_PSCI
234 select MACH_SUNXI_H3_H5
235 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
237 config MACH_SUN8I_R40
238 bool "sun8i (Allwinner R40)"
240 select CPU_V7_HAS_NONSEC
241 select CPU_V7_HAS_VIRT
242 select ARCH_SUPPORT_PSCI
243 select SUNXI_GEN_SUN6I
246 select SUNXI_DRAM_DW_32BIT
248 config MACH_SUN8I_V3S
249 bool "sun8i (Allwinner V3s)"
251 select CPU_V7_HAS_NONSEC
252 select CPU_V7_HAS_VIRT
253 select ARCH_SUPPORT_PSCI
254 select SUNXI_GEN_SUN6I
256 select SUNXI_DRAM_DW_16BIT
258 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
261 bool "sun9i (Allwinner A80)"
265 select SUNXI_GEN_SUN6I
270 bool "sun50i (Allwinner A64)"
275 select SUNXI_GEN_SUN6I
278 select SUNXI_DRAM_DW_32BIT
281 select SUNXI_A64_TIMER_ERRATUM
283 config MACH_SUN50I_H5
284 bool "sun50i (Allwinner H5)"
286 select MACH_SUNXI_H3_H5
292 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
297 default y if MACH_SUN8I_A23
298 default y if MACH_SUN8I_A33
299 default y if MACH_SUN8I_A83T
300 default y if MACH_SUNXI_H3_H5
301 default y if MACH_SUN8I_R40
302 default y if MACH_SUN8I_V3S
304 config RESERVE_ALLWINNER_BOOT0_HEADER
305 bool "reserve space for Allwinner boot0 header"
306 select ENABLE_ARM_SOC_BOOT0_HOOK
308 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
309 filled with magic values post build. The Allwinner provided boot0
310 blob relies on this information to load and execute U-Boot.
311 Only needed on 64-bit Allwinner boards so far when using boot0.
313 config ARM_BOOT_HOOK_RMR
317 select ENABLE_ARM_SOC_BOOT0_HOOK
319 Insert some ARM32 code at the very beginning of the U-Boot binary
320 which uses an RMR register write to bring the core into AArch64 mode.
321 The very first instruction acts as a switch, since it's carefully
322 chosen to be a NOP in one mode and a branch in the other, so the
323 code would only be executed if not already in AArch64.
324 This allows both the SPL and the U-Boot proper to be entered in
325 either mode and switch to AArch64 if needed.
328 config SUNXI_DRAM_DDR3
331 config SUNXI_DRAM_DDR2
334 config SUNXI_DRAM_LPDDR3
338 prompt "DRAM Type and Timing"
339 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
340 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
342 config SUNXI_DRAM_DDR3_1333
344 select SUNXI_DRAM_DDR3
345 depends on !MACH_SUN8I_V3S
347 This option is the original only supported memory type, which suits
348 many H3/H5/A64 boards available now.
350 config SUNXI_DRAM_LPDDR3_STOCK
351 bool "LPDDR3 with Allwinner stock configuration"
352 select SUNXI_DRAM_LPDDR3
354 This option is the LPDDR3 timing used by the stock boot0 by
357 config SUNXI_DRAM_DDR2_V3S
358 bool "DDR2 found in V3s chip"
359 select SUNXI_DRAM_DDR2
360 depends on MACH_SUN8I_V3S
362 This option is only for the DDR2 memory chip which is co-packaged in
369 int "sunxi dram type"
370 depends on MACH_SUN8I_A83T
373 Set the dram type, 3: DDR3, 7: LPDDR3
376 int "sunxi dram clock speed"
377 default 792 if MACH_SUN9I
378 default 648 if MACH_SUN8I_R40
379 default 312 if MACH_SUN6I || MACH_SUN8I
380 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
382 default 672 if MACH_SUN50I
384 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
385 must be a multiple of 24. For the sun9i (A80), the tested values
386 (for DDR3-1600) are 312 to 792.
388 if MACH_SUN5I || MACH_SUN7I
390 int "sunxi mbus clock speed"
393 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
398 int "sunxi dram zq value"
399 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
400 default 127 if MACH_SUN7I
401 default 14779 if MACH_SUN8I_V3S
402 default 3881979 if MACH_SUN8I_R40
403 default 4145117 if MACH_SUN9I
404 default 3881915 if MACH_SUN50I
406 Set the dram zq value.
409 bool "sunxi dram odt enable"
410 default n if !MACH_SUN8I_A23
411 default y if MACH_SUN8I_A23
412 default y if MACH_SUN8I_R40
413 default y if MACH_SUN50I
415 Select this to enable dram odt (on die termination).
417 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
419 int "sunxi dram emr1 value"
420 default 0 if MACH_SUN4I
421 default 4 if MACH_SUN5I || MACH_SUN7I
423 Set the dram controller emr1 value.
426 hex "sunxi dram tpr3 value"
429 Set the dram controller tpr3 parameter. This parameter configures
430 the delay on the command lane and also phase shifts, which are
431 applied for sampling incoming read data. The default value 0
432 means that no phase/delay adjustments are necessary. Properly
433 configuring this parameter increases reliability at high DRAM
436 config DRAM_DQS_GATING_DELAY
437 hex "sunxi dram dqs_gating_delay value"
440 Set the dram controller dqs_gating_delay parmeter. Each byte
441 encodes the DQS gating delay for each byte lane. The delay
442 granularity is 1/4 cycle. For example, the value 0x05060606
443 means that the delay is 5 quarter-cycles for one lane (1.25
444 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
445 The default value 0 means autodetection. The results of hardware
446 autodetection are not very reliable and depend on the chip
447 temperature (sometimes producing different results on cold start
448 and warm reboot). But the accuracy of hardware autodetection
449 is usually good enough, unless running at really high DRAM
450 clocks speeds (up to 600MHz). If unsure, keep as 0.
453 prompt "sunxi dram timings"
454 default DRAM_TIMINGS_VENDOR_MAGIC
456 Select the timings of the DDR3 chips.
458 config DRAM_TIMINGS_VENDOR_MAGIC
459 bool "Magic vendor timings from Android"
461 The same DRAM timings as in the Allwinner boot0 bootloader.
463 config DRAM_TIMINGS_DDR3_1066F_1333H
464 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
466 Use the timings of the standard JEDEC DDR3-1066F speed bin for
467 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
468 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
469 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
470 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
471 that down binning to DDR3-1066F is supported (because DDR3-1066F
472 uses a bit faster timings than DDR3-1333H).
474 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
475 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
477 Use the timings of the slowest possible JEDEC speed bin for the
478 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
479 DDR3-800E, DDR3-1066G or DDR3-1333J.
486 config DRAM_ODT_CORRECTION
487 int "sunxi dram odt correction value"
490 Set the dram odt correction value (range -255 - 255). In allwinner
491 fex files, this option is found in bits 8-15 of the u32 odt_en variable
492 in the [dram] section. When bit 31 of the odt_en variable is set
493 then the correction is negative. Usually the value for this is 0.
497 default 1008000000 if MACH_SUN4I
498 default 1008000000 if MACH_SUN5I
499 default 1008000000 if MACH_SUN6I
500 default 912000000 if MACH_SUN7I
501 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
502 default 1008000000 if MACH_SUN8I
503 default 1008000000 if MACH_SUN9I
505 config SYS_CONFIG_NAME
506 default "sun4i" if MACH_SUN4I
507 default "sun5i" if MACH_SUN5I
508 default "sun6i" if MACH_SUN6I
509 default "sun7i" if MACH_SUN7I
510 default "sun8i" if MACH_SUN8I
511 default "sun9i" if MACH_SUN9I
512 default "sun50i" if MACH_SUN50I
521 bool "UART0 on MicroSD breakout board"
524 Repurpose the SD card slot for getting access to the UART0 serial
525 console. Primarily useful only for low level u-boot debugging on
526 tablets, where normal UART0 is difficult to access and requires
527 device disassembly and/or soldering. As the SD card can't be used
528 at the same time, the system can be only booted in the FEL mode.
529 Only enable this if you really know what you are doing.
531 config OLD_SUNXI_KERNEL_COMPAT
532 bool "Enable workarounds for booting old kernels"
535 Set this to enable various workarounds for old kernels, this results in
536 sub-optimal settings for newer kernels, only enable if needed.
539 string "MAC power pin"
542 Set the pin used to power the MAC. This takes a string in the format
543 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
546 string "Card detect pin for mmc0"
547 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
550 Set the card detect pin for mmc0, leave empty to not use cd. This
551 takes a string in the format understood by sunxi_name_to_gpio, e.g.
552 PH1 for pin 1 of port H.
555 string "Card detect pin for mmc1"
558 See MMC0_CD_PIN help text.
561 string "Card detect pin for mmc2"
564 See MMC0_CD_PIN help text.
567 string "Card detect pin for mmc3"
570 See MMC0_CD_PIN help text.
573 string "Pins for mmc1"
576 Set the pins used for mmc1, when applicable. This takes a string in the
577 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
580 string "Pins for mmc2"
583 See MMC1_PINS help text.
586 string "Pins for mmc3"
589 See MMC1_PINS help text.
591 config MMC_SUNXI_SLOT_EXTRA
592 int "mmc extra slot number"
595 sunxi builds always enable mmc0, some boards also have a second sdcard
596 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
599 config INITIAL_USB_SCAN_DELAY
600 int "delay initial usb scan by x ms to allow builtin devices to init"
603 Some boards have on board usb devices which need longer than the
604 USB spec's 1 second to connect from board powerup. Set this config
605 option to a non 0 value to add an extra delay before the first usb
609 string "Vbus enable pin for usb0 (otg)"
612 Set the Vbus enable pin for usb0 (otg). This takes a string in the
613 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
616 string "Vbus detect pin for usb0 (otg)"
619 Set the Vbus detect pin for usb0 (otg). This takes a string in the
620 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
623 string "ID detect pin for usb0 (otg)"
626 Set the ID detect pin for usb0 (otg). This takes a string in the
627 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
630 string "Vbus enable pin for usb1 (ehci0)"
631 default "PH6" if MACH_SUN4I || MACH_SUN7I
632 default "PH27" if MACH_SUN6I
634 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
635 a string in the format understood by sunxi_name_to_gpio, e.g.
636 PH1 for pin 1 of port H.
639 string "Vbus enable pin for usb2 (ehci1)"
640 default "PH3" if MACH_SUN4I || MACH_SUN7I
641 default "PH24" if MACH_SUN6I
643 See USB1_VBUS_PIN help text.
646 string "Vbus enable pin for usb3 (ehci2)"
649 See USB1_VBUS_PIN help text.
652 bool "Enable I2C/TWI controller 0"
653 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
654 default n if MACH_SUN6I || MACH_SUN8I
657 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
658 its clock and setting up the bus. This is especially useful on devices
659 with slaves connected to the bus or with pins exposed through e.g. an
660 expansion port/header.
663 bool "Enable I2C/TWI controller 1"
667 See I2C0_ENABLE help text.
670 bool "Enable I2C/TWI controller 2"
674 See I2C0_ENABLE help text.
676 if MACH_SUN6I || MACH_SUN7I
678 bool "Enable I2C/TWI controller 3"
682 See I2C0_ENABLE help text.
687 bool "Enable the PRCM I2C/TWI controller"
688 # This is used for the pmic on H3
689 default y if SY8106A_POWER
692 Set this to y to enable the I2C controller which is part of the PRCM.
697 bool "Enable I2C/TWI controller 4"
701 See I2C0_ENABLE help text.
705 bool "Enable support for gpio-s on axp PMICs"
708 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
711 bool "Enable graphical uboot console on HDMI, LCD or VGA"
712 depends on !MACH_SUN8I_A83T
713 depends on !MACH_SUNXI_H3_H5
714 depends on !MACH_SUN8I_R40
715 depends on !MACH_SUN8I_V3S
716 depends on !MACH_SUN9I
717 depends on !MACH_SUN50I
719 imply VIDEO_DT_SIMPLEFB
722 Say Y here to add support for using a cfb console on the HDMI, LCD
723 or VGA output found on most sunxi devices. See doc/README.video for
724 info on how to select the video output and mode.
727 bool "HDMI output support"
728 depends on VIDEO_SUNXI && !MACH_SUN8I
731 Say Y here to add support for outputting video over HDMI.
734 bool "VGA output support"
735 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
738 Say Y here to add support for outputting video over VGA.
740 config VIDEO_VGA_VIA_LCD
741 bool "VGA via LCD controller support"
742 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
745 Say Y here to add support for external DACs connected to the parallel
746 LCD interface driving a VGA connector, such as found on the
749 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
750 bool "Force sync active high for VGA via LCD controller support"
751 depends on VIDEO_VGA_VIA_LCD
754 Say Y here if you've a board which uses opendrain drivers for the vga
755 hsync and vsync signals. Opendrain drivers cannot generate steep enough
756 positive edges for a stable video output, so on boards with opendrain
757 drivers the sync signals must always be active high.
759 config VIDEO_VGA_EXTERNAL_DAC_EN
760 string "LCD panel power enable pin"
761 depends on VIDEO_VGA_VIA_LCD
764 Set the enable pin for the external VGA DAC. This takes a string in the
765 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
767 config VIDEO_COMPOSITE
768 bool "Composite video output support"
769 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
772 Say Y here to add support for outputting composite video.
774 config VIDEO_LCD_MODE
775 string "LCD panel timing details"
776 depends on VIDEO_SUNXI
779 LCD panel timing details string, leave empty if there is no LCD panel.
780 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
781 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
782 Also see: http://linux-sunxi.org/LCD
784 config VIDEO_LCD_DCLK_PHASE
785 int "LCD panel display clock phase"
786 depends on VIDEO_SUNXI || DM_VIDEO
789 Select LCD panel display clock phase shift, range 0-3.
791 config VIDEO_LCD_POWER
792 string "LCD panel power enable pin"
793 depends on VIDEO_SUNXI
796 Set the power enable pin for the LCD panel. This takes a string in the
797 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
799 config VIDEO_LCD_RESET
800 string "LCD panel reset pin"
801 depends on VIDEO_SUNXI
804 Set the reset pin for the LCD panel. This takes a string in the format
805 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
807 config VIDEO_LCD_BL_EN
808 string "LCD panel backlight enable pin"
809 depends on VIDEO_SUNXI
812 Set the backlight enable pin for the LCD panel. This takes a string in the
813 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
816 config VIDEO_LCD_BL_PWM
817 string "LCD panel backlight pwm pin"
818 depends on VIDEO_SUNXI
821 Set the backlight pwm pin for the LCD panel. This takes a string in the
822 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
824 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
825 bool "LCD panel backlight pwm is inverted"
826 depends on VIDEO_SUNXI
829 Set this if the backlight pwm output is active low.
831 config VIDEO_LCD_PANEL_I2C
832 bool "LCD panel needs to be configured via i2c"
833 depends on VIDEO_SUNXI
837 Say y here if the LCD panel needs to be configured via i2c. This
838 will add a bitbang i2c controller using gpios to talk to the LCD.
840 config VIDEO_LCD_PANEL_I2C_SDA
841 string "LCD panel i2c interface SDA pin"
842 depends on VIDEO_LCD_PANEL_I2C
845 Set the SDA pin for the LCD i2c interface. This takes a string in the
846 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
848 config VIDEO_LCD_PANEL_I2C_SCL
849 string "LCD panel i2c interface SCL pin"
850 depends on VIDEO_LCD_PANEL_I2C
853 Set the SCL pin for the LCD i2c interface. This takes a string in the
854 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
857 # Note only one of these may be selected at a time! But hidden choices are
858 # not supported by Kconfig
859 config VIDEO_LCD_IF_PARALLEL
862 config VIDEO_LCD_IF_LVDS
870 bool "Display Engine 2 video driver"
874 imply VIDEO_DT_SIMPLEFB
877 Say y here if you want to build DE2 video driver which is present on
878 newer SoCs. Currently only HDMI output is supported.
882 prompt "LCD panel support"
883 depends on VIDEO_SUNXI
885 Select which type of LCD panel to support.
887 config VIDEO_LCD_PANEL_PARALLEL
888 bool "Generic parallel interface LCD panel"
889 select VIDEO_LCD_IF_PARALLEL
891 config VIDEO_LCD_PANEL_LVDS
892 bool "Generic lvds interface LCD panel"
893 select VIDEO_LCD_IF_LVDS
895 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
896 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
897 select VIDEO_LCD_SSD2828
898 select VIDEO_LCD_IF_PARALLEL
900 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
902 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
903 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
904 select VIDEO_LCD_ANX9804
905 select VIDEO_LCD_IF_PARALLEL
906 select VIDEO_LCD_PANEL_I2C
908 Select this for eDP LCD panels with 4 lanes running at 1.62G,
909 connected via an ANX9804 bridge chip.
911 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
912 bool "Hitachi tx18d42vm LCD panel"
913 select VIDEO_LCD_HITACHI_TX18D42VM
914 select VIDEO_LCD_IF_LVDS
916 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
918 config VIDEO_LCD_TL059WV5C0
919 bool "tl059wv5c0 LCD panel"
920 select VIDEO_LCD_PANEL_I2C
921 select VIDEO_LCD_IF_PARALLEL
923 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
924 Aigo M60/M608/M606 tablets.
929 string "SATA power pin"
932 Set the pins used to power the SATA. This takes a string in the
933 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
937 int "GMAC Transmit Clock Delay Chain"
940 Set the GMAC Transmit Clock Delay Chain value.
942 config SPL_STACK_R_ADDR
943 default 0x4fe00000 if MACH_SUN4I
944 default 0x4fe00000 if MACH_SUN5I
945 default 0x4fe00000 if MACH_SUN6I
946 default 0x4fe00000 if MACH_SUN7I
947 default 0x4fe00000 if MACH_SUN8I
948 default 0x2fe00000 if MACH_SUN9I
949 default 0x4fe00000 if MACH_SUN50I
952 bool "Support for SPI Flash on Allwinner SoCs in SPL"
953 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
955 Enable support for SPI Flash. This option allows SPL to read from
956 sunxi SPI Flash. It uses the same method as the boot ROM, so does
957 not need any extra configuration.