arch/arm/mach-stm32mp/include/mach/stm32.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef _MACH_STM32_H_
   7 #define _MACH_STM32_H_
   8
   9 #ifndef __ASSEMBLY__
  10 #include <linux/bitops.h>
  11 #endif
  12
  13 /*
  14  * Peripheral memory map
  15  * only address used before device tree parsing
  16  */
  17 #define STM32_RCC_BASE                  0x50000000
  18 #define STM32_PWR_BASE                  0x50001000
  19 #define STM32_SYSCFG_BASE               0x50020000
  20 #ifdef CONFIG_STM32MP15x
  21 #define STM32_DBGMCU_BASE               0x50081000
  22 #endif
  23 #define STM32_FMC2_BASE                 0x58002000
  24 #define STM32_IWDG2_BASE                0x5A002000
  25 #define STM32_DDRCTRL_BASE              0x5A003000
  26 #define STM32_DDRPHYC_BASE              0x5A004000
  27 #define STM32_IWDG1_BASE                0x5C003000
  28 #define STM32_TZC_BASE                  0x5C006000
  29 #define STM32_ETZPC_BASE                0x5C007000
  30 #define STM32_STGEN_BASE                0x5C008000
  31 #define STM32_TAMP_BASE                 0x5C00A000
  32
  33 #ifdef CONFIG_STM32MP15x
  34 #define STM32_USART1_BASE               0x5C000000
  35 #define STM32_USART2_BASE               0x4000E000
  36 #endif
  37 #ifdef CONFIG_STM32MP13x
  38 #define STM32_USART1_BASE               0x4c000000
  39 #define STM32_USART2_BASE               0x4c001000
  40 #endif
  41 #define STM32_USART3_BASE               0x4000F000
  42 #define STM32_UART4_BASE                0x40010000
  43 #define STM32_UART5_BASE                0x40011000
  44 #define STM32_USART6_BASE               0x44003000
  45 #define STM32_UART7_BASE                0x40018000
  46 #define STM32_UART8_BASE                0x40019000
  47
  48 #define STM32_SDMMC1_BASE               0x58005000
  49 #define STM32_SDMMC2_BASE               0x58007000
  50 #define STM32_SDMMC3_BASE               0x48004000
  51
  52 #ifdef CONFIG_STM32MP15x
  53 #define STM32_SYSRAM_BASE               0x2FFC0000
  54 #define STM32_SYSRAM_SIZE               SZ_256K
  55 #endif
  56
  57 #define STM32_DDR_BASE                  0xC0000000
  58 #define STM32_DDR_SIZE                  SZ_1G
  59
  60 #ifndef __ASSEMBLY__
  61 /* enumerated used to identify the SYSCON driver instance */
  62 enum {
  63         STM32MP_SYSCON_UNKNOWN,
  64         STM32MP_SYSCON_SYSCFG,
  65 };
  66
  67 /*
  68  * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
  69  * - boot device = bit 8:4
  70  * - boot instance = bit 3:0
  71  */
  72 #define BOOT_TYPE_MASK          0xF0
  73 #define BOOT_TYPE_SHIFT         4
  74 #define BOOT_INSTANCE_MASK      0x0F
  75 #define BOOT_INSTANCE_SHIFT     0
  76
  77 enum boot_device {
  78         BOOT_FLASH_SD = 0x10,
  79         BOOT_FLASH_SD_1 = 0x11,
  80         BOOT_FLASH_SD_2 = 0x12,
  81         BOOT_FLASH_SD_3 = 0x13,
  82
  83         BOOT_FLASH_EMMC = 0x20,
  84         BOOT_FLASH_EMMC_1 = 0x21,
  85         BOOT_FLASH_EMMC_2 = 0x22,
  86         BOOT_FLASH_EMMC_3 = 0x23,
  87
  88         BOOT_FLASH_NAND = 0x30,
  89         BOOT_FLASH_NAND_FMC = 0x31,
  90
  91         BOOT_FLASH_NOR = 0x40,
  92         BOOT_FLASH_NOR_QSPI = 0x41,
  93
  94         BOOT_SERIAL_UART = 0x50,
  95         BOOT_SERIAL_UART_1 = 0x51,
  96         BOOT_SERIAL_UART_2 = 0x52,
  97         BOOT_SERIAL_UART_3 = 0x53,
  98         BOOT_SERIAL_UART_4 = 0x54,
  99         BOOT_SERIAL_UART_5 = 0x55,
 100         BOOT_SERIAL_UART_6 = 0x56,
 101         BOOT_SERIAL_UART_7 = 0x57,
 102         BOOT_SERIAL_UART_8 = 0x58,
 103
 104         BOOT_SERIAL_USB = 0x60,
 105         BOOT_SERIAL_USB_OTG = 0x62,
 106
 107         BOOT_FLASH_SPINAND = 0x70,
 108         BOOT_FLASH_SPINAND_1 = 0x71,
 109 };
 110
 111 /* TAMP registers */
 112 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
 113
 114 #ifdef CONFIG_STM32MP15x
 115 #define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
 116 #define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
 117 #define TAMP_FWU_BOOT_INFO_REG          TAMP_BACKUP_REGISTER(10)
 118 #define TAMP_COPRO_RSC_TBL_ADDRESS      TAMP_BACKUP_REGISTER(17)
 119 #define TAMP_COPRO_STATE                TAMP_BACKUP_REGISTER(18)
 120 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
 121 #define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
 122
 123 #define TAMP_FWU_BOOT_IDX_MASK          GENMASK(3, 0)
 124
 125 #define TAMP_FWU_BOOT_IDX_OFFSET        0
 126
 127 #define TAMP_COPRO_STATE_OFF            0
 128 #define TAMP_COPRO_STATE_INIT           1
 129 #define TAMP_COPRO_STATE_CRUN           2
 130 #define TAMP_COPRO_STATE_CSTOP          3
 131 #define TAMP_COPRO_STATE_STANDBY        4
 132 #define TAMP_COPRO_STATE_CRASH          5
 133 #endif
 134
 135 #ifdef CONFIG_STM32MP13x
 136 #define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(31)
 137 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(30)
 138 #endif
 139
 140 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
 141 #define TAMP_BOOT_MODE_SHIFT            8
 142 #define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
 143 #define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
 144 #define TAMP_BOOT_FORCED_MASK           GENMASK(7, 0)
 145
 146 enum forced_boot_mode {
 147         BOOT_NORMAL = 0x00,
 148         BOOT_FASTBOOT = 0x01,
 149         BOOT_RECOVERY = 0x02,
 150         BOOT_STM32PROG = 0x03,
 151         BOOT_UMS_MMC0 = 0x10,
 152         BOOT_UMS_MMC1 = 0x11,
 153         BOOT_UMS_MMC2 = 0x12,
 154 };
 155
 156 /* offset used for BSEC driver: misc_read and misc_write */
 157 #define STM32_BSEC_SHADOW_OFFSET        0x0
 158 #define STM32_BSEC_SHADOW(id)           (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
 159 #define STM32_BSEC_OTP_OFFSET           0x80000000
 160 #define STM32_BSEC_OTP(id)              (STM32_BSEC_OTP_OFFSET + (id) * 4)
 161 #define STM32_BSEC_LOCK_OFFSET          0xC0000000
 162 #define STM32_BSEC_LOCK(id)             (STM32_BSEC_LOCK_OFFSET + (id) * 4)
 163
 164 /* BSEC OTP index */
 165 #ifdef CONFIG_STM32MP15x
 166 #define BSEC_OTP_RPN    1
 167 #define BSEC_OTP_SERIAL 13
 168 #define BSEC_OTP_PKG    16
 169 #define BSEC_OTP_MAC    57
 170 #define BSEC_OTP_BOARD  59
 171 #endif
 172 #ifdef CONFIG_STM32MP13x
 173 #define BSEC_OTP_RPN    1
 174 #define BSEC_OTP_SERIAL 13
 175 #define BSEC_OTP_MAC    57
 176 #define BSEC_OTP_BOARD  60
 177 #endif
 178
 179 #endif /* __ASSEMBLY__ */
 180 #endif /* _MACH_STM32_H_ */