arch/arm/mach-stm32mp/include/mach/stm32.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef _MACH_STM32_H_
   7 #define _MACH_STM32_H_
   8
   9 /*
  10  * Peripheral memory map
  11  * only address used before device tree parsing
  12  */
  13 #define STM32_RCC_BASE                  0x50000000
  14 #define STM32_PWR_BASE                  0x50001000
  15 #define STM32_DBGMCU_BASE               0x50081000
  16 #define STM32_BSEC_BASE                 0x5C005000
  17 #define STM32_TZC_BASE                  0x5C006000
  18 #define STM32_ETZPC_BASE                0x5C007000
  19 #define STM32_TAMP_BASE                 0x5C00A000
  20
  21 #ifdef CONFIG_DEBUG_UART_BASE
  22 /* hardcoded value can be only used for DEBUG UART */
  23 #define STM32_USART1_BASE               0x5C000000
  24 #define STM32_USART2_BASE               0x4000E000
  25 #define STM32_USART3_BASE               0x4000F000
  26 #define STM32_UART4_BASE                0x40010000
  27 #define STM32_UART5_BASE                0x40011000
  28 #define STM32_USART6_BASE               0x44003000
  29 #define STM32_UART7_BASE                0x40018000
  30 #define STM32_UART8_BASE                0x40019000
  31 #endif
  32
  33 #define STM32_SYSRAM_BASE               0x2FFC0000
  34 #define STM32_SYSRAM_SIZE               SZ_256K
  35
  36 #define STM32_DDR_BASE                  0xC0000000
  37 #define STM32_DDR_SIZE                  SZ_1G
  38
  39 #ifndef __ASSEMBLY__
  40 /* enumerated used to identify the SYSCON driver instance */
  41 enum {
  42         STM32MP_SYSCON_UNKNOWN,
  43         STM32MP_SYSCON_STGEN,
  44         STM32MP_SYSCON_PWR,
  45 };
  46
  47 /*
  48  * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
  49  * - boot device = bit 8:4
  50  * - boot instance = bit 3:0
  51  */
  52 #define BOOT_TYPE_MASK          0xF0
  53 #define BOOT_TYPE_SHIFT         4
  54 #define BOOT_INSTANCE_MASK      0x0F
  55 #define BOOT_INSTANCE_SHIFT     0
  56
  57 enum boot_device {
  58         BOOT_FLASH_SD = 0x10,
  59         BOOT_FLASH_SD_1 = 0x11,
  60         BOOT_FLASH_SD_2 = 0x12,
  61         BOOT_FLASH_SD_3 = 0x13,
  62
  63         BOOT_FLASH_EMMC = 0x20,
  64         BOOT_FLASH_EMMC_1 = 0x21,
  65         BOOT_FLASH_EMMC_2 = 0x22,
  66         BOOT_FLASH_EMMC_3 = 0x23,
  67
  68         BOOT_FLASH_NAND = 0x30,
  69         BOOT_FLASH_NAND_FMC = 0x31,
  70
  71         BOOT_FLASH_NOR = 0x40,
  72         BOOT_FLASH_NOR_QSPI = 0x41,
  73
  74         BOOT_SERIAL_UART = 0x50,
  75         BOOT_SERIAL_UART_1 = 0x51,
  76         BOOT_SERIAL_UART_2 = 0x52,
  77         BOOT_SERIAL_UART_3 = 0x53,
  78         BOOT_SERIAL_UART_4 = 0x54,
  79         BOOT_SERIAL_UART_5 = 0x55,
  80         BOOT_SERIAL_UART_6 = 0x56,
  81         BOOT_SERIAL_UART_7 = 0x57,
  82         BOOT_SERIAL_UART_8 = 0x58,
  83
  84         BOOT_SERIAL_USB = 0x60,
  85         BOOT_SERIAL_USB_OTG = 0x62,
  86 };
  87
  88 /* TAMP registers */
  89 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
  90 #define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
  91 #define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
  92 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
  93
  94 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
  95 #define TAMP_BOOT_MODE_SHIFT            8
  96 #define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
  97 #define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
  98
  99 /* offset used for BSEC driver: misc_read and misc_write */
 100 #define STM32_BSEC_SHADOW_OFFSET        0x0
 101 #define STM32_BSEC_OTP_OFFSET           0x80000000
 102
 103 #endif /* __ASSEMBLY__*/
 104 #endif /* _MACH_STM32_H_ */