arch/arm/mach-stm32mp/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY LOGC_ARCH
   7
   8 #include <common.h>
   9 #include <fdtdec.h>
  10 #include <fdt_support.h>
  11 #include <log.h>
  12 #include <tee.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  15 #include <linux/io.h>
  16
  17 #define ETZPC_DECPROT(n)        (STM32_ETZPC_BASE + 0x10 + 4 * (n))
  18 #define ETZPC_DECPROT_NB        6
  19
  20 #define DECPROT_MASK            0x03
  21 #define NB_PROT_PER_REG         0x10
  22 #define DECPROT_NB_BITS         2
  23
  24 #define DECPROT_SECURED         0x00
  25 #define DECPROT_WRITE_SECURE    0x01
  26 #define DECPROT_MCU_ISOLATION   0x02
  27 #define DECPROT_NON_SECURED     0x03
  28
  29 #define ETZPC_RESERVED          0xffffffff
  30
  31 #define STM32MP13_FDCAN_BASE    0x4400F000
  32 #define STM32MP13_ADC1_BASE     0x48003000
  33 #define STM32MP13_TSC_BASE      0x5000B000
  34 #define STM32MP13_CRYP_BASE     0x54002000
  35 #define STM32MP13_ETH2_BASE     0x5800E000
  36 #define STM32MP13_DCMIPP_BASE   0x5A000000
  37 #define STM32MP13_LTDC_BASE     0x5A010000
  38
  39 #define STM32MP15_FDCAN_BASE    0x4400e000
  40 #define STM32MP15_CRYP2_BASE    0x4c005000
  41 #define STM32MP15_CRYP1_BASE    0x54001000
  42 #define STM32MP15_GPU_BASE      0x59000000
  43 #define STM32MP15_DSI_BASE      0x5a000000
  44
  45 static const u32 stm32mp13_ip_addr[] = {
  46         0x50025000,             /* 0 VREFBUF APB3 */
  47         0x50021000,             /* 1 LPTIM2 APB3 */
  48         0x50022000,             /* 2 LPTIM3 APB3 */
  49         STM32MP13_LTDC_BASE,    /* 3 LTDC APB4 */
  50         STM32MP13_DCMIPP_BASE,  /* 4 DCMIPP APB4 */
  51         0x5A006000,             /* 5 USBPHYCTRL APB4 */
  52         0x5A003000,             /* 6 DDRCTRLPHY APB4 */
  53         ETZPC_RESERVED,         /* 7 Reserved*/
  54         ETZPC_RESERVED,         /* 8 Reserved*/
  55         ETZPC_RESERVED,         /* 9 Reserved*/
  56         0x5C006000,             /* 10 TZC APB5 */
  57         0x58001000,             /* 11 MCE APB5 */
  58         0x5C000000,             /* 12 IWDG1 APB5 */
  59         0x5C008000,             /* 13 STGENC APB5 */
  60         ETZPC_RESERVED,         /* 14 Reserved*/
  61         ETZPC_RESERVED,         /* 15 Reserved*/
  62         0x4C000000,             /* 16 USART1 APB6 */
  63         0x4C001000,             /* 17 USART2 APB6 */
  64         0x4C002000,             /* 18 SPI4 APB6 */
  65         0x4C003000,             /* 19 SPI5 APB6 */
  66         0x4C004000,             /* 20 I2C3 APB6 */
  67         0x4C005000,             /* 21 I2C4 APB6 */
  68         0x4C006000,             /* 22 I2C5 APB6 */
  69         0x4C007000,             /* 23 TIM12 APB6 */
  70         0x4C008000,             /* 24 TIM13 APB6 */
  71         0x4C009000,             /* 25 TIM14 APB6 */
  72         0x4C00A000,             /* 26 TIM15 APB6 */
  73         0x4C00B000,             /* 27 TIM16 APB6 */
  74         0x4C00C000,             /* 28 TIM17 APB6 */
  75         ETZPC_RESERVED,         /* 29 Reserved*/
  76         ETZPC_RESERVED,         /* 30 Reserved*/
  77         ETZPC_RESERVED,         /* 31 Reserved*/
  78         STM32MP13_ADC1_BASE,    /* 32 ADC1 AHB2 */
  79         0x48004000,             /* 33 ADC2 AHB2 */
  80         0x49000000,             /* 34 OTG AHB2 */
  81         ETZPC_RESERVED,         /* 35 Reserved*/
  82         ETZPC_RESERVED,         /* 36 Reserved*/
  83         STM32MP13_TSC_BASE,     /* 37 TSC AHB4 */
  84         ETZPC_RESERVED,         /* 38 Reserved*/
  85         ETZPC_RESERVED,         /* 39 Reserved*/
  86         0x54004000,             /* 40 RNG AHB5 */
  87         0x54003000,             /* 41 HASH AHB5 */
  88         STM32MP13_CRYP_BASE,    /* 42 CRYPT AHB5 */
  89         0x54005000,             /* 43 SAES AHB5 */
  90         0x54006000,             /* 44 PKA AHB5 */
  91         0x54000000,             /* 45 BKPSRAM AHB5 */
  92         ETZPC_RESERVED,         /* 46 Reserved*/
  93         ETZPC_RESERVED,         /* 47 Reserved*/
  94         0x5800A000,             /* 48 ETH1 AHB6 */
  95         STM32MP13_ETH2_BASE,    /* 49 ETH2 AHB6 */
  96         0x58005000,             /* 50 SDMMC1 AHB6 */
  97         0x58007000,             /* 51 SDMMC2 AHB6 */
  98         ETZPC_RESERVED,         /* 52 Reserved*/
  99         ETZPC_RESERVED,         /* 53 Reserved*/
 100         0x58002000,             /* 54 FMC AHB6 */
 101         0x58003000,             /* 55 QSPI AHB6 */
 102         ETZPC_RESERVED,         /* 56 Reserved*/
 103         ETZPC_RESERVED,         /* 57 Reserved*/
 104         ETZPC_RESERVED,         /* 58 Reserved*/
 105         ETZPC_RESERVED,         /* 59 Reserved*/
 106         0x30000000,             /* 60 SRAM1 MLAHB */
 107         0x30004000,             /* 61 SRAM2 MLAHB */
 108         0x30006000,             /* 62 SRAM3 MLAHB */
 109         ETZPC_RESERVED,         /* 63 Reserved*/
 110         ETZPC_RESERVED,         /* 64 Reserved*/
 111         ETZPC_RESERVED,         /* 65 Reserved*/
 112         ETZPC_RESERVED,         /* 66 Reserved*/
 113         ETZPC_RESERVED,         /* 67 Reserved*/
 114         ETZPC_RESERVED,         /* 68 Reserved*/
 115         ETZPC_RESERVED,         /* 69 Reserved*/
 116         ETZPC_RESERVED,         /* 70 Reserved*/
 117         ETZPC_RESERVED,         /* 71 Reserved*/
 118         ETZPC_RESERVED,         /* 72 Reserved*/
 119         ETZPC_RESERVED,         /* 73 Reserved*/
 120         ETZPC_RESERVED,         /* 74 Reserved*/
 121         ETZPC_RESERVED,         /* 75 Reserved*/
 122         ETZPC_RESERVED,         /* 76 Reserved*/
 123         ETZPC_RESERVED,         /* 77 Reserved*/
 124         ETZPC_RESERVED,         /* 78 Reserved*/
 125         ETZPC_RESERVED,         /* 79 Reserved*/
 126         ETZPC_RESERVED,         /* 80 Reserved*/
 127         ETZPC_RESERVED,         /* 81 Reserved*/
 128         ETZPC_RESERVED,         /* 82 Reserved*/
 129         ETZPC_RESERVED,         /* 83 Reserved*/
 130         ETZPC_RESERVED,         /* 84 Reserved*/
 131         ETZPC_RESERVED,         /* 85 Reserved*/
 132         ETZPC_RESERVED,         /* 86 Reserved*/
 133         ETZPC_RESERVED,         /* 87 Reserved*/
 134         ETZPC_RESERVED,         /* 88 Reserved*/
 135         ETZPC_RESERVED,         /* 89 Reserved*/
 136         ETZPC_RESERVED,         /* 90 Reserved*/
 137         ETZPC_RESERVED,         /* 91 Reserved*/
 138         ETZPC_RESERVED,         /* 92 Reserved*/
 139         ETZPC_RESERVED,         /* 93 Reserved*/
 140         ETZPC_RESERVED,         /* 94 Reserved*/
 141         ETZPC_RESERVED,         /* 95 Reserved*/
 142 };
 143
 144 static const u32 stm32mp15_ip_addr[] = {
 145         0x5c008000,     /* 00 stgenc */
 146         0x54000000,     /* 01 bkpsram */
 147         0x5c003000,     /* 02 iwdg1 */
 148         0x5c000000,     /* 03 usart1 */
 149         0x5c001000,     /* 04 spi6 */
 150         0x5c002000,     /* 05 i2c4 */
 151         ETZPC_RESERVED, /* 06 reserved */
 152         0x54003000,     /* 07 rng1 */
 153         0x54002000,     /* 08 hash1 */
 154         STM32MP15_CRYP1_BASE,   /* 09 cryp1 */
 155         0x5a003000,     /* 0A ddrctrl */
 156         0x5a004000,     /* 0B ddrphyc */
 157         0x5c009000,     /* 0C i2c6 */
 158         ETZPC_RESERVED, /* 0D reserved */
 159         ETZPC_RESERVED, /* 0E reserved */
 160         ETZPC_RESERVED, /* 0F reserved */
 161         0x40000000,     /* 10 tim2 */
 162         0x40001000,     /* 11 tim3 */
 163         0x40002000,     /* 12 tim4 */
 164         0x40003000,     /* 13 tim5 */
 165         0x40004000,     /* 14 tim6 */
 166         0x40005000,     /* 15 tim7 */
 167         0x40006000,     /* 16 tim12 */
 168         0x40007000,     /* 17 tim13 */
 169         0x40008000,     /* 18 tim14 */
 170         0x40009000,     /* 19 lptim1 */
 171         0x4000a000,     /* 1A wwdg1 */
 172         0x4000b000,     /* 1B spi2 */
 173         0x4000c000,     /* 1C spi3 */
 174         0x4000d000,     /* 1D spdifrx */
 175         0x4000e000,     /* 1E usart2 */
 176         0x4000f000,     /* 1F usart3 */
 177         0x40010000,     /* 20 uart4 */
 178         0x40011000,     /* 21 uart5 */
 179         0x40012000,     /* 22 i2c1 */
 180         0x40013000,     /* 23 i2c2 */
 181         0x40014000,     /* 24 i2c3 */
 182         0x40015000,     /* 25 i2c5 */
 183         0x40016000,     /* 26 cec */
 184         0x40017000,     /* 27 dac */
 185         0x40018000,     /* 28 uart7 */
 186         0x40019000,     /* 29 uart8 */
 187         ETZPC_RESERVED, /* 2A reserved */
 188         ETZPC_RESERVED, /* 2B reserved */
 189         0x4001c000,     /* 2C mdios */
 190         ETZPC_RESERVED, /* 2D reserved */
 191         ETZPC_RESERVED, /* 2E reserved */
 192         ETZPC_RESERVED, /* 2F reserved */
 193         0x44000000,     /* 30 tim1 */
 194         0x44001000,     /* 31 tim8 */
 195         ETZPC_RESERVED, /* 32 reserved */
 196         0x44003000,     /* 33 usart6 */
 197         0x44004000,     /* 34 spi1 */
 198         0x44005000,     /* 35 spi4 */
 199         0x44006000,     /* 36 tim15 */
 200         0x44007000,     /* 37 tim16 */
 201         0x44008000,     /* 38 tim17 */
 202         0x44009000,     /* 39 spi5 */
 203         0x4400a000,     /* 3A sai1 */
 204         0x4400b000,     /* 3B sai2 */
 205         0x4400c000,     /* 3C sai3 */
 206         0x4400d000,     /* 3D dfsdm */
 207         STM32MP15_FDCAN_BASE,   /* 3E tt_fdcan */
 208         ETZPC_RESERVED, /* 3F reserved */
 209         0x50021000,     /* 40 lptim2 */
 210         0x50022000,     /* 41 lptim3 */
 211         0x50023000,     /* 42 lptim4 */
 212         0x50024000,     /* 43 lptim5 */
 213         0x50027000,     /* 44 sai4 */
 214         0x50025000,     /* 45 vrefbuf */
 215         0x4c006000,     /* 46 dcmi */
 216         0x4c004000,     /* 47 crc2 */
 217         0x48003000,     /* 48 adc */
 218         0x4c002000,     /* 49 hash2 */
 219         0x4c003000,     /* 4A rng2 */
 220         STM32MP15_CRYP2_BASE,   /* 4B cryp2 */
 221         ETZPC_RESERVED, /* 4C reserved */
 222         ETZPC_RESERVED, /* 4D reserved */
 223         ETZPC_RESERVED, /* 4E reserved */
 224         ETZPC_RESERVED, /* 4F reserved */
 225         ETZPC_RESERVED, /* 50 sram1 */
 226         ETZPC_RESERVED, /* 51 sram2 */
 227         ETZPC_RESERVED, /* 52 sram3 */
 228         ETZPC_RESERVED, /* 53 sram4 */
 229         ETZPC_RESERVED, /* 54 retram */
 230         0x49000000,     /* 55 otg */
 231         0x48004000,     /* 56 sdmmc3 */
 232         0x48005000,     /* 57 dlybsd3 */
 233         0x48000000,     /* 58 dma1 */
 234         0x48001000,     /* 59 dma2 */
 235         0x48002000,     /* 5A dmamux */
 236         0x58002000,     /* 5B fmc */
 237         0x58003000,     /* 5C qspi */
 238         0x58004000,     /* 5D dlybq */
 239         0x5800a000,     /* 5E eth */
 240         ETZPC_RESERVED, /* 5F reserved */
 241 };
 242
 243 /* fdt helper */
 244 static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
 245 {
 246         int node;
 247         fdt_addr_t regs;
 248
 249         for (node = fdt_first_subnode(fdt, offset);
 250              node >= 0;
 251              node = fdt_next_subnode(fdt, node)) {
 252                 regs = fdtdec_get_addr(fdt, node, "reg");
 253                 if (addr == regs) {
 254                         if (fdtdec_get_is_enabled(fdt, node)) {
 255                                 fdt_status_disabled(fdt, node);
 256
 257                                 return true;
 258                         }
 259                         return false;
 260                 }
 261         }
 262
 263         return false;
 264 }
 265
 266 static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
 267 {
 268         const u32 *array;
 269         int array_size, i;
 270         int offset, shift;
 271         u32 addr, status, decprot[ETZPC_DECPROT_NB];
 272
 273         if (IS_ENABLED(CONFIG_STM32MP13x)) {
 274                 array = stm32mp13_ip_addr;
 275                 array_size = ARRAY_SIZE(stm32mp13_ip_addr);
 276         }
 277
 278         if (IS_ENABLED(CONFIG_STM32MP15x)) {
 279                 array = stm32mp15_ip_addr;
 280                 array_size = ARRAY_SIZE(stm32mp15_ip_addr);
 281         }
 282
 283         for (i = 0; i < ETZPC_DECPROT_NB; i++)
 284                 decprot[i] = readl(ETZPC_DECPROT(i));
 285
 286         for (i = 0; i < array_size; i++) {
 287                 offset = i / NB_PROT_PER_REG;
 288                 shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
 289                 status = (decprot[offset] >> shift) & DECPROT_MASK;
 290                 addr = array[i];
 291
 292                 log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
 293
 294                 if (addr == ETZPC_RESERVED ||
 295                     status == DECPROT_NON_SECURED)
 296                         continue;
 297
 298                 if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
 299                         log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
 300                                    addr, i, status);
 301         }
 302
 303         return 0;
 304 }
 305
 306 /* deactivate all the cpu except core 0 */
 307 static void stm32_fdt_fixup_cpu(void *blob, char *name)
 308 {
 309         int off;
 310         u32 reg;
 311
 312         off = fdt_path_offset(blob, "/cpus");
 313         if (off < 0) {
 314                 log_warning("%s: couldn't find /cpus node\n", __func__);
 315                 return;
 316         }
 317
 318         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 319         while (off != -FDT_ERR_NOTFOUND) {
 320                 reg = fdtdec_get_addr(blob, off, "reg");
 321                 if (reg != 0) {
 322                         fdt_del_node(blob, off);
 323                         log_notice("FDT: cpu %d node remove for %s\n",
 324                                    reg, name);
 325                         /* after delete we can't trust the offsets anymore */
 326                         off = -1;
 327                 }
 328                 off = fdt_node_offset_by_prop_value(blob, off,
 329                                                     "device_type", "cpu", 4);
 330         }
 331 }
 332
 333 static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
 334                               const char *string, const char *name)
 335 {
 336         if (fdt_disable_subnode_by_address(fdt, offset, addr))
 337                 log_notice("FDT: %s@%08x node disabled for %s\n",
 338                            string, addr, name);
 339 }
 340
 341 static void stm32_fdt_disable_optee(void *blob)
 342 {
 343         int off, node;
 344
 345         /* Delete "optee" firmware node */
 346         off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
 347         if (off >= 0 && fdtdec_get_is_enabled(blob, off))
 348                 fdt_del_node(blob, off);
 349
 350         /* Delete "optee@..." reserved-memory node */
 351         off = fdt_path_offset(blob, "/reserved-memory/");
 352         if (off < 0)
 353                 return;
 354         for (node = fdt_first_subnode(blob, off);
 355              node >= 0;
 356              node = fdt_next_subnode(blob, node)) {
 357                 if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
 358                         continue;
 359
 360                 if (fdt_del_node(blob, node))
 361                         printf("Failed to remove optee reserved-memory node\n");
 362         }
 363 }
 364
 365 static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
 366 {
 367         switch (cpu) {
 368         case CPU_STM32MP131Fxx:
 369         case CPU_STM32MP131Dxx:
 370         case CPU_STM32MP131Cxx:
 371         case CPU_STM32MP131Axx:
 372                 stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
 373                 stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
 374                 fallthrough;
 375         case CPU_STM32MP133Fxx:
 376         case CPU_STM32MP133Dxx:
 377         case CPU_STM32MP133Cxx:
 378         case CPU_STM32MP133Axx:
 379                 stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
 380                 stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
 381                                   name);
 382                 stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
 383                 break;
 384         default:
 385                 break;
 386         }
 387
 388         switch (cpu) {
 389         case CPU_STM32MP135Dxx:
 390         case CPU_STM32MP135Axx:
 391         case CPU_STM32MP133Dxx:
 392         case CPU_STM32MP133Axx:
 393         case CPU_STM32MP131Dxx:
 394         case CPU_STM32MP131Axx:
 395                 stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
 396                 break;
 397         default:
 398                 break;
 399         }
 400 }
 401
 402 static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
 403 {
 404         u32 pkg;
 405
 406         switch (cpu) {
 407         case CPU_STM32MP151Fxx:
 408         case CPU_STM32MP151Dxx:
 409         case CPU_STM32MP151Cxx:
 410         case CPU_STM32MP151Axx:
 411                 stm32_fdt_fixup_cpu(blob, name);
 412                 /* after cpu delete we can't trust the soc offsets anymore */
 413                 soc = fdt_path_offset(blob, "/soc");
 414                 stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
 415                 fallthrough;
 416         case CPU_STM32MP153Fxx:
 417         case CPU_STM32MP153Dxx:
 418         case CPU_STM32MP153Cxx:
 419         case CPU_STM32MP153Axx:
 420                 stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
 421                 stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
 422                 break;
 423         default:
 424                 break;
 425         }
 426         switch (cpu) {
 427         case CPU_STM32MP157Dxx:
 428         case CPU_STM32MP157Axx:
 429         case CPU_STM32MP153Dxx:
 430         case CPU_STM32MP153Axx:
 431         case CPU_STM32MP151Dxx:
 432         case CPU_STM32MP151Axx:
 433                 stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
 434                                   name);
 435                 stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
 436                                   name);
 437                 break;
 438         default:
 439                 break;
 440         }
 441         switch (get_cpu_package()) {
 442         case STM32MP15_PKG_AA_LBGA448:
 443                 pkg = STM32MP_PKG_AA;
 444                 break;
 445         case STM32MP15_PKG_AB_LBGA354:
 446                 pkg = STM32MP_PKG_AB;
 447                 break;
 448         case STM32MP15_PKG_AC_TFBGA361:
 449                 pkg = STM32MP_PKG_AC;
 450                 break;
 451         case STM32MP15_PKG_AD_TFBGA257:
 452                 pkg = STM32MP_PKG_AD;
 453                 break;
 454         default:
 455                 pkg = 0;
 456                 break;
 457         }
 458         if (pkg) {
 459                 do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
 460                                        "st,package", pkg, false);
 461                 do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
 462                                        "st,package", pkg, false);
 463         }
 464 }
 465
 466 /*
 467  * This function is called right before the kernel is booted. "blob" is the
 468  * device tree that will be passed to the kernel.
 469  */
 470 int ft_system_setup(void *blob, struct bd_info *bd)
 471 {
 472         int ret = 0;
 473         int soc;
 474         u32 cpu;
 475         char name[SOC_NAME_SIZE];
 476
 477         soc = fdt_path_offset(blob, "/soc");
 478         /* when absent, nothing to do */
 479         if (soc == -FDT_ERR_NOTFOUND)
 480                 return 0;
 481         if (soc < 0)
 482                 return soc;
 483
 484         if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
 485                 ret = stm32_fdt_fixup_etzpc(blob, soc);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         /* MPUs Part Numbers and name*/
 491         cpu = get_cpu_type();
 492         get_soc_name(name);
 493
 494         if (IS_ENABLED(CONFIG_STM32MP13x))
 495                 stm32mp13_fdt_fixup(blob, soc, cpu, name);
 496
 497         if (IS_ENABLED(CONFIG_STM32MP15x)) {
 498                 stm32mp15_fdt_fixup(blob, soc, cpu, name);
 499
 500                 /*
 501                  * TEMP: remove OP-TEE nodes in kernel device tree
 502                  *       copied from U-Boot device tree by optee_copy_fdt_nodes
 503                  *       when OP-TEE is not detected (probe failed)
 504                  * these OP-TEE nodes are present in <board>-u-boot.dtsi
 505                  * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
 506                  * when FIP is not used by TF-A
 507                  */
 508                 if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE) &&
 509                     !tee_find_device(NULL, NULL, NULL, NULL))
 510                         stm32_fdt_disable_optee(blob);
 511         }
 512
 513         return ret;
 514 }