arch/arm/mach-stm32mp/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY LOGC_ARCH
   7
   8 #include <common.h>
   9 #include <fdt_support.h>
  10 #include <log.h>
  11 #include <tee.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  14 #include <linux/io.h>
  15
  16 #define ETZPC_DECPROT(n)        (STM32_ETZPC_BASE + 0x10 + 4 * (n))
  17 #define ETZPC_DECPROT_NB        6
  18
  19 #define DECPROT_MASK            0x03
  20 #define NB_PROT_PER_REG         0x10
  21 #define DECPROT_NB_BITS         2
  22
  23 #define DECPROT_SECURED         0x00
  24 #define DECPROT_WRITE_SECURE    0x01
  25 #define DECPROT_MCU_ISOLATION   0x02
  26 #define DECPROT_NON_SECURED     0x03
  27
  28 #define ETZPC_RESERVED          0xffffffff
  29
  30 #define STM32_FDCAN_BASE        0x4400e000
  31 #define STM32_CRYP2_BASE        0x4c005000
  32 #define STM32_CRYP1_BASE        0x54001000
  33 #define STM32_GPU_BASE          0x59000000
  34 #define STM32_DSI_BASE          0x5a000000
  35
  36 static const u32 stm32mp1_ip_addr[] = {
  37         0x5c008000,     /* 00 stgenc */
  38         0x54000000,     /* 01 bkpsram */
  39         0x5c003000,     /* 02 iwdg1 */
  40         0x5c000000,     /* 03 usart1 */
  41         0x5c001000,     /* 04 spi6 */
  42         0x5c002000,     /* 05 i2c4 */
  43         ETZPC_RESERVED, /* 06 reserved */
  44         0x54003000,     /* 07 rng1 */
  45         0x54002000,     /* 08 hash1 */
  46         STM32_CRYP1_BASE,       /* 09 cryp1 */
  47         0x5a003000,     /* 0A ddrctrl */
  48         0x5a004000,     /* 0B ddrphyc */
  49         0x5c009000,     /* 0C i2c6 */
  50         ETZPC_RESERVED, /* 0D reserved */
  51         ETZPC_RESERVED, /* 0E reserved */
  52         ETZPC_RESERVED, /* 0F reserved */
  53         0x40000000,     /* 10 tim2 */
  54         0x40001000,     /* 11 tim3 */
  55         0x40002000,     /* 12 tim4 */
  56         0x40003000,     /* 13 tim5 */
  57         0x40004000,     /* 14 tim6 */
  58         0x40005000,     /* 15 tim7 */
  59         0x40006000,     /* 16 tim12 */
  60         0x40007000,     /* 17 tim13 */
  61         0x40008000,     /* 18 tim14 */
  62         0x40009000,     /* 19 lptim1 */
  63         0x4000a000,     /* 1A wwdg1 */
  64         0x4000b000,     /* 1B spi2 */
  65         0x4000c000,     /* 1C spi3 */
  66         0x4000d000,     /* 1D spdifrx */
  67         0x4000e000,     /* 1E usart2 */
  68         0x4000f000,     /* 1F usart3 */
  69         0x40010000,     /* 20 uart4 */
  70         0x40011000,     /* 21 uart5 */
  71         0x40012000,     /* 22 i2c1 */
  72         0x40013000,     /* 23 i2c2 */
  73         0x40014000,     /* 24 i2c3 */
  74         0x40015000,     /* 25 i2c5 */
  75         0x40016000,     /* 26 cec */
  76         0x40017000,     /* 27 dac */
  77         0x40018000,     /* 28 uart7 */
  78         0x40019000,     /* 29 uart8 */
  79         ETZPC_RESERVED, /* 2A reserved */
  80         ETZPC_RESERVED, /* 2B reserved */
  81         0x4001c000,     /* 2C mdios */
  82         ETZPC_RESERVED, /* 2D reserved */
  83         ETZPC_RESERVED, /* 2E reserved */
  84         ETZPC_RESERVED, /* 2F reserved */
  85         0x44000000,     /* 30 tim1 */
  86         0x44001000,     /* 31 tim8 */
  87         ETZPC_RESERVED, /* 32 reserved */
  88         0x44003000,     /* 33 usart6 */
  89         0x44004000,     /* 34 spi1 */
  90         0x44005000,     /* 35 spi4 */
  91         0x44006000,     /* 36 tim15 */
  92         0x44007000,     /* 37 tim16 */
  93         0x44008000,     /* 38 tim17 */
  94         0x44009000,     /* 39 spi5 */
  95         0x4400a000,     /* 3A sai1 */
  96         0x4400b000,     /* 3B sai2 */
  97         0x4400c000,     /* 3C sai3 */
  98         0x4400d000,     /* 3D dfsdm */
  99         STM32_FDCAN_BASE,       /* 3E tt_fdcan */
 100         ETZPC_RESERVED, /* 3F reserved */
 101         0x50021000,     /* 40 lptim2 */
 102         0x50022000,     /* 41 lptim3 */
 103         0x50023000,     /* 42 lptim4 */
 104         0x50024000,     /* 43 lptim5 */
 105         0x50027000,     /* 44 sai4 */
 106         0x50025000,     /* 45 vrefbuf */
 107         0x4c006000,     /* 46 dcmi */
 108         0x4c004000,     /* 47 crc2 */
 109         0x48003000,     /* 48 adc */
 110         0x4c002000,     /* 49 hash2 */
 111         0x4c003000,     /* 4A rng2 */
 112         STM32_CRYP2_BASE,       /* 4B cryp2 */
 113         ETZPC_RESERVED, /* 4C reserved */
 114         ETZPC_RESERVED, /* 4D reserved */
 115         ETZPC_RESERVED, /* 4E reserved */
 116         ETZPC_RESERVED, /* 4F reserved */
 117         ETZPC_RESERVED, /* 50 sram1 */
 118         ETZPC_RESERVED, /* 51 sram2 */
 119         ETZPC_RESERVED, /* 52 sram3 */
 120         ETZPC_RESERVED, /* 53 sram4 */
 121         ETZPC_RESERVED, /* 54 retram */
 122         0x49000000,     /* 55 otg */
 123         0x48004000,     /* 56 sdmmc3 */
 124         0x48005000,     /* 57 dlybsd3 */
 125         0x48000000,     /* 58 dma1 */
 126         0x48001000,     /* 59 dma2 */
 127         0x48002000,     /* 5A dmamux */
 128         0x58002000,     /* 5B fmc */
 129         0x58003000,     /* 5C qspi */
 130         0x58004000,     /* 5D dlybq */
 131         0x5800a000,     /* 5E eth */
 132         ETZPC_RESERVED, /* 5F reserved */
 133 };
 134
 135 /* fdt helper */
 136 static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
 137 {
 138         int node;
 139         fdt_addr_t regs;
 140
 141         for (node = fdt_first_subnode(fdt, offset);
 142              node >= 0;
 143              node = fdt_next_subnode(fdt, node)) {
 144                 regs = fdtdec_get_addr(fdt, node, "reg");
 145                 if (addr == regs) {
 146                         if (fdtdec_get_is_enabled(fdt, node)) {
 147                                 fdt_status_disabled(fdt, node);
 148
 149                                 return true;
 150                         }
 151                         return false;
 152                 }
 153         }
 154
 155         return false;
 156 }
 157
 158 static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
 159 {
 160         const u32 *array;
 161         int array_size, i;
 162         int offset, shift;
 163         u32 addr, status, decprot[ETZPC_DECPROT_NB];
 164
 165         array = stm32mp1_ip_addr;
 166         array_size = ARRAY_SIZE(stm32mp1_ip_addr);
 167
 168         for (i = 0; i < ETZPC_DECPROT_NB; i++)
 169                 decprot[i] = readl(ETZPC_DECPROT(i));
 170
 171         for (i = 0; i < array_size; i++) {
 172                 offset = i / NB_PROT_PER_REG;
 173                 shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
 174                 status = (decprot[offset] >> shift) & DECPROT_MASK;
 175                 addr = array[i];
 176
 177                 log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
 178
 179                 if (addr == ETZPC_RESERVED ||
 180                     status == DECPROT_NON_SECURED)
 181                         continue;
 182
 183                 if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
 184                         log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
 185                                    addr, i, status);
 186         }
 187
 188         return 0;
 189 }
 190
 191 /* deactivate all the cpu except core 0 */
 192 static void stm32_fdt_fixup_cpu(void *blob, char *name)
 193 {
 194         int off;
 195         u32 reg;
 196
 197         off = fdt_path_offset(blob, "/cpus");
 198         if (off < 0) {
 199                 log_warning("%s: couldn't find /cpus node\n", __func__);
 200                 return;
 201         }
 202
 203         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 204         while (off != -FDT_ERR_NOTFOUND) {
 205                 reg = fdtdec_get_addr(blob, off, "reg");
 206                 if (reg != 0) {
 207                         fdt_del_node(blob, off);
 208                         log_notice("FDT: cpu %d node remove for %s\n",
 209                                    reg, name);
 210                         /* after delete we can't trust the offsets anymore */
 211                         off = -1;
 212                 }
 213                 off = fdt_node_offset_by_prop_value(blob, off,
 214                                                     "device_type", "cpu", 4);
 215         }
 216 }
 217
 218 static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
 219                               const char *string, const char *name)
 220 {
 221         if (fdt_disable_subnode_by_address(fdt, offset, addr))
 222                 log_notice("FDT: %s@%08x node disabled for %s\n",
 223                            string, addr, name);
 224 }
 225
 226 static void stm32_fdt_disable_optee(void *blob)
 227 {
 228         int off, node;
 229
 230         /* Delete "optee" firmware node */
 231         off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
 232         if (off >= 0 && fdtdec_get_is_enabled(blob, off))
 233                 fdt_del_node(blob, off);
 234
 235         /* Delete "optee@..." reserved-memory node */
 236         off = fdt_path_offset(blob, "/reserved-memory/");
 237         if (off < 0)
 238                 return;
 239         for (node = fdt_first_subnode(blob, off);
 240              node >= 0;
 241              node = fdt_next_subnode(blob, node)) {
 242                 if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
 243                         continue;
 244
 245                 if (fdt_del_node(blob, node))
 246                         printf("Failed to remove optee reserved-memory node\n");
 247         }
 248 }
 249
 250 /*
 251  * This function is called right before the kernel is booted. "blob" is the
 252  * device tree that will be passed to the kernel.
 253  */
 254 int ft_system_setup(void *blob, struct bd_info *bd)
 255 {
 256         int ret = 0;
 257         int soc;
 258         u32 pkg, cpu;
 259         char name[SOC_NAME_SIZE];
 260
 261         soc = fdt_path_offset(blob, "/soc");
 262         if (soc < 0)
 263                 return soc;
 264
 265         if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
 266                 ret = stm32_fdt_fixup_etzpc(blob, soc);
 267                 if (ret)
 268                         return ret;
 269         }
 270
 271         /* MPUs Part Numbers and name*/
 272         cpu = get_cpu_type();
 273         get_soc_name(name);
 274
 275         switch (cpu) {
 276         case CPU_STM32MP151Fxx:
 277         case CPU_STM32MP151Dxx:
 278         case CPU_STM32MP151Cxx:
 279         case CPU_STM32MP151Axx:
 280                 stm32_fdt_fixup_cpu(blob, name);
 281                 /* after cpu delete we can't trust the soc offsets anymore */
 282                 soc = fdt_path_offset(blob, "/soc");
 283                 stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
 284                 /* fall through */
 285         case CPU_STM32MP153Fxx:
 286         case CPU_STM32MP153Dxx:
 287         case CPU_STM32MP153Cxx:
 288         case CPU_STM32MP153Axx:
 289                 stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
 290                 stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
 291                 break;
 292         default:
 293                 break;
 294         }
 295
 296         switch (cpu) {
 297         case CPU_STM32MP157Dxx:
 298         case CPU_STM32MP157Axx:
 299         case CPU_STM32MP153Dxx:
 300         case CPU_STM32MP153Axx:
 301         case CPU_STM32MP151Dxx:
 302         case CPU_STM32MP151Axx:
 303                 stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
 304                 stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
 305                 break;
 306         default:
 307                 break;
 308         }
 309
 310         switch (get_cpu_package()) {
 311         case PKG_AA_LBGA448:
 312                 pkg = STM32MP_PKG_AA;
 313                 break;
 314         case PKG_AB_LBGA354:
 315                 pkg = STM32MP_PKG_AB;
 316                 break;
 317         case PKG_AC_TFBGA361:
 318                 pkg = STM32MP_PKG_AC;
 319                 break;
 320         case PKG_AD_TFBGA257:
 321                 pkg = STM32MP_PKG_AD;
 322                 break;
 323         default:
 324                 pkg = 0;
 325                 break;
 326         }
 327         if (pkg) {
 328                 do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
 329                                        "st,package", pkg, false);
 330                 do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
 331                                        "st,package", pkg, false);
 332         }
 333
 334         if (!CONFIG_IS_ENABLED(OPTEE) ||
 335             !tee_find_device(NULL, NULL, NULL, NULL))
 336                 stm32_fdt_disable_optee(blob);
 337
 338         return ret;
 339 }