1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
8 #include <debug_uart.h>
15 #include <asm/arch/bsec.h>
16 #include <asm/arch/stm32.h>
17 #include <asm/arch/sys_proto.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
20 #include <linux/bitops.h>
23 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
24 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
25 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
26 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
27 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
28 #define RCC_BDCR_VSWRST BIT(31)
29 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
30 #define RCC_DBGCFGR_DBGCKEN BIT(8)
32 /* Security register */
33 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
34 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
36 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
37 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
38 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
40 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
42 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
43 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
44 #define PWR_CR1_DBP BIT(8)
45 #define PWR_MCUCR_SBF BIT(6)
48 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
49 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
50 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
51 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
52 #define DBGMCU_IDC_DEV_ID_SHIFT 0
53 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
54 #define DBGMCU_IDC_REV_ID_SHIFT 16
57 #define GPIOZ_SECCFGR 0x54004030
59 /* boot interface from Bootrom
60 * - boot instance = bit 31:16
61 * - boot device = bit 15:0
63 #define BOOTROM_PARAM_ADDR 0x2FFC0078
64 #define BOOTROM_MODE_MASK GENMASK(15, 0)
65 #define BOOTROM_MODE_SHIFT 0
66 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
67 #define BOOTROM_INSTANCE_SHIFT 16
69 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
71 #define RPN_MASK GENMASK(7, 0)
73 /* Package = bit 27:29 of OTP16
74 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
75 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
76 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
77 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
81 #define PKG_MASK GENMASK(2, 0)
84 * early TLB into the .data section so that it not get cleared
85 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
87 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
89 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
90 #ifndef CONFIG_TFABOOT
91 static void security_init(void)
93 /* Disable the backup domain write protection */
94 /* the protection is enable at each reset by hardware */
95 /* And must be disable by software */
96 setbits_le32(PWR_CR1, PWR_CR1_DBP);
98 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
101 /* If RTC clock isn't enable so this is a cold boot then we need
102 * to reset the backup domain
104 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
105 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
106 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
108 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
111 /* allow non secure access in Write/Read for all peripheral */
112 writel(GENMASK(25, 0), ETZPC_DECPROT0);
114 /* Open SYSRAM for no secure access */
115 writel(0x0, ETZPC_TZMA1_SIZE);
117 /* enable TZC1 TZC2 clock */
118 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
120 /* Region 0 set to no access by default */
121 /* bit 0 / 16 => nsaid0 read/write Enable
122 * bit 1 / 17 => nsaid1 read/write Enable
124 * bit 15 / 31 => nsaid15 read/write Enable
126 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
127 /* bit 30 / 31 => Secure Global Enable : write/read */
128 /* bit 0 / 1 => Region Enable for filter 0/1 */
129 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
131 /* Enable Filter 0 and 1 */
132 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
134 /* RCC trust zone deactivated */
135 writel(0x0, RCC_TZCR);
137 /* TAMP: deactivate the internal tamper
138 * Bit 23 ITAMP8E: monotonic counter overflow
139 * Bit 20 ITAMP5E: RTC calendar overflow
140 * Bit 19 ITAMP4E: HSE monitoring
141 * Bit 18 ITAMP3E: LSE monitoring
142 * Bit 16 ITAMP1E: RTC power domain supply monitoring
144 writel(0x0, TAMP_CR1);
146 /* GPIOZ: deactivate the security */
147 writel(BIT(0), RCC_MP_AHB5ENSETR);
148 writel(0x0, GPIOZ_SECCFGR);
150 #endif /* CONFIG_TFABOOT */
155 static void dbgmcu_init(void)
158 * Freeze IWDG2 if Cortex-A7 is in debug mode
159 * done in TF-A for TRUSTED boot and
160 * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
162 if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
163 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
164 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
168 void spl_board_init(void)
172 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
174 #if !defined(CONFIG_TFABOOT) && \
175 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
176 /* get bootmode from ROM code boot context: saved in TAMP register */
177 static void update_bootmode(void)
180 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
181 u32 bootrom_device, bootrom_instance;
183 /* enable TAMP clock = RTCAPBEN */
184 writel(BIT(8), RCC_MP_APB5ENSETR);
186 /* read bootrom context */
188 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
190 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
192 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
193 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
196 /* save the boot mode in TAMP backup register */
197 clrsetbits_le32(TAMP_BOOT_CONTEXT,
199 boot_mode << TAMP_BOOT_MODE_SHIFT);
203 u32 get_bootmode(void)
205 /* read bootmode from TAMP backup register */
206 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
207 TAMP_BOOT_MODE_SHIFT;
211 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
212 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
213 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
215 static void early_enable_caches(void)
217 /* I-cache is already enabled in start.S: cpu_init_cp15 */
219 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
222 gd->arch.tlb_size = PGTABLE_SIZE;
223 gd->arch.tlb_addr = (unsigned long)&early_tlb;
227 if (IS_ENABLED(CONFIG_SPL_BUILD))
228 mmu_set_region_dcache_behaviour(
229 ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
230 round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
231 DCACHE_DEFAULT_OPTION);
233 mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
234 CONFIG_DDR_CACHEABLE_SIZE,
235 DCACHE_DEFAULT_OPTION);
241 int arch_cpu_init(void)
245 early_enable_caches();
247 /* early armv7 timer init: needed for polling */
250 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
251 #ifndef CONFIG_TFABOOT
255 /* Reset Coprocessor state unless it wakes up from Standby power mode */
256 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
257 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
258 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
262 boot_mode = get_bootmode();
264 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
265 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
266 #if defined(CONFIG_DEBUG_UART) && \
267 !defined(CONFIG_TFABOOT) && \
268 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
276 void enable_caches(void)
278 /* I-cache is already enabled in start.S: icache_enable() not needed */
280 /* deactivate the data cache, early enabled in arch_cpu_init() */
283 * update MMU after relocation and enable the data cache
284 * warning: the TLB location udpated in board_f.c::reserve_mmu
289 static u32 read_idc(void)
291 /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
292 if (bsec_dbgswenable()) {
293 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
295 return readl(DBGMCU_IDC);
298 if (CONFIG_IS_ENABLED(STM32MP15x))
299 return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
304 u32 get_cpu_dev(void)
306 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
309 u32 get_cpu_rev(void)
311 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
314 static u32 get_otp(int index, int shift, int mask)
320 ret = uclass_get_device_by_driver(UCLASS_MISC,
321 DM_GET_DRIVER(stm32mp_bsec),
325 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
328 return (otp >> shift) & mask;
331 /* Get Device Part Number (RPN) from OTP */
332 static u32 get_cpu_rpn(void)
334 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
337 u32 get_cpu_type(void)
339 return (get_cpu_dev() << 16) | get_cpu_rpn();
342 /* Get Package options from OTP */
343 u32 get_cpu_package(void)
345 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
348 void get_soc_name(char name[SOC_NAME_SIZE])
350 char *cpu_s, *cpu_r, *pkg;
352 /* MPUs Part Numbers */
353 switch (get_cpu_type()) {
354 case CPU_STM32MP157Fxx:
357 case CPU_STM32MP157Dxx:
360 case CPU_STM32MP157Cxx:
363 case CPU_STM32MP157Axx:
366 case CPU_STM32MP153Fxx:
369 case CPU_STM32MP153Dxx:
372 case CPU_STM32MP153Cxx:
375 case CPU_STM32MP153Axx:
378 case CPU_STM32MP151Fxx:
381 case CPU_STM32MP151Dxx:
384 case CPU_STM32MP151Cxx:
387 case CPU_STM32MP151Axx:
396 switch (get_cpu_package()) {
403 case PKG_AC_TFBGA361:
406 case PKG_AD_TFBGA257:
415 switch (get_cpu_rev()) {
430 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
433 #if defined(CONFIG_DISPLAY_CPUINFO)
434 int print_cpuinfo(void)
436 char name[SOC_NAME_SIZE];
439 printf("CPU: %s\n", name);
443 #endif /* CONFIG_DISPLAY_CPUINFO */
445 static void setup_boot_mode(void)
447 const u32 serial_addr[] = {
458 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
460 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
461 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
462 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
466 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
467 __func__, boot_ctx, boot_mode, instance, forced_mode);
468 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
469 case BOOT_SERIAL_UART:
470 if (instance > ARRAY_SIZE(serial_addr))
472 /* serial : search associated alias in devicetree */
473 sprintf(cmd, "serial@%x", serial_addr[instance]);
474 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
476 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
477 dev_of_offset(dev), &alias))
479 sprintf(cmd, "%d", alias);
480 env_set("boot_device", "serial");
481 env_set("boot_instance", cmd);
483 /* restore console on uart when not used */
484 if (gd->cur_serial_dev != dev) {
485 gd->flags &= ~(GD_FLG_SILENT |
486 GD_FLG_DISABLE_CONSOLE);
487 printf("serial boot with console enabled!\n");
490 case BOOT_SERIAL_USB:
491 env_set("boot_device", "usb");
492 env_set("boot_instance", "0");
495 case BOOT_FLASH_EMMC:
496 sprintf(cmd, "%d", instance);
497 env_set("boot_device", "mmc");
498 env_set("boot_instance", cmd);
500 case BOOT_FLASH_NAND:
501 env_set("boot_device", "nand");
502 env_set("boot_instance", "0");
504 case BOOT_FLASH_SPINAND:
505 env_set("boot_device", "spi-nand");
506 env_set("boot_instance", "0");
509 env_set("boot_device", "nor");
510 env_set("boot_instance", "0");
513 pr_debug("unexpected boot mode = %x\n", boot_mode);
517 switch (forced_mode) {
519 printf("Enter fastboot!\n");
520 env_set("preboot", "env set preboot; fastboot 0");
523 env_set("boot_device", "usb");
524 env_set("boot_instance", "0");
529 printf("Enter UMS!\n");
530 instance = forced_mode - BOOT_UMS_MMC0;
531 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
532 env_set("preboot", cmd);
535 env_set("preboot", "env set preboot; run altbootcmd");
540 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
544 /* clear TAMP for next reboot */
545 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
549 * If there is no MAC address in the environment, then it will be initialized
550 * (silently) from the value in the OTP.
552 __weak int setup_mac_address(void)
554 #if defined(CONFIG_NET)
561 /* MAC already in environment */
562 if (eth_env_get_enetaddr("ethaddr", enetaddr))
565 ret = uclass_get_device_by_driver(UCLASS_MISC,
566 DM_GET_DRIVER(stm32mp_bsec),
571 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
576 for (i = 0; i < 6; i++)
577 enetaddr[i] = ((uint8_t *)&otp)[i];
579 if (!is_valid_ethaddr(enetaddr)) {
580 pr_err("invalid MAC address in OTP %pM\n", enetaddr);
583 pr_debug("OTP MAC address = %pM\n", enetaddr);
584 ret = eth_env_set_enetaddr("ethaddr", enetaddr);
586 pr_err("Failed to set mac address %pM from OTP: %d\n",
593 static int setup_serial_number(void)
595 char serial_string[25];
596 u32 otp[3] = {0, 0, 0 };
600 if (env_get("serial#"))
603 ret = uclass_get_device_by_driver(UCLASS_MISC,
604 DM_GET_DRIVER(stm32mp_bsec),
609 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
614 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
615 env_set("serial#", serial_string);
620 int arch_misc_init(void)
624 setup_serial_number();