1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 #define LOG_CATEGORY LOGC_ARCH
11 #include <debug_uart.h>
19 #include <asm/arch/bsec.h>
20 #include <asm/arch/stm32.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/global_data.h>
23 #include <dm/device.h>
24 #include <dm/uclass.h>
25 #include <linux/bitops.h>
28 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
29 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
30 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
31 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
32 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
33 #define RCC_BDCR_VSWRST BIT(31)
34 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
35 #define RCC_DBGCFGR_DBGCKEN BIT(8)
37 /* Security register */
38 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
39 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
41 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
42 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
43 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
45 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
47 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
48 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
49 #define PWR_CR1_DBP BIT(8)
50 #define PWR_MCUCR_SBF BIT(6)
53 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
54 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
55 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
56 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
57 #define DBGMCU_IDC_DEV_ID_SHIFT 0
58 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
59 #define DBGMCU_IDC_REV_ID_SHIFT 16
62 #define GPIOZ_SECCFGR 0x54004030
64 /* boot interface from Bootrom
65 * - boot instance = bit 31:16
66 * - boot device = bit 15:0
68 #define BOOTROM_PARAM_ADDR 0x2FFC0078
69 #define BOOTROM_MODE_MASK GENMASK(15, 0)
70 #define BOOTROM_MODE_SHIFT 0
71 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
72 #define BOOTROM_INSTANCE_SHIFT 16
74 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
76 #define RPN_MASK GENMASK(7, 0)
78 /* Package = bit 27:29 of OTP16
79 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
80 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
81 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
82 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
86 #define PKG_MASK GENMASK(2, 0)
89 * early TLB into the .data section so that it not get cleared
90 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
92 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
96 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
97 #ifndef CONFIG_TFABOOT
98 static void security_init(void)
100 /* Disable the backup domain write protection */
101 /* the protection is enable at each reset by hardware */
102 /* And must be disable by software */
103 setbits_le32(PWR_CR1, PWR_CR1_DBP);
105 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
108 /* If RTC clock isn't enable so this is a cold boot then we need
109 * to reset the backup domain
111 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
112 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
113 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
115 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
118 /* allow non secure access in Write/Read for all peripheral */
119 writel(GENMASK(25, 0), ETZPC_DECPROT0);
121 /* Open SYSRAM for no secure access */
122 writel(0x0, ETZPC_TZMA1_SIZE);
124 /* enable TZC1 TZC2 clock */
125 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
127 /* Region 0 set to no access by default */
128 /* bit 0 / 16 => nsaid0 read/write Enable
129 * bit 1 / 17 => nsaid1 read/write Enable
131 * bit 15 / 31 => nsaid15 read/write Enable
133 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
134 /* bit 30 / 31 => Secure Global Enable : write/read */
135 /* bit 0 / 1 => Region Enable for filter 0/1 */
136 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
138 /* Enable Filter 0 and 1 */
139 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
141 /* RCC trust zone deactivated */
142 writel(0x0, RCC_TZCR);
144 /* TAMP: deactivate the internal tamper
145 * Bit 23 ITAMP8E: monotonic counter overflow
146 * Bit 20 ITAMP5E: RTC calendar overflow
147 * Bit 19 ITAMP4E: HSE monitoring
148 * Bit 18 ITAMP3E: LSE monitoring
149 * Bit 16 ITAMP1E: RTC power domain supply monitoring
151 writel(0x0, TAMP_CR1);
153 /* GPIOZ: deactivate the security */
154 writel(BIT(0), RCC_MP_AHB5ENSETR);
155 writel(0x0, GPIOZ_SECCFGR);
157 #endif /* CONFIG_TFABOOT */
162 static void dbgmcu_init(void)
165 * Freeze IWDG2 if Cortex-A7 is in debug mode
166 * done in TF-A for TRUSTED boot and
167 * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
169 if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
170 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
171 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
175 void spl_board_init(void)
179 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
181 #if !defined(CONFIG_TFABOOT) && \
182 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
183 /* get bootmode from ROM code boot context: saved in TAMP register */
184 static void update_bootmode(void)
187 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
188 u32 bootrom_device, bootrom_instance;
190 /* enable TAMP clock = RTCAPBEN */
191 writel(BIT(8), RCC_MP_APB5ENSETR);
193 /* read bootrom context */
195 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
197 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
199 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
200 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
203 /* save the boot mode in TAMP backup register */
204 clrsetbits_le32(TAMP_BOOT_CONTEXT,
206 boot_mode << TAMP_BOOT_MODE_SHIFT);
210 u32 get_bootmode(void)
212 /* read bootmode from TAMP backup register */
213 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
214 TAMP_BOOT_MODE_SHIFT;
218 * weak function overidde: set the DDR/SYSRAM executable before to enable the
219 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
221 void dram_bank_mmu_setup(int bank)
223 struct bd_info *bd = gd->bd;
227 bool use_lmb = false;
228 enum dcache_option option;
230 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
231 start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
232 size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
233 } else if (gd->flags & GD_FLG_RELOC) {
234 /* bd->bi_dram is available only after relocation */
235 start = bd->bi_dram[bank].start;
236 size = bd->bi_dram[bank].size;
239 /* mark cacheable and executable the beggining of the DDR */
240 start = STM32_DDR_BASE;
241 size = CONFIG_DDR_CACHEABLE_SIZE;
244 for (i = start >> MMU_SECTION_SHIFT;
245 i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
247 option = DCACHE_DEFAULT_OPTION;
248 if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
249 option = 0; /* INVALID ENTRY in TLB */
250 set_section_dcache(i, option);
254 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
255 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
256 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
258 static void early_enable_caches(void)
260 /* I-cache is already enabled in start.S: cpu_init_cp15 */
262 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
265 if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
266 gd->arch.tlb_size = PGTABLE_SIZE;
267 gd->arch.tlb_addr = (unsigned long)&early_tlb;
270 /* enable MMU (default configuration) */
277 int arch_cpu_init(void)
281 early_enable_caches();
283 /* early armv7 timer init: needed for polling */
286 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
287 #ifndef CONFIG_TFABOOT
291 /* Reset Coprocessor state unless it wakes up from Standby power mode */
292 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
293 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
294 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
298 boot_mode = get_bootmode();
300 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
301 (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
302 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
303 #if defined(CONFIG_DEBUG_UART) && \
304 !defined(CONFIG_TFABOOT) && \
305 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
313 void enable_caches(void)
315 /* parse device tree when data cache is still activated */
316 lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
318 /* I-cache is already enabled in start.S: icache_enable() not needed */
320 /* deactivate the data cache, early enabled in arch_cpu_init() */
323 * update MMU after relocation and enable the data cache
324 * warning: the TLB location udpated in board_f.c::reserve_mmu
329 static u32 read_idc(void)
331 /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
332 if (bsec_dbgswenable()) {
333 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
335 return readl(DBGMCU_IDC);
338 if (CONFIG_IS_ENABLED(STM32MP15x))
339 return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
344 u32 get_cpu_dev(void)
346 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
349 u32 get_cpu_rev(void)
351 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
354 static u32 get_otp(int index, int shift, int mask)
360 ret = uclass_get_device_by_driver(UCLASS_MISC,
361 DM_DRIVER_GET(stm32mp_bsec),
365 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
368 return (otp >> shift) & mask;
371 /* Get Device Part Number (RPN) from OTP */
372 static u32 get_cpu_rpn(void)
374 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
377 u32 get_cpu_type(void)
379 return (get_cpu_dev() << 16) | get_cpu_rpn();
382 /* Get Package options from OTP */
383 u32 get_cpu_package(void)
385 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
388 static const char * const soc_type[] = {
390 "151C", "151A", "151F", "151D",
391 "153C", "153A", "153F", "153D",
392 "157C", "157A", "157F", "157D"
395 static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
396 static const char * const soc_rev[] = { "?", "A", "B", "Z" };
398 static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
401 u32 cpu_type = get_cpu_type();
402 u32 ct = cpu_type & ~(BIT(7) | BIT(0));
403 u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
404 u32 cp = get_cpu_package();
406 /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
408 case CPU_STM32MP151Cxx:
411 case CPU_STM32MP153Cxx:
414 case CPU_STM32MP157Cxx:
426 case PKG_AC_TFBGA361:
427 case PKG_AD_TFBGA257:
436 switch (get_cpu_rev()) {
452 void get_soc_name(char name[SOC_NAME_SIZE])
454 unsigned int type, pkg, rev;
456 get_cpu_string_offsets(&type, &pkg, &rev);
458 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
459 soc_type[type], soc_pkg[pkg], soc_rev[rev]);
462 #if defined(CONFIG_DISPLAY_CPUINFO)
463 int print_cpuinfo(void)
465 char name[SOC_NAME_SIZE];
468 printf("CPU: %s\n", name);
472 #endif /* CONFIG_DISPLAY_CPUINFO */
474 static void setup_boot_mode(void)
476 const u32 serial_addr[] = {
487 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
489 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
490 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
491 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
494 log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
495 __func__, boot_ctx, boot_mode, instance, forced_mode);
496 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
497 case BOOT_SERIAL_UART:
498 if (instance > ARRAY_SIZE(serial_addr))
500 /* serial : search associated node in devicetree */
501 sprintf(cmd, "serial@%x", serial_addr[instance]);
502 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
503 /* restore console on error */
504 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
505 gd->flags &= ~(GD_FLG_SILENT |
506 GD_FLG_DISABLE_CONSOLE);
507 log_err("uart%d = %s not found in device tree!\n",
511 sprintf(cmd, "%d", dev_seq(dev));
512 env_set("boot_device", "serial");
513 env_set("boot_instance", cmd);
515 /* restore console on uart when not used */
516 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
517 gd->flags &= ~(GD_FLG_SILENT |
518 GD_FLG_DISABLE_CONSOLE);
519 log_info("serial boot with console enabled!\n");
522 case BOOT_SERIAL_USB:
523 env_set("boot_device", "usb");
524 env_set("boot_instance", "0");
527 case BOOT_FLASH_EMMC:
528 sprintf(cmd, "%d", instance);
529 env_set("boot_device", "mmc");
530 env_set("boot_instance", cmd);
532 case BOOT_FLASH_NAND:
533 env_set("boot_device", "nand");
534 env_set("boot_instance", "0");
536 case BOOT_FLASH_SPINAND:
537 env_set("boot_device", "spi-nand");
538 env_set("boot_instance", "0");
541 env_set("boot_device", "nor");
542 env_set("boot_instance", "0");
545 log_debug("unexpected boot mode = %x\n", boot_mode);
549 switch (forced_mode) {
551 log_info("Enter fastboot!\n");
552 env_set("preboot", "env set preboot; fastboot 0");
555 env_set("boot_device", "usb");
556 env_set("boot_instance", "0");
561 log_info("Enter UMS!\n");
562 instance = forced_mode - BOOT_UMS_MMC0;
563 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
564 env_set("preboot", cmd);
567 env_set("preboot", "env set preboot; run altbootcmd");
572 log_debug("unexpected forced boot mode = %x\n", forced_mode);
576 /* clear TAMP for next reboot */
577 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
581 * If there is no MAC address in the environment, then it will be initialized
582 * (silently) from the value in the OTP.
584 __weak int setup_mac_address(void)
586 #if defined(CONFIG_NET)
593 /* MAC already in environment */
594 if (eth_env_get_enetaddr("ethaddr", enetaddr))
597 ret = uclass_get_device_by_driver(UCLASS_MISC,
598 DM_DRIVER_GET(stm32mp_bsec),
603 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
608 for (i = 0; i < 6; i++)
609 enetaddr[i] = ((uint8_t *)&otp)[i];
611 if (!is_valid_ethaddr(enetaddr)) {
612 log_err("invalid MAC address in OTP %pM\n", enetaddr);
615 log_debug("OTP MAC address = %pM\n", enetaddr);
616 ret = eth_env_set_enetaddr("ethaddr", enetaddr);
618 log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
624 static int setup_serial_number(void)
626 char serial_string[25];
627 u32 otp[3] = {0, 0, 0 };
631 if (env_get("serial#"))
634 ret = uclass_get_device_by_driver(UCLASS_MISC,
635 DM_DRIVER_GET(stm32mp_bsec),
640 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
645 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
646 env_set("serial#", serial_string);
651 static void setup_soc_type_pkg_rev(void)
653 unsigned int type, pkg, rev;
655 get_cpu_string_offsets(&type, &pkg, &rev);
657 env_set("soc_type", soc_type[type]);
658 env_set("soc_pkg", soc_pkg[pkg]);
659 env_set("soc_rev", soc_rev[rev]);
662 int arch_misc_init(void)
666 setup_serial_number();
667 setup_soc_type_pkg_rev();