1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <debug_uart.h>
8 #include <environment.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/sys_proto.h>
13 #include <dm/device.h>
14 #include <dm/uclass.h>
17 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
18 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
19 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
20 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
21 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
22 #define RCC_BDCR_VSWRST BIT(31)
23 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
24 #define RCC_DBGCFGR_DBGCKEN BIT(8)
26 /* Security register */
27 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
28 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
30 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
31 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
32 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
34 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
36 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
37 #define PWR_CR1_DBP BIT(8)
40 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
41 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
42 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
43 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
44 #define DBGMCU_IDC_DEV_ID_SHIFT 0
45 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
46 #define DBGMCU_IDC_REV_ID_SHIFT 16
49 #define GPIOZ_SECCFGR 0x54004030
51 /* boot interface from Bootrom
52 * - boot instance = bit 31:16
53 * - boot device = bit 15:0
55 #define BOOTROM_PARAM_ADDR 0x2FFC0078
56 #define BOOTROM_MODE_MASK GENMASK(15, 0)
57 #define BOOTROM_MODE_SHIFT 0
58 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
59 #define BOOTROM_INSTANCE_SHIFT 16
62 #define BSEC_OTP_RPN 1
63 #define BSEC_OTP_SERIAL 13
64 #define BSEC_OTP_PKG 16
65 #define BSEC_OTP_MAC 57
67 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
69 #define RPN_MASK GENMASK(7, 0)
71 /* Package = bit 27:29 of OTP16
72 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
73 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
74 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
75 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
79 #define PKG_MASK GENMASK(2, 0)
81 #define PKG_AA_LBGA448 4
82 #define PKG_AB_LBGA354 3
83 #define PKG_AC_TFBGA361 2
84 #define PKG_AD_TFBGA257 1
86 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
87 #ifndef CONFIG_STM32MP1_TRUSTED
88 static void security_init(void)
90 /* Disable the backup domain write protection */
91 /* the protection is enable at each reset by hardware */
92 /* And must be disable by software */
93 setbits_le32(PWR_CR1, PWR_CR1_DBP);
95 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
98 /* If RTC clock isn't enable so this is a cold boot then we need
99 * to reset the backup domain
101 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
102 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
103 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
105 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
108 /* allow non secure access in Write/Read for all peripheral */
109 writel(GENMASK(25, 0), ETZPC_DECPROT0);
111 /* Open SYSRAM for no secure access */
112 writel(0x0, ETZPC_TZMA1_SIZE);
114 /* enable TZC1 TZC2 clock */
115 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
117 /* Region 0 set to no access by default */
118 /* bit 0 / 16 => nsaid0 read/write Enable
119 * bit 1 / 17 => nsaid1 read/write Enable
121 * bit 15 / 31 => nsaid15 read/write Enable
123 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
124 /* bit 30 / 31 => Secure Global Enable : write/read */
125 /* bit 0 / 1 => Region Enable for filter 0/1 */
126 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
128 /* Enable Filter 0 and 1 */
129 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
131 /* RCC trust zone deactivated */
132 writel(0x0, RCC_TZCR);
134 /* TAMP: deactivate the internal tamper
135 * Bit 23 ITAMP8E: monotonic counter overflow
136 * Bit 20 ITAMP5E: RTC calendar overflow
137 * Bit 19 ITAMP4E: HSE monitoring
138 * Bit 18 ITAMP3E: LSE monitoring
139 * Bit 16 ITAMP1E: RTC power domain supply monitoring
141 writel(0x0, TAMP_CR1);
143 /* GPIOZ: deactivate the security */
144 writel(BIT(0), RCC_MP_AHB5ENSETR);
145 writel(0x0, GPIOZ_SECCFGR);
147 #endif /* CONFIG_STM32MP1_TRUSTED */
152 static void dbgmcu_init(void)
154 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
156 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
157 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
159 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
161 #if !defined(CONFIG_STM32MP1_TRUSTED) && \
162 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
163 /* get bootmode from ROM code boot context: saved in TAMP register */
164 static void update_bootmode(void)
167 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
168 u32 bootrom_device, bootrom_instance;
170 /* enable TAMP clock = RTCAPBEN */
171 writel(BIT(8), RCC_MP_APB5ENSETR);
173 /* read bootrom context */
175 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
177 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
179 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
180 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
183 /* save the boot mode in TAMP backup register */
184 clrsetbits_le32(TAMP_BOOT_CONTEXT,
186 boot_mode << TAMP_BOOT_MODE_SHIFT);
190 u32 get_bootmode(void)
192 /* read bootmode from TAMP backup register */
193 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
194 TAMP_BOOT_MODE_SHIFT;
200 int arch_cpu_init(void)
204 /* early armv7 timer init: needed for polling */
207 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
209 #ifndef CONFIG_STM32MP1_TRUSTED
215 boot_mode = get_bootmode();
217 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
218 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
219 #if defined(CONFIG_DEBUG_UART) && \
220 !defined(CONFIG_STM32MP1_TRUSTED) && \
221 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
229 void enable_caches(void)
231 /* Enable D-cache. I-cache is already enabled in start.S */
235 static u32 read_idc(void)
237 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
239 return readl(DBGMCU_IDC);
242 u32 get_cpu_rev(void)
244 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
247 static u32 get_otp(int index, int shift, int mask)
253 ret = uclass_get_device_by_driver(UCLASS_MISC,
254 DM_GET_DRIVER(stm32mp_bsec),
258 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
261 return (otp >> shift) & mask;
264 /* Get Device Part Number (RPN) from OTP */
265 static u32 get_cpu_rpn(void)
267 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
270 u32 get_cpu_type(void)
274 id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
276 return (id << 16) | get_cpu_rpn();
279 /* Get Package options from OTP */
280 static u32 get_cpu_package(void)
282 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
285 #if defined(CONFIG_DISPLAY_CPUINFO)
286 int print_cpuinfo(void)
288 char *cpu_s, *cpu_r, *pkg;
290 /* MPUs Part Numbers */
291 switch (get_cpu_type()) {
292 case CPU_STM32MP157Cxx:
295 case CPU_STM32MP157Axx:
298 case CPU_STM32MP153Cxx:
301 case CPU_STM32MP153Axx:
304 case CPU_STM32MP151Cxx:
307 case CPU_STM32MP151Axx:
316 switch (get_cpu_package()) {
323 case PKG_AC_TFBGA361:
326 case PKG_AD_TFBGA257:
335 switch (get_cpu_rev()) {
347 printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
351 #endif /* CONFIG_DISPLAY_CPUINFO */
353 static void setup_boot_mode(void)
355 const u32 serial_addr[] = {
366 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
368 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
369 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
370 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
374 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
375 __func__, boot_ctx, boot_mode, instance, forced_mode);
376 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
377 case BOOT_SERIAL_UART:
378 if (instance > ARRAY_SIZE(serial_addr))
380 /* serial : search associated alias in devicetree */
381 sprintf(cmd, "serial@%x", serial_addr[instance]);
382 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
384 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
385 dev_of_offset(dev), &alias))
387 sprintf(cmd, "%d", alias);
388 env_set("boot_device", "serial");
389 env_set("boot_instance", cmd);
391 /* restore console on uart when not used */
392 if (gd->cur_serial_dev != dev) {
393 gd->flags &= ~(GD_FLG_SILENT |
394 GD_FLG_DISABLE_CONSOLE);
395 printf("serial boot with console enabled!\n");
398 case BOOT_SERIAL_USB:
399 env_set("boot_device", "usb");
400 env_set("boot_instance", "0");
403 case BOOT_FLASH_EMMC:
404 sprintf(cmd, "%d", instance);
405 env_set("boot_device", "mmc");
406 env_set("boot_instance", cmd);
408 case BOOT_FLASH_NAND:
409 env_set("boot_device", "nand");
410 env_set("boot_instance", "0");
413 env_set("boot_device", "nor");
414 env_set("boot_instance", "0");
417 pr_debug("unexpected boot mode = %x\n", boot_mode);
421 switch (forced_mode) {
423 printf("Enter fastboot!\n");
424 env_set("preboot", "env set preboot; fastboot 0");
427 env_set("boot_device", "usb");
428 env_set("boot_instance", "0");
433 printf("Enter UMS!\n");
434 instance = forced_mode - BOOT_UMS_MMC0;
435 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
436 env_set("preboot", cmd);
439 env_set("preboot", "env set preboot; run altbootcmd");
444 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
448 /* clear TAMP for next reboot */
449 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
453 * If there is no MAC address in the environment, then it will be initialized
454 * (silently) from the value in the OTP.
456 static int setup_mac_address(void)
458 #if defined(CONFIG_NET)
465 /* MAC already in environment */
466 if (eth_env_get_enetaddr("ethaddr", enetaddr))
469 ret = uclass_get_device_by_driver(UCLASS_MISC,
470 DM_GET_DRIVER(stm32mp_bsec),
475 ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
480 for (i = 0; i < 6; i++)
481 enetaddr[i] = ((uint8_t *)&otp)[i];
483 if (!is_valid_ethaddr(enetaddr)) {
484 pr_err("invalid MAC address in OTP %pM", enetaddr);
487 pr_debug("OTP MAC address = %pM\n", enetaddr);
488 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
490 pr_err("Failed to set mac address %pM from OTP: %d\n",
497 static int setup_serial_number(void)
499 char serial_string[25];
500 u32 otp[3] = {0, 0, 0 };
504 if (env_get("serial#"))
507 ret = uclass_get_device_by_driver(UCLASS_MISC,
508 DM_GET_DRIVER(stm32mp_bsec),
513 ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
518 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
519 env_set("serial#", serial_string);
524 int arch_misc_init(void)
528 setup_serial_number();