1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 #define LOG_CATEGORY LOGC_ARCH
11 #include <debug_uart.h>
18 #include <asm/arch/bsec.h>
19 #include <asm/arch/stm32.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/global_data.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
24 #include <linux/bitops.h>
27 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
28 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
29 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
30 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
31 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
32 #define RCC_BDCR_VSWRST BIT(31)
33 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
34 #define RCC_DBGCFGR_DBGCKEN BIT(8)
36 /* Security register */
37 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
38 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
40 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
41 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
42 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
44 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
46 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
47 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
48 #define PWR_CR1_DBP BIT(8)
49 #define PWR_MCUCR_SBF BIT(6)
52 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
53 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
55 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
56 #define DBGMCU_IDC_DEV_ID_SHIFT 0
57 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
58 #define DBGMCU_IDC_REV_ID_SHIFT 16
61 #define GPIOZ_SECCFGR 0x54004030
63 /* boot interface from Bootrom
64 * - boot instance = bit 31:16
65 * - boot device = bit 15:0
67 #define BOOTROM_PARAM_ADDR 0x2FFC0078
68 #define BOOTROM_MODE_MASK GENMASK(15, 0)
69 #define BOOTROM_MODE_SHIFT 0
70 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
71 #define BOOTROM_INSTANCE_SHIFT 16
73 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
75 #define RPN_MASK GENMASK(7, 0)
77 /* Package = bit 27:29 of OTP16
78 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
79 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
80 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
81 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
85 #define PKG_MASK GENMASK(2, 0)
88 * early TLB into the .data section so that it not get cleared
89 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
91 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
93 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
94 #ifndef CONFIG_TFABOOT
95 static void security_init(void)
97 /* Disable the backup domain write protection */
98 /* the protection is enable at each reset by hardware */
99 /* And must be disable by software */
100 setbits_le32(PWR_CR1, PWR_CR1_DBP);
102 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
105 /* If RTC clock isn't enable so this is a cold boot then we need
106 * to reset the backup domain
108 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
109 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
110 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
112 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
115 /* allow non secure access in Write/Read for all peripheral */
116 writel(GENMASK(25, 0), ETZPC_DECPROT0);
118 /* Open SYSRAM for no secure access */
119 writel(0x0, ETZPC_TZMA1_SIZE);
121 /* enable TZC1 TZC2 clock */
122 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
124 /* Region 0 set to no access by default */
125 /* bit 0 / 16 => nsaid0 read/write Enable
126 * bit 1 / 17 => nsaid1 read/write Enable
128 * bit 15 / 31 => nsaid15 read/write Enable
130 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
131 /* bit 30 / 31 => Secure Global Enable : write/read */
132 /* bit 0 / 1 => Region Enable for filter 0/1 */
133 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
135 /* Enable Filter 0 and 1 */
136 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
138 /* RCC trust zone deactivated */
139 writel(0x0, RCC_TZCR);
141 /* TAMP: deactivate the internal tamper
142 * Bit 23 ITAMP8E: monotonic counter overflow
143 * Bit 20 ITAMP5E: RTC calendar overflow
144 * Bit 19 ITAMP4E: HSE monitoring
145 * Bit 18 ITAMP3E: LSE monitoring
146 * Bit 16 ITAMP1E: RTC power domain supply monitoring
148 writel(0x0, TAMP_CR1);
150 /* GPIOZ: deactivate the security */
151 writel(BIT(0), RCC_MP_AHB5ENSETR);
152 writel(0x0, GPIOZ_SECCFGR);
154 #endif /* CONFIG_TFABOOT */
159 static void dbgmcu_init(void)
162 * Freeze IWDG2 if Cortex-A7 is in debug mode
163 * done in TF-A for TRUSTED boot and
164 * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
166 if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
167 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
172 void spl_board_init(void)
176 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
178 #if !defined(CONFIG_TFABOOT) && \
179 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
180 /* get bootmode from ROM code boot context: saved in TAMP register */
181 static void update_bootmode(void)
184 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
185 u32 bootrom_device, bootrom_instance;
187 /* enable TAMP clock = RTCAPBEN */
188 writel(BIT(8), RCC_MP_APB5ENSETR);
190 /* read bootrom context */
192 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
194 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
196 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
197 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
200 /* save the boot mode in TAMP backup register */
201 clrsetbits_le32(TAMP_BOOT_CONTEXT,
203 boot_mode << TAMP_BOOT_MODE_SHIFT);
207 u32 get_bootmode(void)
209 /* read bootmode from TAMP backup register */
210 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
211 TAMP_BOOT_MODE_SHIFT;
215 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
216 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
217 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
219 static void early_enable_caches(void)
221 /* I-cache is already enabled in start.S: cpu_init_cp15 */
223 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
226 if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
227 gd->arch.tlb_size = PGTABLE_SIZE;
228 gd->arch.tlb_addr = (unsigned long)&early_tlb;
233 if (IS_ENABLED(CONFIG_SPL_BUILD))
234 mmu_set_region_dcache_behaviour(
235 ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
236 ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
237 DCACHE_DEFAULT_OPTION);
239 mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
240 CONFIG_DDR_CACHEABLE_SIZE,
241 DCACHE_DEFAULT_OPTION);
247 int arch_cpu_init(void)
251 early_enable_caches();
253 /* early armv7 timer init: needed for polling */
256 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
257 #ifndef CONFIG_TFABOOT
261 /* Reset Coprocessor state unless it wakes up from Standby power mode */
262 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
263 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
264 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
268 boot_mode = get_bootmode();
270 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
271 (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
272 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
273 #if defined(CONFIG_DEBUG_UART) && \
274 !defined(CONFIG_TFABOOT) && \
275 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
283 void enable_caches(void)
285 /* I-cache is already enabled in start.S: icache_enable() not needed */
287 /* deactivate the data cache, early enabled in arch_cpu_init() */
290 * update MMU after relocation and enable the data cache
291 * warning: the TLB location udpated in board_f.c::reserve_mmu
296 static u32 read_idc(void)
298 /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
299 if (bsec_dbgswenable()) {
300 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
302 return readl(DBGMCU_IDC);
305 if (CONFIG_IS_ENABLED(STM32MP15x))
306 return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
311 u32 get_cpu_dev(void)
313 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
316 u32 get_cpu_rev(void)
318 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
321 static u32 get_otp(int index, int shift, int mask)
327 ret = uclass_get_device_by_driver(UCLASS_MISC,
328 DM_DRIVER_GET(stm32mp_bsec),
332 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
335 return (otp >> shift) & mask;
338 /* Get Device Part Number (RPN) from OTP */
339 static u32 get_cpu_rpn(void)
341 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
344 u32 get_cpu_type(void)
346 return (get_cpu_dev() << 16) | get_cpu_rpn();
349 /* Get Package options from OTP */
350 u32 get_cpu_package(void)
352 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
355 void get_soc_name(char name[SOC_NAME_SIZE])
357 char *cpu_s, *cpu_r, *pkg;
359 /* MPUs Part Numbers */
360 switch (get_cpu_type()) {
361 case CPU_STM32MP157Fxx:
364 case CPU_STM32MP157Dxx:
367 case CPU_STM32MP157Cxx:
370 case CPU_STM32MP157Axx:
373 case CPU_STM32MP153Fxx:
376 case CPU_STM32MP153Dxx:
379 case CPU_STM32MP153Cxx:
382 case CPU_STM32MP153Axx:
385 case CPU_STM32MP151Fxx:
388 case CPU_STM32MP151Dxx:
391 case CPU_STM32MP151Cxx:
394 case CPU_STM32MP151Axx:
403 switch (get_cpu_package()) {
410 case PKG_AC_TFBGA361:
413 case PKG_AD_TFBGA257:
422 switch (get_cpu_rev()) {
437 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
440 #if defined(CONFIG_DISPLAY_CPUINFO)
441 int print_cpuinfo(void)
443 char name[SOC_NAME_SIZE];
446 printf("CPU: %s\n", name);
450 #endif /* CONFIG_DISPLAY_CPUINFO */
452 static void setup_boot_mode(void)
454 const u32 serial_addr[] = {
465 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
467 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
468 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
469 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
472 log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
473 __func__, boot_ctx, boot_mode, instance, forced_mode);
474 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
475 case BOOT_SERIAL_UART:
476 if (instance > ARRAY_SIZE(serial_addr))
478 /* serial : search associated node in devicetree */
479 sprintf(cmd, "serial@%x", serial_addr[instance]);
480 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
481 /* restore console on error */
482 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
483 gd->flags &= ~(GD_FLG_SILENT |
484 GD_FLG_DISABLE_CONSOLE);
485 printf("uart%d = %s not found in device tree!\n",
489 sprintf(cmd, "%d", dev_seq(dev));
490 env_set("boot_device", "serial");
491 env_set("boot_instance", cmd);
493 /* restore console on uart when not used */
494 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
495 gd->flags &= ~(GD_FLG_SILENT |
496 GD_FLG_DISABLE_CONSOLE);
497 printf("serial boot with console enabled!\n");
500 case BOOT_SERIAL_USB:
501 env_set("boot_device", "usb");
502 env_set("boot_instance", "0");
505 case BOOT_FLASH_EMMC:
506 sprintf(cmd, "%d", instance);
507 env_set("boot_device", "mmc");
508 env_set("boot_instance", cmd);
510 case BOOT_FLASH_NAND:
511 env_set("boot_device", "nand");
512 env_set("boot_instance", "0");
514 case BOOT_FLASH_SPINAND:
515 env_set("boot_device", "spi-nand");
516 env_set("boot_instance", "0");
519 env_set("boot_device", "nor");
520 env_set("boot_instance", "0");
523 log_debug("unexpected boot mode = %x\n", boot_mode);
527 switch (forced_mode) {
529 printf("Enter fastboot!\n");
530 env_set("preboot", "env set preboot; fastboot 0");
533 env_set("boot_device", "usb");
534 env_set("boot_instance", "0");
539 printf("Enter UMS!\n");
540 instance = forced_mode - BOOT_UMS_MMC0;
541 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
542 env_set("preboot", cmd);
545 env_set("preboot", "env set preboot; run altbootcmd");
550 log_debug("unexpected forced boot mode = %x\n", forced_mode);
554 /* clear TAMP for next reboot */
555 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
559 * If there is no MAC address in the environment, then it will be initialized
560 * (silently) from the value in the OTP.
562 __weak int setup_mac_address(void)
564 #if defined(CONFIG_NET)
571 /* MAC already in environment */
572 if (eth_env_get_enetaddr("ethaddr", enetaddr))
575 ret = uclass_get_device_by_driver(UCLASS_MISC,
576 DM_DRIVER_GET(stm32mp_bsec),
581 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
586 for (i = 0; i < 6; i++)
587 enetaddr[i] = ((uint8_t *)&otp)[i];
589 if (!is_valid_ethaddr(enetaddr)) {
590 log_err("invalid MAC address in OTP %pM\n", enetaddr);
593 log_debug("OTP MAC address = %pM\n", enetaddr);
594 ret = eth_env_set_enetaddr("ethaddr", enetaddr);
596 log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
602 static int setup_serial_number(void)
604 char serial_string[25];
605 u32 otp[3] = {0, 0, 0 };
609 if (env_get("serial#"))
612 ret = uclass_get_device_by_driver(UCLASS_MISC,
613 DM_DRIVER_GET(stm32mp_bsec),
618 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
623 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
624 env_set("serial#", serial_string);
629 int arch_misc_init(void)
633 setup_serial_number();