1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <debug_uart.h>
8 #include <environment.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/sys_proto.h>
13 #include <dm/device.h>
14 #include <dm/uclass.h>
17 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
18 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
19 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
20 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
21 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
22 #define RCC_BDCR_VSWRST BIT(31)
23 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
24 #define RCC_DBGCFGR_DBGCKEN BIT(8)
26 /* Security register */
27 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
28 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
30 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
31 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
32 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
34 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
36 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
37 #define PWR_CR1_DBP BIT(8)
40 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
41 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
42 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
43 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
44 #define DBGMCU_IDC_DEV_ID_SHIFT 0
45 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
46 #define DBGMCU_IDC_REV_ID_SHIFT 16
49 #define GPIOZ_SECCFGR 0x54004030
51 /* boot interface from Bootrom
52 * - boot instance = bit 31:16
53 * - boot device = bit 15:0
55 #define BOOTROM_PARAM_ADDR 0x2FFC0078
56 #define BOOTROM_MODE_MASK GENMASK(15, 0)
57 #define BOOTROM_MODE_SHIFT 0
58 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
59 #define BOOTROM_INSTANCE_SHIFT 16
62 #define BSEC_OTP_RPN 1
63 #define BSEC_OTP_SERIAL 13
64 #define BSEC_OTP_PKG 16
65 #define BSEC_OTP_MAC 57
67 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
69 #define RPN_MASK GENMASK(7, 0)
71 /* Package = bit 27:29 of OTP16
72 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
73 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
74 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
75 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
79 #define PKG_MASK GENMASK(2, 0)
81 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
82 #ifndef CONFIG_STM32MP1_TRUSTED
83 static void security_init(void)
85 /* Disable the backup domain write protection */
86 /* the protection is enable at each reset by hardware */
87 /* And must be disable by software */
88 setbits_le32(PWR_CR1, PWR_CR1_DBP);
90 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
93 /* If RTC clock isn't enable so this is a cold boot then we need
94 * to reset the backup domain
96 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
97 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
98 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
100 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
103 /* allow non secure access in Write/Read for all peripheral */
104 writel(GENMASK(25, 0), ETZPC_DECPROT0);
106 /* Open SYSRAM for no secure access */
107 writel(0x0, ETZPC_TZMA1_SIZE);
109 /* enable TZC1 TZC2 clock */
110 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
112 /* Region 0 set to no access by default */
113 /* bit 0 / 16 => nsaid0 read/write Enable
114 * bit 1 / 17 => nsaid1 read/write Enable
116 * bit 15 / 31 => nsaid15 read/write Enable
118 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
119 /* bit 30 / 31 => Secure Global Enable : write/read */
120 /* bit 0 / 1 => Region Enable for filter 0/1 */
121 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
123 /* Enable Filter 0 and 1 */
124 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
126 /* RCC trust zone deactivated */
127 writel(0x0, RCC_TZCR);
129 /* TAMP: deactivate the internal tamper
130 * Bit 23 ITAMP8E: monotonic counter overflow
131 * Bit 20 ITAMP5E: RTC calendar overflow
132 * Bit 19 ITAMP4E: HSE monitoring
133 * Bit 18 ITAMP3E: LSE monitoring
134 * Bit 16 ITAMP1E: RTC power domain supply monitoring
136 writel(0x0, TAMP_CR1);
138 /* GPIOZ: deactivate the security */
139 writel(BIT(0), RCC_MP_AHB5ENSETR);
140 writel(0x0, GPIOZ_SECCFGR);
142 #endif /* CONFIG_STM32MP1_TRUSTED */
147 static void dbgmcu_init(void)
149 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
151 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
152 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
154 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
156 #if !defined(CONFIG_STM32MP1_TRUSTED) && \
157 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
158 /* get bootmode from ROM code boot context: saved in TAMP register */
159 static void update_bootmode(void)
162 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
163 u32 bootrom_device, bootrom_instance;
165 /* enable TAMP clock = RTCAPBEN */
166 writel(BIT(8), RCC_MP_APB5ENSETR);
168 /* read bootrom context */
170 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
172 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
174 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
175 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
178 /* save the boot mode in TAMP backup register */
179 clrsetbits_le32(TAMP_BOOT_CONTEXT,
181 boot_mode << TAMP_BOOT_MODE_SHIFT);
185 u32 get_bootmode(void)
187 /* read bootmode from TAMP backup register */
188 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
189 TAMP_BOOT_MODE_SHIFT;
195 int arch_cpu_init(void)
199 /* early armv7 timer init: needed for polling */
202 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
204 #ifndef CONFIG_STM32MP1_TRUSTED
210 boot_mode = get_bootmode();
212 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
213 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
214 #if defined(CONFIG_DEBUG_UART) && \
215 !defined(CONFIG_STM32MP1_TRUSTED) && \
216 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
224 void enable_caches(void)
226 /* Enable D-cache. I-cache is already enabled in start.S */
230 static u32 read_idc(void)
232 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
234 return readl(DBGMCU_IDC);
237 u32 get_cpu_rev(void)
239 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
242 static u32 get_otp(int index, int shift, int mask)
248 ret = uclass_get_device_by_driver(UCLASS_MISC,
249 DM_GET_DRIVER(stm32mp_bsec),
253 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
256 return (otp >> shift) & mask;
259 /* Get Device Part Number (RPN) from OTP */
260 static u32 get_cpu_rpn(void)
262 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
265 u32 get_cpu_type(void)
269 id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
271 return (id << 16) | get_cpu_rpn();
274 /* Get Package options from OTP */
275 u32 get_cpu_package(void)
277 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
280 #if defined(CONFIG_DISPLAY_CPUINFO)
281 int print_cpuinfo(void)
283 char *cpu_s, *cpu_r, *pkg;
285 /* MPUs Part Numbers */
286 switch (get_cpu_type()) {
287 case CPU_STM32MP157Cxx:
290 case CPU_STM32MP157Axx:
293 case CPU_STM32MP153Cxx:
296 case CPU_STM32MP153Axx:
299 case CPU_STM32MP151Cxx:
302 case CPU_STM32MP151Axx:
311 switch (get_cpu_package()) {
318 case PKG_AC_TFBGA361:
321 case PKG_AD_TFBGA257:
330 switch (get_cpu_rev()) {
342 printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
346 #endif /* CONFIG_DISPLAY_CPUINFO */
348 static void setup_boot_mode(void)
350 const u32 serial_addr[] = {
361 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
363 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
364 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
365 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
369 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
370 __func__, boot_ctx, boot_mode, instance, forced_mode);
371 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
372 case BOOT_SERIAL_UART:
373 if (instance > ARRAY_SIZE(serial_addr))
375 /* serial : search associated alias in devicetree */
376 sprintf(cmd, "serial@%x", serial_addr[instance]);
377 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
379 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
380 dev_of_offset(dev), &alias))
382 sprintf(cmd, "%d", alias);
383 env_set("boot_device", "serial");
384 env_set("boot_instance", cmd);
386 /* restore console on uart when not used */
387 if (gd->cur_serial_dev != dev) {
388 gd->flags &= ~(GD_FLG_SILENT |
389 GD_FLG_DISABLE_CONSOLE);
390 printf("serial boot with console enabled!\n");
393 case BOOT_SERIAL_USB:
394 env_set("boot_device", "usb");
395 env_set("boot_instance", "0");
398 case BOOT_FLASH_EMMC:
399 sprintf(cmd, "%d", instance);
400 env_set("boot_device", "mmc");
401 env_set("boot_instance", cmd);
403 case BOOT_FLASH_NAND:
404 env_set("boot_device", "nand");
405 env_set("boot_instance", "0");
408 env_set("boot_device", "nor");
409 env_set("boot_instance", "0");
412 pr_debug("unexpected boot mode = %x\n", boot_mode);
416 switch (forced_mode) {
418 printf("Enter fastboot!\n");
419 env_set("preboot", "env set preboot; fastboot 0");
422 env_set("boot_device", "usb");
423 env_set("boot_instance", "0");
428 printf("Enter UMS!\n");
429 instance = forced_mode - BOOT_UMS_MMC0;
430 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
431 env_set("preboot", cmd);
434 env_set("preboot", "env set preboot; run altbootcmd");
439 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
443 /* clear TAMP for next reboot */
444 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
448 * If there is no MAC address in the environment, then it will be initialized
449 * (silently) from the value in the OTP.
451 static int setup_mac_address(void)
453 #if defined(CONFIG_NET)
460 /* MAC already in environment */
461 if (eth_env_get_enetaddr("ethaddr", enetaddr))
464 ret = uclass_get_device_by_driver(UCLASS_MISC,
465 DM_GET_DRIVER(stm32mp_bsec),
470 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
475 for (i = 0; i < 6; i++)
476 enetaddr[i] = ((uint8_t *)&otp)[i];
478 if (!is_valid_ethaddr(enetaddr)) {
479 pr_err("invalid MAC address in OTP %pM\n", enetaddr);
482 pr_debug("OTP MAC address = %pM\n", enetaddr);
483 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
485 pr_err("Failed to set mac address %pM from OTP: %d\n",
492 static int setup_serial_number(void)
494 char serial_string[25];
495 u32 otp[3] = {0, 0, 0 };
499 if (env_get("serial#"))
502 ret = uclass_get_device_by_driver(UCLASS_MISC,
503 DM_GET_DRIVER(stm32mp_bsec),
508 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
513 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
514 env_set("serial#", serial_string);
519 int arch_misc_init(void)
523 setup_serial_number();