1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <debug_uart.h>
8 #include <environment.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/sys_proto.h>
13 #include <dm/device.h>
14 #include <dm/uclass.h>
17 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
18 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
19 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
20 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
21 #define RCC_BDCR_VSWRST BIT(31)
22 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
23 #define RCC_DBGCFGR_DBGCKEN BIT(8)
25 /* Security register */
26 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
27 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
29 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
30 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
31 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
33 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
35 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
36 #define PWR_CR1_DBP BIT(8)
39 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
40 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
42 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
43 #define DBGMCU_IDC_DEV_ID_SHIFT 0
44 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
45 #define DBGMCU_IDC_REV_ID_SHIFT 16
47 /* boot interface from Bootrom
48 * - boot instance = bit 31:16
49 * - boot device = bit 15:0
51 #define BOOTROM_PARAM_ADDR 0x2FFC0078
52 #define BOOTROM_MODE_MASK GENMASK(15, 0)
53 #define BOOTROM_MODE_SHIFT 0
54 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
55 #define BOOTROM_INSTANCE_SHIFT 16
58 #define BSEC_OTP_SERIAL 13
59 #define BSEC_OTP_MAC 57
61 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
62 #ifndef CONFIG_STM32MP1_TRUSTED
63 static void security_init(void)
65 /* Disable the backup domain write protection */
66 /* the protection is enable at each reset by hardware */
67 /* And must be disable by software */
68 setbits_le32(PWR_CR1, PWR_CR1_DBP);
70 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
73 /* If RTC clock isn't enable so this is a cold boot then we need
74 * to reset the backup domain
76 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
77 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
78 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
80 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
83 /* allow non secure access in Write/Read for all peripheral */
84 writel(GENMASK(25, 0), ETZPC_DECPROT0);
86 /* Open SYSRAM for no secure access */
87 writel(0x0, ETZPC_TZMA1_SIZE);
89 /* enable TZC1 TZC2 clock */
90 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
92 /* Region 0 set to no access by default */
93 /* bit 0 / 16 => nsaid0 read/write Enable
94 * bit 1 / 17 => nsaid1 read/write Enable
96 * bit 15 / 31 => nsaid15 read/write Enable
98 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
99 /* bit 30 / 31 => Secure Global Enable : write/read */
100 /* bit 0 / 1 => Region Enable for filter 0/1 */
101 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
103 /* Enable Filter 0 and 1 */
104 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
106 /* RCC trust zone deactivated */
107 writel(0x0, RCC_TZCR);
109 /* TAMP: deactivate the internal tamper
110 * Bit 23 ITAMP8E: monotonic counter overflow
111 * Bit 20 ITAMP5E: RTC calendar overflow
112 * Bit 19 ITAMP4E: HSE monitoring
113 * Bit 18 ITAMP3E: LSE monitoring
114 * Bit 16 ITAMP1E: RTC power domain supply monitoring
116 writel(0x0, TAMP_CR1);
118 #endif /* CONFIG_STM32MP1_TRUSTED */
123 static void dbgmcu_init(void)
125 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
127 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
128 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
130 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
132 static u32 get_bootmode(void)
135 #if !defined(CONFIG_STM32MP1_TRUSTED) && \
136 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
137 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
138 u32 bootrom_device, bootrom_instance;
141 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
143 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
145 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
146 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
149 /* save the boot mode in TAMP backup register */
150 clrsetbits_le32(TAMP_BOOT_CONTEXT,
152 boot_mode << TAMP_BOOT_MODE_SHIFT);
154 /* read TAMP backup register */
155 boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
156 TAMP_BOOT_MODE_SHIFT;
164 int arch_cpu_init(void)
168 /* early armv7 timer init: needed for polling */
171 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
173 #ifndef CONFIG_STM32MP1_TRUSTED
178 /* get bootmode from BootRom context: saved in TAMP register */
179 boot_mode = get_bootmode();
181 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
182 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
183 #if defined(CONFIG_DEBUG_UART) && \
184 !defined(CONFIG_STM32MP1_TRUSTED) && \
185 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
193 void enable_caches(void)
195 /* Enable D-cache. I-cache is already enabled in start.S */
199 static u32 read_idc(void)
201 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
203 return readl(DBGMCU_IDC);
206 u32 get_cpu_rev(void)
208 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
211 u32 get_cpu_type(void)
213 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
216 #if defined(CONFIG_DISPLAY_CPUINFO)
217 int print_cpuinfo(void)
221 switch (get_cpu_type()) {
222 case CPU_STMP32MP15x:
230 switch (get_cpu_rev()) {
242 printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r);
246 #endif /* CONFIG_DISPLAY_CPUINFO */
248 static void setup_boot_mode(void)
251 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
253 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
254 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
256 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d\n",
257 __func__, boot_ctx, boot_mode, instance);
259 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
260 case BOOT_SERIAL_UART:
261 sprintf(cmd, "%d", instance);
262 env_set("boot_device", "uart");
263 env_set("boot_instance", cmd);
265 case BOOT_SERIAL_USB:
266 env_set("boot_device", "usb");
267 env_set("boot_instance", "0");
270 case BOOT_FLASH_EMMC:
271 sprintf(cmd, "%d", instance);
272 env_set("boot_device", "mmc");
273 env_set("boot_instance", cmd);
275 case BOOT_FLASH_NAND:
276 env_set("boot_device", "nand");
277 env_set("boot_instance", "0");
280 env_set("boot_device", "nor");
281 env_set("boot_instance", "0");
284 pr_debug("unexpected boot mode = %x\n", boot_mode);
290 * If there is no MAC address in the environment, then it will be initialized
291 * (silently) from the value in the OTP.
293 static int setup_mac_address(void)
295 #if defined(CONFIG_NET)
302 /* MAC already in environment */
303 if (eth_env_get_enetaddr("ethaddr", enetaddr))
306 ret = uclass_get_device_by_driver(UCLASS_MISC,
307 DM_GET_DRIVER(stm32mp_bsec),
312 ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
317 for (i = 0; i < 6; i++)
318 enetaddr[i] = ((uint8_t *)&otp)[i];
320 if (!is_valid_ethaddr(enetaddr)) {
321 pr_err("invalid MAC address in OTP %pM", enetaddr);
324 pr_debug("OTP MAC address = %pM\n", enetaddr);
325 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
327 pr_err("Failed to set mac address %pM from OTP: %d\n",
334 static int setup_serial_number(void)
336 char serial_string[25];
337 u32 otp[3] = {0, 0, 0 };
341 if (env_get("serial#"))
344 ret = uclass_get_device_by_driver(UCLASS_MISC,
345 DM_GET_DRIVER(stm32mp_bsec),
350 ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
355 sprintf(serial_string, "%08x%08x%08x", otp[0], otp[1], otp[2]);
356 env_set("serial#", serial_string);
361 int arch_misc_init(void)
365 setup_serial_number();