1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
13 #include <asm/arch/stm32mp1_smc.h>
14 #include <asm/global_data.h>
15 #include <dm/uclass.h>
16 #include <jffs2/load_kernel.h>
17 #include <linux/list.h>
18 #include <linux/list_sort.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/sizes.h>
22 #include "stm32prog.h"
24 /* Primary GPT header size for 128 entries : 17kB = 34 LBA of 512B */
25 #define GPT_HEADER_SZ 34
27 #define OPT_SELECT BIT(0)
28 #define OPT_EMPTY BIT(1)
29 #define OPT_DELETE BIT(2)
31 #define IS_SELECT(part) ((part)->option & OPT_SELECT)
32 #define IS_EMPTY(part) ((part)->option & OPT_EMPTY)
33 #define IS_DELETE(part) ((part)->option & OPT_DELETE)
35 #define ALT_BUF_LEN SZ_1K
37 #define ROOTFS_MMC0_UUID \
38 EFI_GUID(0xE91C4E10, 0x16E6, 0x4C0E, \
39 0xBD, 0x0E, 0x77, 0xBE, 0xCF, 0x4A, 0x35, 0x82)
41 #define ROOTFS_MMC1_UUID \
42 EFI_GUID(0x491F6117, 0x415D, 0x4F53, \
43 0x88, 0xC9, 0x6E, 0x0D, 0xE5, 0x4D, 0xEA, 0xC6)
45 #define ROOTFS_MMC2_UUID \
46 EFI_GUID(0xFD58F1C7, 0xBE0D, 0x4338, \
47 0x88, 0xE9, 0xAD, 0x8F, 0x05, 0x0A, 0xEB, 0x18)
49 /* RAW parttion (binary / bootloader) used Linux - reserved UUID */
50 #define LINUX_RESERVED_UUID "8DA63339-0007-60C0-C436-083AC8230908"
53 * unique partition guid (uuid) for partition named "rootfs"
54 * on each MMC instance = SD Card or eMMC
55 * allow fixed kernel bootcmd: "rootf=PARTUID=e91c4e10-..."
57 static const efi_guid_t uuid_mmc[3] = {
63 /* order of column in flash layout file */
64 enum stm32prog_col_t {
74 #define FIP_TOC_HEADER_NAME 0xAA640001
76 struct fip_toc_header {
82 DECLARE_GLOBAL_DATA_PTR;
84 /* partition handling routines : CONFIG_CMD_MTDPARTS */
85 int mtdparts_init(void);
86 int find_dev_and_part(const char *id, struct mtd_device **dev,
87 u8 *part_num, struct part_info **part);
89 char *stm32prog_get_error(struct stm32prog_data *data)
91 static const char error_msg[] = "Unspecified";
93 if (strlen(data->error) == 0)
94 strcpy(data->error, error_msg);
99 static bool stm32prog_is_fip_header(struct fip_toc_header *header)
101 return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number;
104 void stm32prog_header_check(struct raw_header_s *raw_header,
105 struct image_header_s *header)
109 if (!raw_header || !header) {
110 log_debug("%s:no header data\n", __func__);
114 header->type = HEADER_NONE;
115 header->image_checksum = 0x0;
116 header->image_length = 0x0;
118 if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) {
119 header->type = HEADER_FIP;
123 if (raw_header->magic_number !=
124 (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
125 log_debug("%s:invalid magic number : 0x%x\n",
126 __func__, raw_header->magic_number);
129 /* only header v1.0 supported */
130 if (raw_header->header_version != 0x00010000) {
131 log_debug("%s:invalid header version : 0x%x\n",
132 __func__, raw_header->header_version);
135 if (raw_header->reserved1 != 0x0 || raw_header->reserved2) {
136 log_debug("%s:invalid reserved field\n", __func__);
139 for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) {
140 if (raw_header->padding[i] != 0) {
141 log_debug("%s:invalid padding field\n", __func__);
145 header->type = HEADER_STM32IMAGE;
146 header->image_checksum = le32_to_cpu(raw_header->image_checksum);
147 header->image_length = le32_to_cpu(raw_header->image_length);
152 static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header)
157 /* compute checksum on payload */
158 payload = (u8 *)addr;
160 for (i = header->image_length; i > 0; i--)
161 checksum += *(payload++);
166 /* FLASHLAYOUT PARSING *****************************************/
167 static int parse_option(struct stm32prog_data *data,
168 int i, char *p, struct stm32prog_part_t *part)
180 part->option |= OPT_SELECT;
183 part->option |= OPT_EMPTY;
186 part->option |= OPT_DELETE;
190 stm32prog_err("Layout line %d: invalid option '%c' in %s)",
196 if (!(part->option & OPT_SELECT)) {
197 stm32prog_err("Layout line %d: missing 'P' in option %s", i, p);
204 static int parse_id(struct stm32prog_data *data,
205 int i, char *p, struct stm32prog_part_t *part)
210 result = strict_strtoul(p, 0, &value);
212 if (result || value > PHASE_LAST_USER) {
213 stm32prog_err("Layout line %d: invalid phase value = %s", i, p);
220 static int parse_name(struct stm32prog_data *data,
221 int i, char *p, struct stm32prog_part_t *part)
225 if (strlen(p) < sizeof(part->name)) {
226 strcpy(part->name, p);
228 stm32prog_err("Layout line %d: partition name too long [%d]: %s",
236 static int parse_type(struct stm32prog_data *data,
237 int i, char *p, struct stm32prog_part_t *part)
243 if (!strncmp(p, "Binary", 6)) {
244 part->part_type = PART_BINARY;
246 /* search for Binary(X) case */
256 dectoul(&p[7], NULL);
258 } else if (!strcmp(p, "System")) {
259 part->part_type = PART_SYSTEM;
260 } else if (!strcmp(p, "FileSystem")) {
261 part->part_type = PART_FILESYSTEM;
262 } else if (!strcmp(p, "RawImage")) {
263 part->part_type = RAW_IMAGE;
268 stm32prog_err("Layout line %d: type parsing error : '%s'",
274 static int parse_ip(struct stm32prog_data *data,
275 int i, char *p, struct stm32prog_part_t *part)
278 unsigned int len = 0;
281 if (!strcmp(p, "none")) {
282 part->target = STM32PROG_NONE;
283 } else if (!strncmp(p, "mmc", 3)) {
284 part->target = STM32PROG_MMC;
286 } else if (!strncmp(p, "nor", 3)) {
287 part->target = STM32PROG_NOR;
289 } else if (!strncmp(p, "nand", 4)) {
290 part->target = STM32PROG_NAND;
292 } else if (!strncmp(p, "spi-nand", 8)) {
293 part->target = STM32PROG_SPI_NAND;
295 } else if (!strncmp(p, "ram", 3)) {
296 part->target = STM32PROG_RAM;
302 /* only one digit allowed for device id */
303 if (strlen(p) != len + 1) {
306 part->dev_id = p[len] - '0';
307 if (part->dev_id > 9)
312 stm32prog_err("Layout line %d: ip parsing error: '%s'", i, p);
317 static int parse_offset(struct stm32prog_data *data,
318 int i, char *p, struct stm32prog_part_t *part)
326 /* eMMC boot parttion */
327 if (!strncmp(p, "boot", 4)) {
328 if (strlen(p) != 5) {
333 else if (p[4] == '2')
339 stm32prog_err("Layout line %d: invalid part '%s'",
342 part->addr = simple_strtoull(p, &tail, 0);
343 if (tail == p || *tail != '\0') {
344 stm32prog_err("Layout line %d: invalid offset '%s'",
354 int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p,
355 struct stm32prog_part_t *part) = {
356 [COL_OPTION] = parse_option,
358 [COL_NAME] = parse_name,
359 [COL_TYPE] = parse_type,
361 [COL_OFFSET] = parse_offset,
364 static int parse_flash_layout(struct stm32prog_data *data,
368 int column = 0, part_nb = 0, ret;
369 bool end_of_line, eof;
370 char *p, *start, *last, *col;
371 struct stm32prog_part_t *part;
372 struct image_header_s header;
378 /* check if STM32image is detected */
379 stm32prog_header_check((struct raw_header_s *)addr, &header);
380 if (header.type == HEADER_STM32IMAGE) {
383 addr = addr + BL_HEADER_SIZE;
384 size = header.image_length;
386 checksum = stm32prog_header_checksum(addr, &header);
387 if (checksum != header.image_checksum) {
388 stm32prog_err("Layout: invalid checksum : 0x%x expected 0x%x",
389 checksum, header.image_checksum);
396 start = (char *)addr;
399 *last = 0x0; /* force null terminated string */
400 log_debug("flash layout =\n%s\n", start);
402 /* calculate expected number of partitions */
405 while (*p && (p < last)) {
408 if (p < last && *p == '#')
412 if (part_list_size > PHASE_LAST_USER) {
413 stm32prog_err("Layout: too many partition (%d)",
417 part = calloc(sizeof(struct stm32prog_part_t), part_list_size);
419 stm32prog_err("Layout: alloc failed");
422 data->part_array = part;
424 /* main parsing loop */
428 col = start; /* 1st column */
432 /* CR is ignored and replaced by NULL character */
447 /* comment line is skipped */
448 if (column == 0 && p == col) {
449 while ((p < last) && *p)
454 if (p >= last || !*p) {
461 /* by default continue with the next character */
467 /* replace by \0: allow string parsing for each column */
475 /* skip empty line and multiple TAB in tsv file */
476 if (strlen(col) == 0) {
478 /* skip empty line */
479 if (column == 0 && end_of_line) {
486 if (column < COL_NB_STM32) {
487 ret = parse[column](data, i, col, part);
492 /* save the beginning of the next column */
499 /* end of the line detected */
502 if (column < COL_NB_STM32) {
503 stm32prog_err("Layout line %d: no enought column", i);
510 if (part_nb >= part_list_size) {
513 stm32prog_err("Layout: no enought memory for %d part",
519 data->part_nb = part_nb;
520 if (data->part_nb == 0) {
521 stm32prog_err("Layout: no partition found");
528 static int __init part_cmp(void *priv, struct list_head *a, struct list_head *b)
530 struct stm32prog_part_t *parta, *partb;
532 parta = container_of(a, struct stm32prog_part_t, list);
533 partb = container_of(b, struct stm32prog_part_t, list);
535 if (parta->part_id != partb->part_id)
536 return parta->part_id - partb->part_id;
538 return parta->addr > partb->addr ? 1 : -1;
541 static void get_mtd_by_target(char *string, enum stm32prog_target target,
553 case STM32PROG_SPI_NAND:
554 dev_str = "spi-nand";
560 sprintf(string, "%s%d", dev_str, dev_id);
563 static int init_device(struct stm32prog_data *data,
564 struct stm32prog_dev_t *dev)
566 struct mmc *mmc = NULL;
567 struct blk_desc *block_dev = NULL;
568 struct mtd_info *mtd = NULL;
572 u64 first_addr = 0, last_addr = 0;
573 struct stm32prog_part_t *part, *next_part;
574 u64 part_addr, part_size;
576 const char *part_name;
578 switch (dev->target) {
580 if (!IS_ENABLED(CONFIG_MMC)) {
581 stm32prog_err("unknown device type = %d", dev->target);
584 mmc = find_mmc_device(dev->dev_id);
585 if (!mmc || mmc_init(mmc)) {
586 stm32prog_err("mmc device %d not found", dev->dev_id);
589 block_dev = mmc_get_blk_desc(mmc);
591 stm32prog_err("mmc device %d not probed", dev->dev_id);
594 dev->erase_size = mmc->erase_grp_size * block_dev->blksz;
597 /* reserve a full erase group for each GTP headers */
598 if (mmc->erase_grp_size > GPT_HEADER_SZ) {
599 first_addr = dev->erase_size;
600 last_addr = (u64)(block_dev->lba -
601 mmc->erase_grp_size) *
604 first_addr = (u64)GPT_HEADER_SZ * block_dev->blksz;
605 last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) *
608 log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
609 block_dev->lba, block_dev->blksz);
610 log_debug(" available address = 0x%llx..0x%llx\n",
611 first_addr, last_addr);
612 log_debug(" full_update = %d\n", dev->full_update);
616 case STM32PROG_SPI_NAND:
617 if (!IS_ENABLED(CONFIG_MTD)) {
618 stm32prog_err("unknown device type = %d", dev->target);
621 get_mtd_by_target(mtd_id, dev->target, dev->dev_id);
622 log_debug("%s\n", mtd_id);
625 mtd = get_mtd_device_nm(mtd_id);
627 stm32prog_err("MTD device %s not found", mtd_id);
631 last_addr = mtd->size;
632 dev->erase_size = mtd->erasesize;
633 log_debug("MTD device %s: size=%lld erasesize=%d\n",
634 mtd_id, mtd->size, mtd->erasesize);
635 log_debug(" available address = 0x%llx..0x%llx\n",
636 first_addr, last_addr);
640 first_addr = gd->bd->bi_dram[0].start;
641 last_addr = first_addr + gd->bd->bi_dram[0].size;
645 stm32prog_err("unknown device type = %d", dev->target);
648 log_debug(" erase size = 0x%x\n", dev->erase_size);
649 log_debug(" full_update = %d\n", dev->full_update);
651 /* order partition list in offset order */
652 list_sort(NULL, &dev->part_list, &part_cmp);
654 log_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n");
655 list_for_each_entry(part, &dev->part_list, list) {
656 if (part->bin_nb > 1) {
657 if ((dev->target != STM32PROG_NAND &&
658 dev->target != STM32PROG_SPI_NAND) ||
659 part->id >= PHASE_FIRST_USER ||
660 strncmp(part->name, "fsbl", 4)) {
661 stm32prog_err("%s (0x%x): multiple binary %d not supported",
662 part->name, part->id,
667 if (part->part_type == RAW_IMAGE) {
671 part->size = block_dev->lba * block_dev->blksz;
673 part->size = last_addr;
674 log_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n",
675 part->option, part->id, part->name,
676 part->part_type, part->bin_nb, part->target,
677 part->dev_id, part->addr, part->size);
680 if (part->part_id < 0) { /* boot hw partition for eMMC */
682 part->size = mmc->capacity_boot;
684 stm32prog_err("%s (0x%x): hw partition not expected : %d",
685 part->name, part->id,
690 part->part_id = part_id++;
692 /* last partition : size to the end of the device */
693 if (part->list.next != &dev->part_list) {
695 container_of(part->list.next,
696 struct stm32prog_part_t,
698 if (part->addr < next_part->addr) {
699 part->size = next_part->addr -
702 stm32prog_err("%s (0x%x): same address : 0x%llx == %s (0x%x): 0x%llx",
703 part->name, part->id,
711 if (part->addr <= last_addr) {
712 part->size = last_addr - part->addr;
714 stm32prog_err("%s (0x%x): invalid address 0x%llx (max=0x%llx)",
715 part->name, part->id,
716 part->addr, last_addr);
720 if (part->addr < first_addr) {
721 stm32prog_err("%s (0x%x): invalid address 0x%llx (min=0x%llx)",
722 part->name, part->id,
723 part->addr, first_addr);
727 if ((part->addr & ((u64)part->dev->erase_size - 1)) != 0) {
728 stm32prog_err("%s (0x%x): not aligned address : 0x%llx on erase size 0x%x",
729 part->name, part->id, part->addr,
730 part->dev->erase_size);
733 log_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx",
734 part->part_id, part->option, part->id, part->name,
735 part->part_type, part->bin_nb, part->target,
736 part->dev_id, part->addr, part->size);
742 /* check coherency with existing partition */
745 * block devices with GPT: check user partition size
746 * only for partial update, the GPT partions are be
747 * created for full update
749 if (dev->full_update || part->part_id < 0) {
753 struct disk_partition partinfo;
755 ret = part_get_info(block_dev, part->part_id,
759 stm32prog_err("%s (0x%x):Couldn't find part %d on device mmc %d",
760 part->name, part->id,
761 part_id, part->dev_id);
764 part_addr = (u64)partinfo.start * partinfo.blksz;
765 part_size = (u64)partinfo.size * partinfo.blksz;
766 part_name = (char *)partinfo.name;
770 if (IS_ENABLED(CONFIG_MTD) && mtd) {
771 char mtd_part_id[32];
772 struct part_info *mtd_part;
773 struct mtd_device *mtd_dev;
776 sprintf(mtd_part_id, "%s,%d", mtd_id,
778 ret = find_dev_and_part(mtd_part_id, &mtd_dev,
779 &part_num, &mtd_part);
781 stm32prog_err("%s (0x%x): Invalid MTD partition %s",
782 part->name, part->id,
786 part_addr = mtd_part->offset;
787 part_size = mtd_part->size;
788 part_name = mtd_part->name;
792 /* no partition for this device */
798 log_debug(" %08llx %08llx\n", part_addr, part_size);
800 if (part->addr != part_addr) {
801 stm32prog_err("%s (0x%x): Bad address for partition %d (%s) = 0x%llx <> 0x%llx expected",
802 part->name, part->id, part->part_id,
803 part_name, part->addr, part_addr);
806 if (part->size != part_size) {
807 stm32prog_err("%s (0x%x): Bad size for partition %d (%s) at 0x%llx = 0x%llx <> 0x%llx expected",
808 part->name, part->id, part->part_id,
809 part_name, part->addr, part->size,
817 static int treat_partition_list(struct stm32prog_data *data)
820 struct stm32prog_part_t *part;
822 for (j = 0; j < STM32PROG_MAX_DEV; j++) {
823 data->dev[j].target = STM32PROG_NONE;
824 INIT_LIST_HEAD(&data->dev[j].part_list);
827 data->tee_detected = false;
828 data->fsbl_nor_detected = false;
829 for (i = 0; i < data->part_nb; i++) {
830 part = &data->part_array[i];
833 /* skip partition with IP="none" */
834 if (part->target == STM32PROG_NONE) {
835 if (IS_SELECT(part)) {
836 stm32prog_err("Layout: selected none phase = 0x%x",
843 if (part->id == PHASE_FLASHLAYOUT ||
844 part->id > PHASE_LAST_USER) {
845 stm32prog_err("Layout: invalid phase = 0x%x",
849 for (j = i + 1; j < data->part_nb; j++) {
850 if (part->id == data->part_array[j].id) {
851 stm32prog_err("Layout: duplicated phase 0x%x at line %d and %d",
856 for (j = 0; j < STM32PROG_MAX_DEV; j++) {
857 if (data->dev[j].target == STM32PROG_NONE) {
858 /* new device found */
859 data->dev[j].target = part->target;
860 data->dev[j].dev_id = part->dev_id;
861 data->dev[j].full_update = true;
864 } else if ((part->target == data->dev[j].target) &&
865 (part->dev_id == data->dev[j].dev_id)) {
869 if (j == STM32PROG_MAX_DEV) {
870 stm32prog_err("Layout: too many device");
873 switch (part->target) {
875 if (!data->fsbl_nor_detected &&
876 !strncmp(part->name, "fsbl", 4))
877 data->fsbl_nor_detected = true;
880 case STM32PROG_SPI_NAND:
881 if (!data->tee_detected &&
882 !strncmp(part->name, "tee", 3))
883 data->tee_detected = true;
888 part->dev = &data->dev[j];
889 if (!IS_SELECT(part))
890 part->dev->full_update = false;
891 list_add_tail(&part->list, &data->dev[j].part_list);
897 static int create_gpt_partitions(struct stm32prog_data *data)
900 const int buflen = SZ_8K;
902 char uuid[UUID_STR_LEN + 1];
903 unsigned char *uuid_bin;
907 struct stm32prog_part_t *part;
909 buf = malloc(buflen);
913 puts("partitions : ");
914 /* initialize the selected device */
915 for (i = 0; i < data->dev_nb; i++) {
916 /* create gpt partition support only for full update on MMC */
917 if (data->dev[i].target != STM32PROG_MMC ||
918 !data->dev[i].full_update)
922 rootfs_found = false;
923 memset(buf, 0, buflen);
925 list_for_each_entry(part, &data->dev[i].part_list, list) {
926 /* skip eMMC boot partitions */
927 if (part->part_id < 0)
930 if (part->part_type == RAW_IMAGE)
933 if (offset + 100 > buflen) {
934 log_debug("\n%s: buffer too small, %s skippped",
935 __func__, part->name);
940 offset += sprintf(buf, "gpt write mmc %d \"",
941 data->dev[i].dev_id);
943 offset += snprintf(buf + offset, buflen - offset,
944 "name=%s,start=0x%llx,size=0x%llx",
949 if (part->part_type == PART_BINARY)
950 offset += snprintf(buf + offset,
953 LINUX_RESERVED_UUID);
955 offset += snprintf(buf + offset,
959 if (part->part_type == PART_SYSTEM)
960 offset += snprintf(buf + offset,
964 if (!rootfs_found && !strcmp(part->name, "rootfs")) {
965 mmc_id = part->dev_id;
967 if (mmc_id < ARRAY_SIZE(uuid_mmc)) {
969 (unsigned char *)uuid_mmc[mmc_id].b;
970 uuid_bin_to_str(uuid_bin, uuid,
971 UUID_STR_FORMAT_GUID);
972 offset += snprintf(buf + offset,
978 offset += snprintf(buf + offset, buflen - offset, ";");
982 offset += snprintf(buf + offset, buflen - offset, "\"");
983 log_debug("\ncmd: %s\n", buf);
984 if (run_command(buf, 0)) {
985 stm32prog_err("GPT partitionning fail: %s",
993 if (data->dev[i].mmc)
994 part_init(mmc_get_blk_desc(data->dev[i].mmc));
997 sprintf(buf, "gpt verify mmc %d", data->dev[i].dev_id);
998 log_debug("\ncmd: %s", buf);
999 if (run_command(buf, 0))
1004 sprintf(buf, "part list mmc %d", data->dev[i].dev_id);
1005 run_command(buf, 0);
1011 run_command("mtd list", 0);
1018 static int stm32prog_alt_add(struct stm32prog_data *data,
1019 struct dfu_entity *dfu,
1020 struct stm32prog_part_t *part)
1026 char buf[ALT_BUF_LEN];
1028 char multiplier, type;
1030 /* max 3 digit for sector size */
1031 if (part->size > SZ_1M) {
1032 size = (u32)(part->size / SZ_1M);
1034 } else if (part->size > SZ_1K) {
1035 size = (u32)(part->size / SZ_1K);
1038 size = (u32)part->size;
1041 if (IS_SELECT(part) && !IS_EMPTY(part))
1042 type = 'e'; /*Readable and Writeable*/
1044 type = 'a';/*Readable*/
1046 memset(buf, 0, sizeof(buf));
1047 offset = snprintf(buf, ALT_BUF_LEN - offset,
1048 "@%s/0x%02x/1*%d%c%c ",
1049 part->name, part->id,
1050 size, multiplier, type);
1052 if (part->target == STM32PROG_RAM) {
1053 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1054 "ram 0x%llx 0x%llx",
1055 part->addr, part->size);
1056 } else if (part->part_type == RAW_IMAGE) {
1059 if (part->dev->target == STM32PROG_MMC)
1060 dfu_size = part->size / part->dev->mmc->read_bl_len;
1062 dfu_size = part->size;
1063 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1064 "raw 0x0 0x%llx", dfu_size);
1065 } else if (part->part_id < 0) {
1066 u64 nb_blk = part->size / part->dev->mmc->read_bl_len;
1068 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1069 "raw 0x%llx 0x%llx",
1070 part->addr, nb_blk);
1071 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1072 " mmcpart %d;", -(part->part_id));
1074 if (part->part_type == PART_SYSTEM &&
1075 (part->target == STM32PROG_NAND ||
1076 part->target == STM32PROG_NOR ||
1077 part->target == STM32PROG_SPI_NAND))
1078 offset += snprintf(buf + offset,
1079 ALT_BUF_LEN - offset,
1082 offset += snprintf(buf + offset,
1083 ALT_BUF_LEN - offset,
1085 /* dev_id requested by DFU MMC */
1086 if (part->target == STM32PROG_MMC)
1087 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1088 " %d", part->dev_id);
1089 offset += snprintf(buf + offset, ALT_BUF_LEN - offset,
1090 " %d;", part->part_id);
1093 switch (part->target) {
1095 if (IS_ENABLED(CONFIG_MMC)) {
1097 sprintf(dfustr, "mmc");
1098 sprintf(devstr, "%d", part->dev_id);
1101 case STM32PROG_NAND:
1103 case STM32PROG_SPI_NAND:
1104 if (IS_ENABLED(CONFIG_MTD)) {
1106 sprintf(dfustr, "mtd");
1107 get_mtd_by_target(devstr, part->target, part->dev_id);
1112 sprintf(dfustr, "ram");
1113 sprintf(devstr, "0");
1119 stm32prog_err("invalid target: %d", part->target);
1122 log_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf);
1123 ret = dfu_alt_add(dfu, dfustr, devstr, buf);
1124 log_debug("dfu_alt_add(%s,%s,%s) result %d\n",
1125 dfustr, devstr, buf, ret);
1130 static int stm32prog_alt_add_virt(struct dfu_entity *dfu,
1131 char *name, int phase, int size)
1135 char buf[ALT_BUF_LEN];
1137 sprintf(devstr, "%d", phase);
1138 sprintf(buf, "@%s/0x%02x/1*%dBe", name, phase, size);
1139 ret = dfu_alt_add(dfu, "virt", devstr, buf);
1140 log_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret);
1145 static int dfu_init_entities(struct stm32prog_data *data)
1148 int phase, i, alt_id;
1149 struct stm32prog_part_t *part;
1150 struct dfu_entity *dfu;
1153 alt_nb = 2; /* number of virtual = CMD, OTP*/
1154 if (CONFIG_IS_ENABLED(DM_PMIC))
1155 alt_nb++; /* PMIC NVMEM*/
1157 if (data->part_nb == 0)
1158 alt_nb++; /* +1 for FlashLayout */
1160 for (i = 0; i < data->part_nb; i++) {
1161 if (data->part_array[i].target != STM32PROG_NONE)
1165 if (dfu_alt_init(alt_nb, &dfu))
1168 puts("DFU alt info setting: ");
1169 if (data->part_nb) {
1172 (phase <= PHASE_LAST_USER) &&
1173 (alt_id < alt_nb) && !ret;
1175 /* ordering alt setting by phase id */
1177 for (i = 0; i < data->part_nb; i++) {
1178 if (phase == data->part_array[i].id) {
1179 part = &data->part_array[i];
1185 if (part->target == STM32PROG_NONE)
1187 part->alt_id = alt_id;
1190 ret = stm32prog_alt_add(data, dfu, part);
1193 char buf[ALT_BUF_LEN];
1195 sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000",
1196 PHASE_FLASHLAYOUT, STM32_DDR_BASE);
1197 ret = dfu_alt_add(dfu, "ram", NULL, buf);
1198 log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
1202 ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE);
1205 ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, OTP_SIZE);
1207 if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
1208 ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE);
1211 stm32prog_err("dfu init failed: %d", ret);
1215 dfu_show_entities();
1220 int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
1223 log_debug("%s: %x %lx\n", __func__, offset, *size);
1225 if (!data->otp_part) {
1226 data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE);
1227 if (!data->otp_part)
1232 memset(data->otp_part, 0, OTP_SIZE);
1234 if (offset + *size > OTP_SIZE)
1235 *size = OTP_SIZE - offset;
1237 memcpy((void *)((u32)data->otp_part + offset), buffer, *size);
1242 int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
1247 if (!IS_ENABLED(CONFIG_ARM_SMCCC)) {
1248 stm32prog_err("OTP update not supported");
1253 log_debug("%s: %x %lx\n", __func__, offset, *size);
1254 /* alway read for first packet */
1256 if (!data->otp_part)
1258 memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE);
1260 if (!data->otp_part) {
1265 /* init struct with 0 */
1266 memset(data->otp_part, 0, OTP_SIZE);
1268 /* call the service */
1269 result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL,
1270 (u32)data->otp_part, 0);
1275 if (!data->otp_part) {
1280 if (offset + *size > OTP_SIZE)
1281 *size = OTP_SIZE - offset;
1282 memcpy(buffer, (void *)((u32)data->otp_part + offset), *size);
1285 log_debug("%s: result %i\n", __func__, result);
1290 int stm32prog_otp_start(struct stm32prog_data *data)
1293 struct arm_smccc_res res;
1295 if (!IS_ENABLED(CONFIG_ARM_SMCCC)) {
1296 stm32prog_err("OTP update not supported");
1301 if (!data->otp_part) {
1302 stm32prog_err("start OTP without data");
1306 arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL,
1307 (u32)data->otp_part, 0, 0, 0, 0, 0, &res);
1315 stm32prog_err("Provisioning");
1319 log_err("%s: OTP incorrect value (err = %ld)\n",
1325 log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
1326 __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0);
1330 free(data->otp_part);
1331 data->otp_part = NULL;
1332 log_debug("%s: result %i\n", __func__, result);
1337 int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
1340 log_debug("%s: %x %lx\n", __func__, offset, *size);
1343 memset(data->pmic_part, 0, PMIC_SIZE);
1345 if (offset + *size > PMIC_SIZE)
1346 *size = PMIC_SIZE - offset;
1348 memcpy(&data->pmic_part[offset], buffer, *size);
1353 int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
1356 int result = 0, ret;
1357 struct udevice *dev;
1359 if (!CONFIG_IS_ENABLED(PMIC_STPMIC1)) {
1360 stm32prog_err("PMIC update not supported");
1365 log_debug("%s: %x %lx\n", __func__, offset, *size);
1366 ret = uclass_get_device_by_driver(UCLASS_MISC,
1367 DM_DRIVER_GET(stpmic1_nvm),
1372 /* alway request PMIC for first packet */
1374 /* init struct with 0 */
1375 memset(data->pmic_part, 0, PMIC_SIZE);
1377 ret = uclass_get_device_by_driver(UCLASS_MISC,
1378 DM_DRIVER_GET(stpmic1_nvm),
1383 ret = misc_read(dev, 0xF8, data->pmic_part, PMIC_SIZE);
1388 if (ret != PMIC_SIZE) {
1394 if (offset + *size > PMIC_SIZE)
1395 *size = PMIC_SIZE - offset;
1397 memcpy(buffer, &data->pmic_part[offset], *size);
1400 log_debug("%s: result %i\n", __func__, result);
1404 int stm32prog_pmic_start(struct stm32prog_data *data)
1407 struct udevice *dev;
1409 if (!CONFIG_IS_ENABLED(PMIC_STPMIC1)) {
1410 stm32prog_err("PMIC update not supported");
1415 ret = uclass_get_device_by_driver(UCLASS_MISC,
1416 DM_DRIVER_GET(stpmic1_nvm),
1421 return misc_write(dev, 0xF8, data->pmic_part, PMIC_SIZE);
1424 /* copy FSBL on NAND to improve reliability on NAND */
1425 static int stm32prog_copy_fsbl(struct stm32prog_part_t *part)
1429 struct image_header_s header;
1430 struct raw_header_s raw_header;
1431 struct dfu_entity *dfu;
1434 if (part->target != STM32PROG_NAND &&
1435 part->target != STM32PROG_SPI_NAND)
1438 dfu = dfu_get_entity(part->alt_id);
1441 dfu_transaction_cleanup(dfu);
1442 size = BL_HEADER_SIZE;
1443 ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size);
1447 stm32prog_header_check(&raw_header, &header);
1448 if (header.type != HEADER_STM32IMAGE)
1451 /* read header + payload */
1452 size = header.image_length + BL_HEADER_SIZE;
1453 size = round_up(size, part->dev->mtd->erasesize);
1454 fsbl = calloc(1, size);
1457 ret = dfu->read_medium(dfu, 0, fsbl, &size);
1458 log_debug("%s read size=%lx ret=%d\n", __func__, size, ret);
1462 dfu_transaction_cleanup(dfu);
1464 for (i = part->bin_nb - 1; i > 0; i--) {
1466 /* write to the next erase block */
1467 ret = dfu->write_medium(dfu, offset, fsbl, &size);
1468 log_debug("%s copy at ofset=%lx size=%lx ret=%d",
1469 __func__, offset, size, ret);
1479 static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset)
1481 if (data->phase == PHASE_FLASHLAYOUT) {
1482 if (parse_flash_layout(data, STM32_DDR_BASE, 0))
1483 stm32prog_err("Layout: invalid FlashLayout");
1487 if (!data->cur_part)
1490 if (data->cur_part->target == STM32PROG_RAM) {
1491 if (data->cur_part->part_type == PART_SYSTEM)
1492 data->uimage = data->cur_part->addr;
1493 if (data->cur_part->part_type == PART_FILESYSTEM)
1494 data->dtb = data->cur_part->addr;
1495 if (data->cur_part->part_type == PART_BINARY) {
1496 data->initrd = data->cur_part->addr;
1497 data->initrd_size = offset;
1501 if (CONFIG_IS_ENABLED(MMC) &&
1502 data->cur_part->part_id < 0) {
1505 sprintf(cmdbuf, "mmc bootbus %d 0 0 0; mmc partconf %d 1 %d 0",
1506 data->cur_part->dev_id, data->cur_part->dev_id,
1507 -(data->cur_part->part_id));
1508 if (run_command(cmdbuf, 0)) {
1509 stm32prog_err("commands '%s' failed", cmdbuf);
1514 if (CONFIG_IS_ENABLED(MTD) &&
1515 data->cur_part->bin_nb > 1) {
1516 if (stm32prog_copy_fsbl(data->cur_part)) {
1517 stm32prog_err("%s (0x%x): copy of fsbl failed",
1518 data->cur_part->name, data->cur_part->id);
1524 void stm32prog_do_reset(struct stm32prog_data *data)
1526 if (data->phase == PHASE_RESET) {
1527 data->phase = PHASE_DO_RESET;
1528 puts("Reset requested\n");
1532 void stm32prog_next_phase(struct stm32prog_data *data)
1535 struct stm32prog_part_t *part;
1538 phase = data->phase;
1542 case PHASE_DO_RESET:
1546 /* found next selected partition */
1548 data->cur_part = NULL;
1549 data->phase = PHASE_END;
1553 if (phase > PHASE_LAST_USER)
1555 for (i = 0; i < data->part_nb; i++) {
1556 part = &data->part_array[i];
1557 if (part->id == phase) {
1558 if (IS_SELECT(part) && !IS_EMPTY(part)) {
1559 data->cur_part = part;
1560 data->phase = phase;
1568 if (data->phase == PHASE_END)
1569 puts("Phase=END\n");
1572 static int part_delete(struct stm32prog_data *data,
1573 struct stm32prog_part_t *part)
1576 unsigned long blks, blks_offset, blks_size;
1577 struct blk_desc *block_dev = NULL;
1581 printf("Erasing %s ", part->name);
1582 switch (part->target) {
1584 if (!IS_ENABLED(CONFIG_MMC)) {
1586 stm32prog_err("%s (0x%x): erase invalid",
1587 part->name, part->id);
1590 printf("on mmc %d: ", part->dev->dev_id);
1591 block_dev = mmc_get_blk_desc(part->dev->mmc);
1592 blks_offset = lldiv(part->addr, part->dev->mmc->read_bl_len);
1593 blks_size = lldiv(part->size, part->dev->mmc->read_bl_len);
1594 /* -1 or -2 : delete boot partition of MMC
1595 * need to switch to associated hwpart 1 or 2
1597 if (part->part_id < 0)
1598 if (blk_select_hwpart_devnum(IF_TYPE_MMC,
1603 blks = blk_derase(block_dev, blks_offset, blks_size);
1605 /* return to user partition */
1606 if (part->part_id < 0)
1607 blk_select_hwpart_devnum(IF_TYPE_MMC,
1608 part->dev->dev_id, 0);
1609 if (blks != blks_size) {
1611 stm32prog_err("%s (0x%x): MMC erase failed",
1612 part->name, part->id);
1616 case STM32PROG_NAND:
1617 case STM32PROG_SPI_NAND:
1618 if (!IS_ENABLED(CONFIG_MTD)) {
1620 stm32prog_err("%s (0x%x): erase invalid",
1621 part->name, part->id);
1624 get_mtd_by_target(devstr, part->target, part->dev->dev_id);
1625 printf("on %s: ", devstr);
1626 sprintf(cmdbuf, "mtd erase %s 0x%llx 0x%llx",
1627 devstr, part->addr, part->size);
1628 if (run_command(cmdbuf, 0)) {
1630 stm32prog_err("%s (0x%x): MTD erase commands failed (%s)",
1631 part->name, part->id, cmdbuf);
1636 memset((void *)(uintptr_t)part->addr, 0, (size_t)part->size);
1640 stm32prog_err("%s (0x%x): erase invalid", part->name, part->id);
1649 static void stm32prog_devices_init(struct stm32prog_data *data)
1653 struct stm32prog_part_t *part;
1655 ret = treat_partition_list(data);
1659 /* initialize the selected device */
1660 for (i = 0; i < data->dev_nb; i++) {
1661 ret = init_device(data, &data->dev[i]);
1666 /* delete RAW partition before create partition */
1667 for (i = 0; i < data->part_nb; i++) {
1668 part = &data->part_array[i];
1670 if (part->part_type != RAW_IMAGE)
1673 if (!IS_SELECT(part) || !IS_DELETE(part))
1676 ret = part_delete(data, part);
1681 if (IS_ENABLED(CONFIG_MMC)) {
1682 ret = create_gpt_partitions(data);
1687 /* delete partition GPT or MTD */
1688 for (i = 0; i < data->part_nb; i++) {
1689 part = &data->part_array[i];
1691 if (part->part_type == RAW_IMAGE)
1694 if (!IS_SELECT(part) || !IS_DELETE(part))
1697 ret = part_delete(data, part);
1708 int stm32prog_dfu_init(struct stm32prog_data *data)
1710 /* init device if no error */
1712 stm32prog_devices_init(data);
1715 stm32prog_next_phase(data);
1717 /* prepare DFU for device read/write */
1718 dfu_free_entities();
1719 return dfu_init_entities(data);
1722 int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size)
1724 memset(data, 0x0, sizeof(*data));
1725 data->read_phase = PHASE_RESET;
1726 data->phase = PHASE_FLASHLAYOUT;
1728 return parse_flash_layout(data, addr, size);
1731 void stm32prog_clean(struct stm32prog_data *data)
1734 dfu_free_entities();
1735 free(data->part_array);
1736 free(data->otp_part);
1740 /* DFU callback: used after serial and direct DFU USB access */
1741 void dfu_flush_callback(struct dfu_entity *dfu)
1743 if (!stm32prog_data)
1746 if (dfu->dev_type == DFU_DEV_VIRT) {
1747 if (dfu->data.virt.dev_num == PHASE_OTP)
1748 stm32prog_otp_start(stm32prog_data);
1749 else if (dfu->data.virt.dev_num == PHASE_PMIC)
1750 stm32prog_pmic_start(stm32prog_data);
1754 if (dfu->dev_type == DFU_DEV_RAM) {
1755 if (dfu->alt == 0 &&
1756 stm32prog_data->phase == PHASE_FLASHLAYOUT) {
1757 stm32prog_end_phase(stm32prog_data, dfu->offset);
1758 /* waiting DFU DETACH for reenumeration */
1762 if (!stm32prog_data->cur_part)
1765 if (dfu->alt == stm32prog_data->cur_part->alt_id) {
1766 stm32prog_end_phase(stm32prog_data, dfu->offset);
1767 stm32prog_next_phase(stm32prog_data);
1771 void dfu_initiated_callback(struct dfu_entity *dfu)
1773 if (!stm32prog_data)
1776 if (!stm32prog_data->cur_part)
1779 /* force the saved offset for the current partition */
1780 if (dfu->alt == stm32prog_data->cur_part->alt_id) {
1781 dfu->offset = stm32prog_data->offset;
1782 stm32prog_data->dfu_seq = 0;
1783 log_debug("dfu offset = 0x%llx\n", dfu->offset);
1787 void dfu_error_callback(struct dfu_entity *dfu, const char *msg)
1789 struct stm32prog_data *data = stm32prog_data;
1791 if (!stm32prog_data)
1794 if (!stm32prog_data->cur_part)
1797 if (dfu->alt == stm32prog_data->cur_part->alt_id)