1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
8 #include <asm/u-boot.h>
11 #include <debug_uart.h>
14 #include <asm/arch/clock_manager.h>
15 #include <asm/arch/firewall.h>
16 #include <asm/arch/mailbox_s10.h>
17 #include <asm/arch/misc.h>
18 #include <asm/arch/reset_manager.h>
19 #include <asm/arch/system_manager.h>
21 #include <dm/uclass.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 u32 spl_boot_device(void)
27 /* TODO: Get from SDM or handoff */
28 return BOOT_DEVICE_MMC1;
31 #ifdef CONFIG_SPL_MMC_SUPPORT
32 u32 spl_boot_mode(const u32 boot_device)
34 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
37 return MMCSD_MODE_RAW;
42 void board_init_f(ulong dummy)
44 const struct cm_config *cm_default_cfg = cm_get_default_config();
47 ret = spl_early_init();
51 socfpga_get_managers_addr();
53 #ifdef CONFIG_HW_WATCHDOG
54 /* Ensure watchdog is paused when debugging is happening */
55 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
56 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
58 /* Enable watchdog before initializing the HW */
59 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
60 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
64 /* ensure all processors are not released prior Linux boot */
65 writeq(0, CPU_RELEASE_ADDR);
67 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
72 /* configuring the HPS clocks */
73 cm_basic_init(cm_default_cfg);
75 #ifdef CONFIG_DEBUG_UART
76 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
80 preloader_console_init();
81 cm_print_clock_quick_summary();
85 /* disable ocram security at CCU for non secure access */
86 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
87 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
88 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
89 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
91 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
94 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
96 debug("DRAM init failed: %d\n", ret);
103 #ifdef CONFIG_CADENCE_QSPI