arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <hang.h>
   8 #include <asm/io.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <common.h>
  12 #include <debug_uart.h>
  13 #include <image.h>
  14 #include <spl.h>
  15 #include <asm/arch/clock_manager.h>
  16 #include <asm/arch/firewall.h>
  17 #include <asm/arch/mailbox_s10.h>
  18 #include <asm/arch/misc.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/arch/system_manager.h>
  21 #include <watchdog.h>
  22 #include <dm/uclass.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 u32 spl_boot_device(void)
  27 {
  28         /* TODO: Get from SDM or handoff */
  29         return BOOT_DEVICE_MMC1;
  30 }
  31
  32 #ifdef CONFIG_SPL_MMC_SUPPORT
  33 u32 spl_boot_mode(const u32 boot_device)
  34 {
  35 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  36         return MMCSD_MODE_FS;
  37 #else
  38         return MMCSD_MODE_RAW;
  39 #endif
  40 }
  41 #endif
  42
  43 void board_init_f(ulong dummy)
  44 {
  45         const struct cm_config *cm_default_cfg = cm_get_default_config();
  46         int ret;
  47
  48         ret = spl_early_init();
  49         if (ret)
  50                 hang();
  51
  52         socfpga_get_managers_addr();
  53
  54 #ifdef CONFIG_HW_WATCHDOG
  55         /* Ensure watchdog is paused when debugging is happening */
  56         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  57                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  58
  59         /* Enable watchdog before initializing the HW */
  60         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  61         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  62         hw_watchdog_init();
  63 #endif
  64
  65         /* ensure all processors are not released prior Linux boot */
  66         writeq(0, CPU_RELEASE_ADDR);
  67
  68         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  69         timer_init();
  70
  71         sysmgr_pinmux_init();
  72
  73         /* configuring the HPS clocks */
  74         cm_basic_init(cm_default_cfg);
  75
  76 #ifdef CONFIG_DEBUG_UART
  77         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  78         debug_uart_init();
  79 #endif
  80
  81         preloader_console_init();
  82         cm_print_clock_quick_summary();
  83
  84         firewall_setup();
  85
  86         /* disable ocram security at CCU for non secure access */
  87         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
  88                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  89         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
  90                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  91
  92 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  93                 struct udevice *dev;
  94
  95                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  96                 if (ret) {
  97                         debug("DRAM init failed: %d\n", ret);
  98                         hang();
  99                 }
 100 #endif
 101
 102         mbox_init();
 103
 104 #ifdef CONFIG_CADENCE_QSPI
 105         mbox_qspi_open();
 106 #endif
 107 }