arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <hang.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <asm/u-boot.h>
  12 #include <asm/utils.h>
  13 #include <common.h>
  14 #include <debug_uart.h>
  15 #include <image.h>
  16 #include <spl.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/firewall.h>
  19 #include <asm/arch/mailbox_s10.h>
  20 #include <asm/arch/misc.h>
  21 #include <asm/arch/reset_manager.h>
  22 #include <asm/arch/system_manager.h>
  23 #include <watchdog.h>
  24 #include <dm/uclass.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 u32 spl_boot_device(void)
  29 {
  30         /* TODO: Get from SDM or handoff */
  31         return BOOT_DEVICE_MMC1;
  32 }
  33
  34 #ifdef CONFIG_SPL_MMC_SUPPORT
  35 u32 spl_mmc_boot_mode(const u32 boot_device)
  36 {
  37 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  38         return MMCSD_MODE_FS;
  39 #else
  40         return MMCSD_MODE_RAW;
  41 #endif
  42 }
  43 #endif
  44
  45 void board_init_f(ulong dummy)
  46 {
  47         const struct cm_config *cm_default_cfg = cm_get_default_config();
  48         int ret;
  49
  50         ret = spl_early_init();
  51         if (ret)
  52                 hang();
  53
  54         socfpga_get_managers_addr();
  55
  56 #ifdef CONFIG_HW_WATCHDOG
  57         /* Ensure watchdog is paused when debugging is happening */
  58         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  59                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  60
  61         /* Enable watchdog before initializing the HW */
  62         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  63         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  64         hw_watchdog_init();
  65 #endif
  66
  67         /* ensure all processors are not released prior Linux boot */
  68         writeq(0, CPU_RELEASE_ADDR);
  69
  70         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  71         timer_init();
  72
  73         sysmgr_pinmux_init();
  74
  75         /* configuring the HPS clocks */
  76         cm_basic_init(cm_default_cfg);
  77
  78 #ifdef CONFIG_DEBUG_UART
  79         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  80         debug_uart_init();
  81 #endif
  82
  83         preloader_console_init();
  84         cm_print_clock_quick_summary();
  85
  86         firewall_setup();
  87
  88         /* disable ocram security at CCU for non secure access */
  89         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
  90                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  91         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
  92                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  93
  94 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  95                 struct udevice *dev;
  96
  97                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  98                 if (ret) {
  99                         debug("DRAM init failed: %d\n", ret);
 100                         hang();
 101                 }
 102 #endif
 103
 104         mbox_init();
 105
 106 #ifdef CONFIG_CADENCE_QSPI
 107         mbox_qspi_open();
 108 #endif
 109 }